Advanced, Hardened By Process Microelectronic Products For Next

Honeywell 1Copyright 2009 Honeywell International Inc May be published with permission by JAXA 2009

Advanced, Hardened By Process

Microelectronic Products

For Next Generation Space Systems

October 15, 2009


Presentation Summary

• Introduction

• S150 150nm Rad Hard Process

•SOI CMOS Technology

•Trusted Foundry and Quality

• ASIC Platform And Design Flow

• Standard Products

•Memories

•SerDes

•ADC

•Processors

• Summary


Introduction

Honeywell Is An Experienced, Fully Qualified Supplier Of Space

Microelectronics

- Four Generations Of Digital ASICs For Space

- Over 700 Space ASICs Developed And Flown

- Five Generations Of SRAM Products For Space, From Legacy

256K To Leadership 64M Densities

- ASIC Design Resources Across The USA and Globally

- SOI CMOS Technology Built In Our Trusted Foundry

- QML Certified Products And Processes

- Semiconductor Industry Experienced Management Team


Trusted Foundry Accreditation

Process Name

.7 um

SOI-4

.35 um

SOI-5

150nm

S150

Unclassified

Wafer FabAccredited Accredited Accredited

Classified

Wafer FabAccredited Accredited Accredited

ASIC Design Classified Or Unclassified

Classified Or Unclassified

Classified Or Unclassified

ASIC Design Flow

Several Synopsys Synopsys

ASIC Assembly

Classified Or

Unclassified

Classified Or

Unclassified

Classified Or

Unclassified

ASIC TestClassified Or

Unclassified

Classified Or

Unclassified

Classified Or

Unclassified

Mask Making

In USA In USA In USA

Process

Flows

Digital RH

Mixed Sig. RH

Mixed Sig. RF

High Temp

Digital RH

Mixed Sig. RH

Mixed Sig. RF

High Temp

4LM Rad Hard

6LM Rad Hard

8LM Rad Hard

6LM NV SRAM

Aerial View Of Honeywell Trusted Foundry Campus


SOI CMOS Wafer Processes

Buried SiO2 Layer Provides- Radiation Hardness

- Ultra High Reliability

- Faster Circuits At Same Process Node

- Lower Power At Same ProcessNode

- Excellent Isolation For Mixed Signal ASICs

- Continuous High Temp Operation At 225°C

SOI CMOS

Bulk CMOS

N+ P+ P+

S DG S DG

Silicon Substrate

N+

Silicon Substrate

SiO2

High Capacitance Region Substantially Reduced By Buried Oxide Layer

Bulk CMOS

N+ N+ P+ P+

S DG S DG

SiO2

Silicon Substrate

N+N+

Silicon Substrate

Transistor Cross SectionsProcess Name

SOI-4 SOI-5 S150

Production*Now Thru

2015+Now Thru

2015+Now Thru

2015+

Interconnect4 Level CuAl

4 Level CuAl

4-8 Level CuAl

Gate Length .7 um .35 um 150 nm

Wafer Size 150 mm 150 mm 200 mm

DevicesNCh, PCh,

DMOSNCh, PCh,

DMOSNCh, PCh, MIMCAP

Vdd (V) 3.3-20 3.3 3.3/2.5/1.8

Hardened By

Process Process Process

Process

Flows

Digital RH

Mixed Sig. RH

Mixed Sig. RF

High Temp

Digital RH

Mixed Sig. RH

Mixed Sig. RF

High Temp

4LM Rad Hard

6LM Rad Hard

8LM Rad Hard

6LM NV SRAM

* Assured Source Of Supply To Major Programs For United States Government


Why SOI (Silicon on Insulator)?

• High-Temperature Operation

• Low Leakage, High Isolation resistance & Low Parasitics

• Low Power Operation

• Radiation Hard Operation- Greatly reduced sensitive

volume

- Reduced error rate for unhardened circuits

- Reduced overhead for hardening

- Latch-up immune

• Electro-Optic capability

SOI

Bulk

SOI


Radiation Hardened By Process

• SOI And Radiation Hardness

- Rad Hard By Process – SOI CMOS Wafer Technology Is “Hard”

- Circuit Design And Layout Techniques Implemented To Further Improve Radiation Hardness Total Dose: > 1 X 106 Rad(Si)

Soft Error Rate: 1 X 10-11 Upsets/Bit-day

Transient Dose Rate

• Upset: > 1 X 1011 rad(Si)/S

• Survivability: > 1 X 1012 Rad(Si)/S

Neutron Fluence: 1x1014 N/Cm2

No Latchup

• Performance Benefits

- Minimum Area Required To Meet Rad Requirements

- Improved Speed, Power And Density Reduced Capacitance From SOI Technology

10-30 dB Lower Cross-talk Than Bulk Silicon

Higher Density From Small Cell Design


Advanced Space ASIC Platforms

PlatformHX2000

HMX2000

HX3000

HMX3000

HX5000

HMX5000

Structured Array

SOI CMOS Process

0.7 um 0.35 um 150 nm 150 nm

# Base Arrays 5 4 7 1

Max # I/O 372 472 1000 824

Useable Gates 40-390K* 235-1,200K* 2-15M* 3-5M*

Design IPHoneywell, Customer

Honeywell, Customer

Honeywell SERDES,

Synopsys**

Honeywell Synopsys**

Device TypesNch,Pch, Lincap, DMOS, Inductor,

CrSi Resistor

Nch,Pch, Lincap, DMOS, Inductor,

CrSi Resistor

Nch, Pch, MIMCap

Nch, Pch, MIMCap

Available Now Now Now 2010

* Maximum Number Depends On Mix Of Logic And Memory **From Synopsys DesignWare IP Library


HX5000 ASIC Features• Up to 15M gates• Core operating speed >

500MHz• I/O Speeds 500 MHz• Full military temp (-55C°

to 125C°)• BGA & flip chip high rel

packaging• Standard Cell Library

HX5000: 150-nanometer Rad-Hard Family

Advanced Technology• 200mm (8”) wafers• 150nm gate length• 8 layer metal• Low Power (1.8V core)• I/O Compatibility (3.3/2.5/1.8V)

Rad Hard Performance• Total dose 1Mrad(Si)• SER <1E-11 e/bd• Prompt Dose 1E11 rad(Si)/s • Neutron 1E13 MeVeq n/m2

16Mb SRAM

4Mb SRAM

1Mb MRAM

Structured ASIC

SERDES4 TX

Lanes

4 RX

Lanes

PLL

Block

4 TX

Lanes

4 RX

Lanes

SERDES8HM

SERDES8SM

4 TX

Lanes

4 RX

Lanes

4 TX

Lanes

4 RX

Lanes

8 CH

Common

SERDES8_TOP

4 TX

Lanes

4 RX

Lanes

PLL

Block

4 TX

Lanes

4 RX

Lanes

SERDES8HM

SERDES8SM

4 TX

Lanes

4 RX

Lanes

4 TX

Lanes

4 RX

Lanes

8 CH

Common

SERDES8_TOP

DRVDD DRGND D1 D0 DCO OEB AVDD AGND(5) AVDD CLK- CLK+ AGND(5)

cf 48 47 46 45 44 cf cf 43 42 41 cf cf 40 39 38 37 cf

d_crnr d_vdd d_vdd d_vss d_vss d_ d_ d_ d_vdd d_vss d_vss a_vdd a_vss a_ a_vdd a_vdd a_vss a_vss a_vss a_vdd a_vdd a_clk_ a_clk_ a_vss a_crnr

_d2 io_pc io_pc io io dout dout clkout io_pc io _d3 a_pc a_pc shmit_ a_pc a_pc a_pc _d1 a_pc a a_pc r_hvt r_hvt a_pc _d1

in_hvt

vssfl (2) vssfl

vdddr vdddr vssdr vssdr d1 d0 dco vdddr vssdr vssfl vddfl vssmd oe_b vddmd vddmd vssmd vssfl vssclk vddclk vddclk clkinn clkinp vssclk

s s s s s s

o o o o

d2 PC PC VSSIO PC o d3 o PC VSSA PC PC PC o d1 o PC PC VSSA PC d1

o | o s pwdn 36 PDWN

D2 1 d2 s VDDIO | PC VDDA VDDA a_shmit_in_hvt

d_dout | V V t ad9246 cf (4)

D3 2 d3 s o VSS | VSS o D S a_shmit_in_hvt

d_dout | D S t enc125 cf (4)

D4 3 d4 s VDD | A A a_shmit_in_hvt

d_dout o --|-- vddclk

cf vssfl o d2 pad a_vdda

d_vss_d2 PC vssclk cf

vddfl PC PC power clamp o a_vssa_pc

d_vdd_pc s pad to pkg signal land d1 o vssfl(2) cf

vdddr PC pad name t pad to pkg tie-off land o a_vss_d1

d_vddio_pc I/O name corner pad to vssfl PC vsssha cf

vssdr a_vssa_pc

d_vssio 48 pin no planes pkg wirebond land s rbias 35 RBIAS

D5 4 d5 s V V V V a_bias_r

d_dout S D S D # single wirebond to pkg pin # s cml 34 CML

D6 5 d6 s S D S D #pads a_bias_r

d_dout I I PC vddsha

D7 6 d7 s O O # double wirebond to pkg pin # a_vdda_pc 33 AVDD

d_dout PC vddsha

vssdr PC a_vdda_pc

DR 7 d_vssio_pc cf single wirebond to pkg cavity floor vsssha 32 AGND(5)

GND vssdr V V V a_vssa

d_vssio vssfl vssfl S D S s vin 31 VIN-

vdddr | I/O I/O | S D S a_vin_r

DR 8 d_vddio | | o A A s vip 30 VIN+

VDD vdddr PC o o o o d1 a_vin_r

d_vddio_pc d2 I/O PC vsssha cf

vddfl PC I/O o a_vssa_pc

d_vdd_pc o VSSIO = vssdr d1 o vssfl(2) cf

cf vssfl o d2 I/O VDDIO = vdddr Direction o a_vss_d1

d_vss_d2 vssfl -------------------------------------------------- o I/O VSS = vssfl N PC vssref 29 AGND(5)

D8 9 d8 s o o -------------------------------------------------- vssfl VDD = vddfl W + E a_vssa_pc

d_dout S vddref

D9 10 d9 s o d2 I/O I/O d1 o VSSA = vssmd & vssclk & vsssha & vssref -------------------------------------------------- a_vdda

d_dout -------------------------------------------------- VDDA = vddmd & vddclk & vddsha & vddref s reft 28 REFT

D10 11 d10 s -------------------------------------------------- a_ref_r_hvt

d_dout -------------------------------------------------- --|-- V V s refb 27 REFB

D11 12 d11 s VDD | D S a_ref_r_hvt

d_dout | D S s vref 26 VREF

vssdr PC o VSS | VSS o d1 o o A A a_vref_r

d_vssio_pc | o s sense 25 SENSE

vdddr PC VDDIO | VDDA VDDA a_vref_r

d_vddio | (6) PC vssref cf

cf vssfl o d2 o d2 o PC VSSIO PC o d3 o VSSA PC PC PC PC o d1 o PC VSSA PC o d1 o a_vssa_pc

d_crnr_d2 o o o vssfl cf

s s s s s s a_crnr_d1

d12 d13 or vssfl vssdr vssdr vdddr vdddr spi_sd vssdr vssfl spi_sc spi_ vssfl vssfl vddfl vddfl vssfl vssref vssref vssref vddref vddref

io_dcs lk_dfs csb (2) _db2

d_ d_ d_ d_vss d_vss d_vss d_vdd d_vdd d_ d_vss d_vss a_ a_ a_vss a_vss a_vdd a_vdd a_vss a_vss a_vss a_vss a_vdd a_vdd

dout dout dout _d2 io_pc io io io_pc bidir io _d3 shmit_ shmit_ a_pc a_pc a_pc a_pc _d1 a_pc a ref_d1 a a_pc

in_hvt in_hvt

13 14 15 cf 16 17 18 cf 19 20 21 cf 22 cf cf 23 cf 24

D12 D13 OR DRGND DRVDD SDIO/DCS SCLK/DFS CSB AGND(5) AVDD AGND(5) AVDD

total

25

23

23

24

95

top

bottom

left

right

#I/O

23

23

22

23

91HMXADC9246


HX5000 / S150 Capability

QML Complete:

• QML Certification Received – 4/7/07

• S150H Technology QML Qualification Received –4/22/08

• 16M SRAM QML Qualification Received –4/22/08

• HX5000 QML Qualification Received – 11/18/08

HX5000/S150 Successes:

• PDV 1.6M gates

• QTV 3.9M gates

• 4M SRAM

• 16M SRAM

• 1M MRAM

• Quad SerDes Std Prod

• Customer ASIC 1 6.9M gates




Structured Array Features

• S150-based (0.15µ) ASIC platform combining advantages of gate array with the flexibility of standard cell

- Same wafer technology as HX5000

- Proven memory and PLL macros

- HX5000 ASIC NRE tools and flow

- Up to 15% faster than HX5000

- Provides ASIC NRE cost and schedule advantages

• 3M to 5M usable logic gates

• Dual port SRAM - 1.9M bits

• 10 instances 512x36

• 14 instances 1024x36

• 14 instance 2048x36

• 4 Phase Locked Loops (PLLs)

• 512 signals, many I/O options

Parameter Requirement

Total Ionizing Dose > 1 MRad(Si)

Single-Event-Upset

(Adams’ 90% Worst

Case Environment)

SEU_NORMAL < 1E-8 e/b-d

SEUT1 < 1E-9 e/b-d

SEUT2 < 1E-10 e/b-d

SEUT3 < 1E-11 e/b-d

Single-Event-Latchup Immune

Neutron Irradiation >1E12 Mev eq. n/cm2

Dose-Rate Upset > 1E9 Rad(Si)/s

Dose-Rate Survivability >1E12 Rad(Si)/s


QML Qualified, Synopsys Based HX5000 Design Flow

Chip

Specification

Development

Synthesis

RTL

Design

Verification

Floorplan

Physical

Synthesis

ASIC

Fabrication

Package

Requirements

Test

Requirements

Package

Development

Test

Development

Assembly

Test

Screening

Place and

Route

System

Specification

Development

DFT

QML Design Flow

Trial Place And RouteRTL Refinement

and Optimization

Typical Responsibilities

Customer Customer-Honeywell Honeywell

Working Silicon On

12.4M Gate, 64 Bit

RISC Processor


Validated SERDES Design IP

• Supports Multiple Standards

- 10GE (4x3.125 Gb/s XAUI)

- 10G Fibre Channel (4x3.1875 Gb/s XAUI)

- 1G/2G Fiber Channel

- 1G Ethernet

• Low Power

- 185 mW Per Channel @ 1.8V

- 8 Lanes With A Single VCO

• Ready To License & Design-In Today

- DoD Approved At TRL7

- Completed All Radiation Testing, Exceeding Customer Requirements

- Hard & Soft Macro In 150nm Library Now

• High Signal Integrity

- Superior Distance

FR4 backplane > 1m @ 3.125 Gbps

Infiniband cable > 15m @ 3.125 Gbps

- Margin Increases At Lower Data Rates

- Low jitter

TX DJ = 0.20 UI, TX TJ = 0.33 UI

RX DJ = 0.33 UI, RX TJ = 0.62 UI

- BER Of <1e-14

• Individual Channel Programmability

- Selectable Data Rate

- Selectable Signal Shaping For Optimization Of Individual Channels

Validated SERDES On 150nm Rad Hard Process


SERDES Standard Product

Product Features• Quad SERDES, Redundant Serial I/O

• Parallel Interface Using SSTL2 I/O

• 468 Pin LGA Package

• Evaluation Board, Data Sheet, Users

Manual And Pricing Available Now

Protocol Support• 1 To 3.1875 Gb/Sec For General Backplane

Applications

• 1G/2G/10G (XAUI ) Fibre Channel

• 1G And 10G (XAUI) Ethernet

JTAG MDC/MDIO CMU

(PLL and

Clocks)

Configuration

and Control

Registers

4 Channels Port A

4 Channels Port B

RX 2:1 MUX

4 Channels Port A

4 Channels Port B

Parallel Interface

4 Channels

4 Channels

RX 8

8

8

8

RXD_0

RXD_1

RXD_2

RXD_3

TX 8

8

8

8

TXD_0

TXD_1

TXD_2

TXD_3

Port A RX Diff Pairs TX Diff Pairs

8

8

8

8

8

8

8

8

RX0_A

RX1_A

RX2_A

RX3_A

TX0_A

TX1_A

TX2_A

TX3_A

Port B RX Diff Pairs TX Diff Pairs

8

8

8

8

8

8

8

8

RX0_B

RX1_B

RX2_B

RX3_B

TX0_B

TX1_B

TX2_B

TX3_B


SERDES Evaluation Kit

• Contents- 8 Channel SERDES Board

- Cables

- Software and Documentation

• Mates To Existing Backplane For At Speed Characterization

• Multiple Programmable Configuration Interfaces

- External USB

- External MDC/MDIO

- FPGA

- On-board Jumpers

• Xilinx4 FPGA Interface To SERDES via

SSTL2 Bus - Use Application Code With SERDES


Static RAM Product Family Overview

Organization Package Delivery Spec Sheet

HX6256 256K (x8) 28 DIP, FP Now www.honeywell.com/radhard

HLX6256 256K (x8) 28 DIP, FP Now www.honeywell.com/radhard

HX6228 1M (x8) 32 Or 40 FP Now www.honeywell.com/radhard

HLX6228 1M (x8) 32 Or 40 FP Now www.honeywell.com/radhard

HX6408 4M (x8) 36 FP Now www.honeywell.com/radhard

HXS6408 4M (x8) 36 FP Now www.honeywell.com/radhard

HXSR01608 16M (x8) 40 FP Now www.honeywell.com/radhard


HXNV0100 1M (x16) 64 CQFP EM Now www.honeywell.com/radhard


QML Qualified Memories For Space Applications


Rad-Hard 16Mbit SRAM

• Designed For Radiation Sensitive Environments

• Available as 2M x 8 or 512K x 32

• SEU Hardened With No Internal EDAC Implemented

• Target Applications - Reconfigurable Space Processors

- Payload Computers

- Navigation Computers

• Key Specifications- Organization: 2M x 8 or 512K x 32

- Operation: Asynchronous

- Access Time: 13ns Typ @ 1.8V, 25oC

- Core Voltage: 1.8 Volts

- I/O Voltage: 2.5 / 3.3 Volts

- Package: 40 Pin Flatpack x8 Option86 Pin Flatpack x32 Option

- Power (50MHz, x8 option): < 270mW @ 25oCStandby Current: < 5mA @ 25oC


Rad-Hard 4Mbit SRAM

• Manufactured on 150nm technology

• Form, Fit, and Function of existing HX6408

• Faster Access Times

• Lower Dynamic Power

• Key Specifications

- Organization: 512k x 8

- Operation: Asynchronous

- Access Time: <10ns typical

- Supply Voltage: 3.3 Volts

- I/O Voltage: 2.5 / 3.3 Volts

- Package: 36 Lead Flatpack

- Dynamic Current: <1mA/MHz


HXSR06432 64M SRAM Memory Module

• Uses A 4-High Stack Of 512K X 32 SRAM Die

• Configured As 2M X 32

• 86 Lead Flatpack

- 1.23 X 0.96 X 0.19 In

- Vs 16M SRAM:1.13 X 0.85 X 0.16 In

- Saves 75% Of Board Space

• Engineering Model Orders Now

• Production Upgrade Q4 2009

HXSR06432 SRAM Module


HXNV0100 1M Non Volatile MRAM Product

• 64K X 16-bit Non-volatile Memory- No Data Loss On Power Down Or Power

Interruption

• Radiation Hardened For Strategic Applications

• 0.15 micron Silicon-On-Insulator process

• No Wear Out - Unlimited Writes

• Non-destructive Readout (NDRO)

• Magneto-resistance (MRAM) Memory Bits

• Magnetically-shielded 64-pin Ceramic Package

• Error Correction Code (ECC)- Single EDAC Per Address

• Performance- < 70 nS Read Cycle Time

- < 100 nS Write Cycle Time

- < 500 mW Active Power

- < 100 mW Standby Power

- 1.8V Core And 3.3v I/O


HMXADC9225 12-bit A/D Converter

• Radiation Hardened Monolithic 12-bit A/D Converter• 25 MSPS, 4 Stage Pipeline Architecture• On-chip Sample-and-hold Amplifier • Single +5volt Analog Supply• 5V Or 3.3V Digital Tri-state I/O• Requires External 1-2 Volts Vref • 28-lead Space Qualified Ceramic Package

• Performance- Rad Hard to >1M Rad(Si) TID- No Latchup - No Missing Codes Guaranteed- Differential Non-Linearity Error: 0.4 LSB- Straight Binary Output Data- Signal-to-Noise and Distortion Ratio: 69.6 db- Spurious-Free Dynamic Range: - 81 db- Typical Low Power: 345mW


14-bit A/D Converter (HMXADC9246)

• Conversion of Commercial AD9246 To Honeywell’s Rad Hard S150 Process

• 14-bit Pipeline A/D

• Sample Rate Up To 125 MSPS

• Power Supplies- 1.8V analog supply

- 1.8 to 3.3V output supply

• Flexible analog input- 1V p-p to 2V p-p input range

In Design Now, Ready To Sample In Mid 2010


RHPPC - Based on Freescale PowerPC 603e

• 32 Bit Microprocessor

• Licensed From Freescale Semiconductor

• 100% Compatible With Freescale Power PC 603e Processor

- Operating System

- Software Development Tools

- Function

• Key Specifications- Core frequency up to 80 MHz

- Programmable integrated PLL

- Power Supply = 3.3 V ± 0.3 V

- Power Dissipation: 7.6W max, 3.6V, 125°C, (GCLK=80 MHz, SYSCLK=20MHz)

- Radiation Performance

Total Ionizing Dose: >300krad(Si)

Soft Error Rate: <1.5x10-5 Upsets/processor-day

- Up to five instructions in execution per cycle.

- Single cycle throughput for most instructions

Five independent execution units and two register files

- Branch Processing Unit (BPU) for static branch prediction

- Integer Unit with 32 32-bit General Purpose Registers (GPR)

- Fully IEEE 754-compliant Floating Point Unit (FPU) with 32 32-bit Floating Point Registers (FPR),

- Load Store Unit (LSU) for data transfer between data cache and GPRs and FPRs

- System Register Unit (SRU) that executes condition register (CR), special-purpose register (SPR) instructions, and integer add/compare instructions


Radiation Hard Analog and Digital SSI components

-RS422 Driver

-RS422 Receiver

-LVDS Driver

-LVDS Receiver

-Quad Nand Gate

-BUS Transceiver

-Analog Multiplexer

-Comparator

-Dual Operational Amplifier

-Digital to Analog Converter

Honeywell is currently productizing the following production SOI CMOS rad hard digital and analog SSI components:


ASIC Test Capability

• Testing Capabilities High Speed Digital To 3+ Gbps

High Pincount To 1024 Pins

High Density Memory

Precision Analog

Multiple Burn-In Test Systems

• Certifications MIL-PRF-38535 (QML)

Class Q/B Tactical Devices

Class S/V Space Devices

MIL-STD-883 Screening

For Testing Classified Products

• In House Test Engineering Team

• Advanced Tester Systems

ITS9000 CX Digital – 320 I/O @ 80MHz For HX2000

ITS9000 FX Digital – 320 I/O @ 100MHz For HX3000

ITS9000 EXA8000-300 – 960 I/O @ 800 Mbps For HX5000

AEHR ATX3200, MCC HPB5 And EJ Systems For Burn-In

ITS9000 EXA8000-300 High Speed Tester For Testing Classified or

Unclassified ASICs With Up To 960 I/O At Speeds Up To 800 Mbps


ASIC Assembly Capability

• Plant Large Assembly Facility

Class 1000 Clean Rooms

Class 100 Hoods For Inspection And Lid Seal

Continuous Environmental Monitoring

• Certifications QML (MIL-PRF-38535) For SCP & MCMs

Class Q/B Tactical And Class S/V Space Devices

DSCC (MIL-STD-883) Screening Test Methods

Assemble Classified Products

• In House Package Design Engineering Team ASIC Assembly Facility


Summary

• Honeywell Is An Experienced, Fully Qualified Supplier Of Space

Microelectronics, Ready To Work Directly With You To Apply Our

Capabilities To Your Programs

- Four Generations Of Digital ASICs For Space

- Strategic Partnership With Synopsys Design Automation

- Over 700 Space ASICs Developed And Flown

- 12.4M Gate, 64 Bit RISC Processor Built On HX5000 In 2008

- Five Generations Of SRAM Products For Space, From Legacy

256K To Leadership 64M Densities

- ASIC Design and Verification Resources

- SOI CMOS Technology Built In Our Trusted Foundry

- QML Certified Products And Processes

- Semiconductor Industry Experienced Management Team

Advanced, Hardened By Process Microelectronic Products For Next

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