Advanced Digital Design Asynchronous Design: DI Methods by A. Steininger and M. Delvai Vienna...

Advanced Digital DesignAdvanced Digital DesignAsynchronous Design: DI MethodsAsynchronous Design: DI Methods

by A. Steininger and M. DelvaiVienna University of Technology

Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 2

OutlineOutline

Delay Insensitive design - principleDelay Insensitive design - principle NULL-Convention LogicNULL-Convention Logic Code conditions for DI logicCode conditions for DI logic Four-State LogicFour-State Logic Evaluation of async. design stylesEvaluation of async. design styles

Bundled DataBundled Data NULL-Convention LogicNULL-Convention Logic Four-State LogicFour-State Logic


„ „The control flow requires agreement The control flow requires agreement between source and sink. For this between source and sink. For this purpose they need to purpose they need to communicatecommunicate““

Source indicates capture conditionSource indicates capture condition for sink. for sink.

Sink indicates issue condition Sink indicates issue condition for source. for source.

Asynchronous PhilosophyAsynchronous Philosophy

„HANDSHAKE“

recall


Handshake PrincipleHandshake Principle

SRC SNK f(x) f(x)

When it is valid and consistent

When SNK has consumed the previous one

When can SNK use its input?

When can SRC apply the next input?

REQ: „Data word valid, you can use it“

ACK: „Data word consumed, send the next“

recall


A very Important DetailA very Important Detail

The handshake establishes a The handshake establishes a closed-loop controlclosed-loop control for the data flow for the data flow between sender and receiverbetween sender and receiver

This makes operation more robust than in This makes operation more robust than in the synchronous (= open-loop) casethe synchronous (= open-loop) case

The art of asynchronous design is to make The art of asynchronous design is to make many of these closed loops interoperate many of these closed loops interoperate properlyproperly

This is much more complicated than a This is much more complicated than a synchronous design.synchronous design.

recall


Very disappointing…Very disappointing…

For a closed loop we need to For a closed loop we need to measuremeasure the quantity of interest the quantity of interest

So far we have not done that:So far we have not done that: We have not measured validity & We have not measured validity &

consistencyconsistency We have used time as an We have used time as an

indirectindirect measure instead measure instead Thus Bounded Delay methods do not Thus Bounded Delay methods do not

provide the benefits of a closed loopprovide the benefits of a closed loop BUT: Can we measure validity & BUT: Can we measure validity &

consistency at all?consistency at all?


Criticality of ACKCriticality of ACK

cannot measure „act of latching“ as an eventcannot measure „act of latching“ as an event use latching use latching commandcommand instead instead fork produces race between fork produces race between trigger processtrigger process

and and next data wavenext data wave race is uncritical (but still exists!)race is uncritical (but still exists!)

SRC SNK f(x) f(x) FF2

„„latch!“latch!“

recall


Criticality of REQCriticality of REQ

SRC SNK f(x) f(x)

cannot use issue trigger as an event:cannot use issue trigger as an event: produces unacceptable race between produces unacceptable race between

datadata and and REQREQ must introduce timer (bounded delay)must introduce timer (bounded delay) OR: find better event (downstream)OR: find better event (downstream)

completion detectioncompletion detection

recall


Completion DetectionCompletion Detection

In order to judge when data are valid & In order to judge when data are valid & consistent we need to be able to see consistent we need to be able to see when this is NOT the casewhen this is NOT the case

not possible with Boolean logicnot possible with Boolean logic need representation for INVALIDneed representation for INVALID an ACK in parallel to data (bundled data) an ACK in parallel to data (bundled data)

will always cause a racewill always cause a race need more than two signal states for need more than two signal states for

every individual bit (!)every individual bit (!) need more than one rail per bitneed more than one rail per bit


Multi-level LogicMulti-level Logic

use more than two (e.g. three) voltage use more than two (e.g. three) voltage levels per raillevels per rail

allows to express „invalid“ in the currently allows to express „invalid“ in the currently „forbidden“ area between HI and „LO“„forbidden“ area between HI and „LO“

requires two thresholds for every gate requires two thresholds for every gate inputinput

output must be able to drive three different output must be able to drive three different levels reliablylevels reliably

causes substantial technological problemscauses substantial technological problems

not further pursuednot further pursued


Our OptionsOur Options

We must only use consistent input We must only use consistent input vectorsvectors

How can we tell an input vector is How can we tell an input vector is consistent?consistent?

(1) use TIME to mark consistent phases(1) use TIME to mark consistent phases synchronous approach / global time basesynchronous approach / global time base asynchronous/bounded delayasynchronous/bounded delay

(2) use CODING to add information(2) use CODING to add information asynchronous/delay insensitiveasynchronous/delay insensitive

recall


TerminologyTerminology

consistent DW: all bits belong to the same context

valid signal: result of function applied to consistent DW

recall


Add the value NULL to the alphabetAdd the value NULL to the alphabet

Signal Signal XX

X.aX.a X.bX.b meaningmeaning

00 00 NULL (N)NULL (N)

00 11 TRUE (T)TRUE (T)

11 00 FALSE (F)FALSE (F)

11 11 illegalillegal

X X.a

X.b

two-rail coding:

NULL Convention LogicNULL Convention Logic

„„DATA“DATA“


TT FF NN

TT TT FF NN

FF FF FF NN

NN NN NN NN

AND TT FF NN

TT TT TT NN

FF TT FF NN

NN NN NN NN

OR

TT FF

FF TT

NN NN

NOT

NCL FunctionsNCL Functions

naive approach: if any input is „N“ then output „N“


NCL Flow ControlNCL Flow Control

NULL waves enframe DATA wavesNULL waves enframe DATA waves

Completion detection = Completion detection = check wether all bits are „DATA“ check wether all bits are „DATA“ (completeness of DATA)(completeness of DATA)

NULL

NULL

NULL

TRUE

TRUE

FALSE

TRUE

NULL

NULL

NULL

NULL

TRUE

FALSE

TRUE

FALSENULL

tconsistent DATAconsistent DATA


Still Problems …Still Problems …

What about this situation?What about this situation?

Fast bits may catch up with a slow bit from Fast bits may catch up with a slow bit from the previous word. the previous word. The word containing The word containing the „old“ bit is considered consistent!the „old“ bit is considered consistent!

NULL

NULL

NULL

TRUE

TRUE

FALSE

TRUE

NULL

NULL

NULL

TRUE

TRUE

FALSENULL


DATA DATANULLNULLoutput


Solution PrincipleSolution Principle

Enforce „completeness of NULL“ as Enforce „completeness of NULL“ as well:well: The output must not go to NULL before The output must not go to NULL before allall

inputs have changed to NULLinputs have changed to NULL In a closed loop configuration this keeps the In a closed loop configuration this keeps the

slow paths in synchrony with the fast onesslow paths in synchrony with the fast ones

We need different truth table when We need different truth table when output is NULLoutput is NULL


TT FF NN

TT TT FF NN

FF FF FF NN

NN NN NN NN

AND TT FF NN

TT TT FF DD

FF FF FF DD

NN DD DD NN

AND

Two Truth TablesTwo Truth Tables

for DATA wavesfor DATA waves for NULL wavesfor NULL waves

D … DATA D … DATA (T or F)(T or F)

must hold output in last valid state before new input is complete

need „hysteresis“ need to consider current output in truth table


AB

Y‘

NN FF TT

NN TT FF NN TT FF NN TT FF

NN TT FF NN TT FF NN TT FF NN TT FF NN TT FF NN TT FF NN TT FF NN TT FF NN TT FF

NN NN NN NN TT FF NN FF FF NN FF FF FF FF FF FF FF FF NN TT TT TT TT TT TT TT TT

Y

YAB

Y‘

TF

FNN

N

FN

A

&

Feedback GateFeedback Gate

unstable (Y Y‘)


No more Problems …No more Problems …

Have we solved the problem?Have we solved the problem?

YES! The output now remains at DATA with the YES! The output now remains at DATA with the slowest bit, thus inhibiting (via the closed loop) slowest bit, thus inhibiting (via the closed loop) the fast bits to convey the next DATA wave.the fast bits to convey the next DATA wave.

NULL

NULL

NULL

TRUE

TRUE

FALSE

TRUE

NULL

NULL

NULLNULL


DATANULLoutput


The desired hysteresis requires an NCL The desired hysteresis requires an NCL gate to gate to holdhold its output until its output until all inputs are DATA orall inputs are DATA or all inputs are NULLall inputs are NULL

need storage need storage capability (or capability (or feedback loop) feedback loop) even in combi-even in combi-national gatenational gate

Mem

X1.a

X1.bX1

X2.a

X2.bX2

Y.aY.b

Y

Mem

NCL GatesNCL Gates


[G. Sobelmann, K. Fant: CMOS Circuit Design of Threshold Gates with Hysteresis]

p- and n-stack not dual

memory cell at output

A

NCL Gate ImplementationNCL Gate Implementation

Mem

X1.a

X1.bX1

X2.a

X2.bX2

Y.aY.b

Y

Mem

figure shown for one output rail only

CMOS-Transistors only

but no standard cells


The Charme of NCLThe Charme of NCL

self-regulating data flowself-regulating data flow in a NULL initialized circuit a DATA front in a NULL initialized circuit a DATA front

will propagate towards the outputwill propagate towards the output alternating waves of NULL and DATA alternating waves of NULL and DATA

pace the data flow (which, in some pace the data flow (which, in some sense, forms the „clock“)sense, forms the „clock“)

based on direct assessment of based on direct assessment of validity & consistencyvalidity & consistency

no delay assumptions necessary no delay assumptions necessary (ideally), no „worst case“, …(ideally), no „worst case“, …

globally applicable solutionglobally applicable solution


Validity and ConsistencyValidity and Consistency

Consistency Consistency (multiple bits @ input)(multiple bits @ input) all bits that are combined are valid all bits that are combined are valid

and belong to the same contextand belong to the same context

Validity Validity (single bit @ output)(single bit @ output) the bit is the stable result of a the bit is the stable result of a

combination of consistent bitscombination of consistent bits

Consistency implies validity (per Consistency implies validity (per definition) but NOT vice versa!definition) but NOT vice versa!


Val. & Consistcy. in NCLVal. & Consistcy. in NCL Validity:Validity:

output is changed only when consistent output is changed only when consistent input is available („hold“ in truth table)input is available („hold“ in truth table)

coding ensures direct transistion from coding ensures direct transistion from valid code to another (NULL is valid but valid code to another (NULL is valid but spacer only)spacer only)

continuous validitycontinuous validity Consistency:Consistency:

NULL spacer between DATA waves NULL spacer between DATA waves allows identification of contextallows identification of context

synchronization of context by virtue of synchronization of context by virtue of „completeness of NULL“ condition„completeness of NULL“ condition


What about sync. & BD?What about sync. & BD?

TimingTiming ensures that every data item ensures that every data item is both valid and consistent at the is both valid and consistent at the time it is used:time it is used: choice of clock period (sync)choice of clock period (sync) choice of delay values (BD)choice of delay values (BD)

In contrast to NCL (temporary) In contrast to NCL (temporary) invalidity of data is admitted.invalidity of data is admitted.

No explicit measures (other than No explicit measures (other than timing) are taken/necessary to cope timing) are taken/necessary to cope with these issues.with these issues.


synchronous modelsynchronous model known bounds for delays, global timingknown bounds for delays, global timing

bounded delay model (fundamental)bounded delay model (fundamental) known bounds for known bounds for absoluteabsolute delays, local timing delays, local timing

scalable-delay-insensitive modelscalable-delay-insensitive model bounds for bounds for relativerelative deviation between delays known deviation between delays known

quasi-delay-insensitivequasi-delay-insensitive output paths of a fork have same delayoutput paths of a fork have same delay

delay insensitivedelay insensitive no restrictionsno restrictions on delays (just finite) on delays (just finite)

Softening the restrictionsSoftening the restrictionsrecall


validity & consistency validity & consistency directlydirectly visible visible no timing assumptions requiredno timing assumptions required (ideally) (ideally) „ „delay insensitive“ (ideally)delay insensitive“ (ideally) suitable for CMOS implementationsuitable for CMOS implementation coding of one bit on two railscoding of one bit on two rails 2 memory cells per combinational output2 memory cells per combinational output efficiency: 50% of the data flow areefficiency: 50% of the data flow are

unproductive NULL waves unproductive NULL waves patented und industrially usedpatented und industrially used

NCL: A Brief SummaryNCL: A Brief Summary


Our OptionsOur Options

We must only use consistent input We must only use consistent input vectorsvectors

How can we tell an input vector is How can we tell an input vector is consistent?consistent?

(1) use TIME to mark consistent phases(1) use TIME to mark consistent phases synchronous approach / global time basesynchronous approach / global time base asynchronous/bounded delayasynchronous/bounded delay

(2) use CODING to add information(2) use CODING to add information asynchronous/delay insensitiveasynchronous/delay insensitive

recall

ARE THERE OTHER CODING OPTIONS?


(C1) Identification of every context switch(C1) Identification of every context switchIt must be possible to clearly separate two It must be possible to clearly separate two successive data words under all successive data words under all circumstancescircumstances

(C2) Unique context membership(C2) Unique context membershipThe transition from one valid code word to The transition from one valid code word to the next must be unambiguous, i.e. no the next must be unambiguous, i.e. no intermediate state may be a valid codeintermediate state may be a valid code

Conditions for DI CodingConditions for DI Coding



Conditions for DI codingConditions for DI coding

0,0,0 0,0,0

?




0,0,0 1,0,0 1,0,1 1,1,1

?


(C1) Return to NULL forces separation (C1) Return to NULL forces separation between successive data waves between successive data waves

(C2) Coding scheme (C2) Coding scheme guarantees direct guarantees direct switch from one switch from one legal value to next legal value to next (only one rail changes!)(only one rail changes!)

Signal Signal XX

X.aX.a X.bX.b valuevalue

00 00 NULLNULL

00 11 TRUETRUE

11 00 FALSEFALSE

11 11 illegalillegal

What about NCL‘s CodingWhat about NCL‘s Coding


AA BB YY

00 00 00

00 11 00

11 00 00

11 11 110

,1

1,0

NU

LL

&A

B

Y

NU

LL

0 0N N

NU

LL

N

Synchronization of WavesSynchronization of Waves

no glitch!no glitch!successive successive „0“s clearly „0“s clearly separableseparable


Transition SignalingTransition Signaling

NULL-Convention LogicNULL-Convention Logic

NCL vs. Trans. SignalingNCL vs. Trans. Signaling

A0

A1

A=0 A=1 A=1 A=1 A=0

A0

A1

A=0 A=1 A=1 A=1 A=0


More Efficient Coding?More Efficient Coding?

NCL employs a 4-phase (RTZ) version NCL employs a 4-phase (RTZ) version of transition signaling.of transition signaling.

The „return to zero“ is due to the The „return to zero“ is due to the NULL waves.NULL waves.

The NULL waves are unproductive The NULL waves are unproductive and hence undesired.and hence undesired.

Can we employ 2-phase (NRZ) Can we employ 2-phase (NRZ) transition signaling instead?transition signaling instead?


Four-State Logic (FSL)Four-State Logic (FSL)

Use Use 2 codes per logic value2 codes per logic value

X X.a

X.b

two-rail coding:


Alternate code sets („phase“)Alternate code sets („phase“)

Completion detection: Check whether Completion detection: Check whether all bits belong to the same phaseall bits belong to the same phase

A

H

L

H

h

l

l

h

L

L

H

H

l

l

h

hH

tkonsistent phase 0consistent phase 1

NULL

NULL

NULL

TRUE

TRUE

FALSE

TRUE

NULL

NULL

NULL

NULL

TRUE

FALSE

TRUE

FALSENULL

NCLFSL

FSL Flow ControlFSL Flow Control


FSL AND-Gate: Truth TableFSL AND-Gate: Truth Table

YY ll hh LL HH

ll ll ll ** **

hh ll hh ** **

LL ** ** LL LL

HH ** ** LL HH

IN_1IN_1

IN_2IN_2

* … hold last valid output


Four-State Logic (FSL)Four-State Logic (FSL)

An FSL gate An FSL gate holdsholds its output until its output until all inputs are in the same phaseall inputs are in the same phase

need storage need storage capability (or capability (or feedback loop) feedback loop) even in combi-even in combi-national gatenational gate

Mem

X1.a

X1.bX1

X2.a

X2.b

X2

Y.aY.b

Y

Mem


(C1) Phase change forces separation (C1) Phase change forces separation between successive data waves between successive data waves

(C2) Coding scheme (C2) Coding scheme guarantees direct guarantees direct switch from one switch from one legal value in onelegal value in onephase to legal valuephase to legal valuein next phasein next phase(only one rail changes!)(only one rail changes!)

FSL and Code ConditionsFSL and Code Conditions

Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 43A

AA BB YY

00 00 00

00 11 00

11 00 00

11 11 110

,1

1,0

&A

B

Y

0 0

0 1

Synchronization of WavesSynchronization of Waves

no glitch!no glitch!successive successive „0“s clearly „0“s clearly separableseparable


FSL retains all the charme of NCLFSL retains all the charme of NCL FSL provides double data throughputFSL provides double data throughput

implementation of 4-phase schemeimplementation of 4-phase scheme tends to require more efforts (remains tends to require more efforts (remains to be investigated) to be investigated)

FSL: A Brief SummaryFSL: A Brief Summary

Evaluation of PropertiesEvaluation of PropertiesBounded Delay & Delay Insensitive Bounded Delay & Delay Insensitive Asynchronous Design MethodsAsynchronous Design Methods


Ideal Design MethodIdeal Design Method

An ideal design method …An ideal design method … minimizes power consumptionminimizes power consumption miminizes circuit overheadmiminizes circuit overhead naturally supports composabilitynaturally supports composability naturally aids testabilitynaturally aids testability yields robust circuitsyields robust circuits yields fast circuits.yields fast circuits.

recall


! Area Efficiency BD! Area Efficiency BD

%100

CtrlF

Farea AA

AE

area proportion devoted to intended logic function

0 (handshake logic negligible)


! Area Efficiency NCL! Area Efficiency NCL

%33...50

CtrlF

Farea AA

AE

* [Smith & Ligthart ASP-DAC 2001]

overheads for overheads for flow control (Micropipeline)flow control (Micropipeline) two-rail codingtwo-rail coding storage cellsstorage cells

sum up to about sum up to about 500% 500% AAFF with standard cells with standard cells

100%...200% 100%...200% AAFF with custom cells (*) with custom cells (*)


! Area Efficiency FSL! Area Efficiency FSL

%29...40

CtrlF

Farea AA

AE

overheads similar to NCL but NULL overheads similar to NCL but NULL state tends to result in more conveni-state tends to result in more conveni-ent implementation than second phaseent implementation than second phase

rough estimation:rough estimation: 600% 600% AAFF with standard cells with standard cells

150%...250% 150%...250% AAFF with custom cells with custom cells


Area Efficiency - ComparisonArea Efficiency - Comparison

Area EfficiencyArea Efficiency

sync.sync. 50%50%

BDBD 100%100%

NCLNCL 50…33%50…33%

FSLFSL 40…29%40…29%


Area Efficiency: SummaryArea Efficiency: Summary

Asynchronous circuits save the need for Asynchronous circuits save the need for the clock network, but require the clock network, but require (relatively little) area for handshaking.(relatively little) area for handshaking.

In addition DI circuits cause substantial In addition DI circuits cause substantial circuit overheads for coding and circuit overheads for coding and completion detection.completion detection.

These overheads outweigh the savings These overheads outweigh the savings for the clock tree, hence BD circuits for the clock tree, hence BD circuits promise the most area savings promise the most area savings (the (the delay, however, is diffcult to implement)delay, however, is diffcult to implement)


! Power Efficiency BD! Power Efficiency BD

FFtot PPP )1.01()1(

dissipated power (total)

static part

dynamic part

assumption: handshaking increases dynamic power

by 10%

power for intended function

99.01.01

pwrE

%90

)0(10

%)10(%50

%)100(%92

circuit utilization


! Power Efficiency NCL! Power Efficiency NCL

FFtot PPP )1.01()1(

logic overhead (2.5)

assumption: handshaking plus completion detection increase dyn. pwr by 10%

9.925.01

pwrE

%90

)0(4

%)10(%8

%)100(%10

coding overhead (2 trans/bit instead

of 0.5 => 4x)


! Power Efficiency FSL! Power Efficiency FSL

FFtot PPP )1.01()1(

logic overhead (3)

assumption: handshaking plus completion detection increase dyn. pwr by 10%

94.53.01

pwrE

%90

)0(3.3

%)10(%11

%)100(%16

coding overhead (1 trans/bit instead

of 0.5 => 2x)


Pwr Efficiency - ComparisonPwr Efficiency - Comparison

=100%=100% =10%=10% 0%0%

sync.sync. 53%53% 5.3%5.3%

BDBD 92%92% 50%50% 1010

NCLNCL 10%10% 8%8% 44

FSLFSL 16%16% 11%11% 3.33.3


Pwr Efficiency: SummaryPwr Efficiency: Summary

Asynchronous circuits save the power Asynchronous circuits save the power consumed by the clock network, and consumed by the clock network, and require less power for handshaking.require less power for handshaking.

The DI circuits‘ additional transitions The DI circuits‘ additional transitions plus their substantial circuit overheads plus their substantial circuit overheads increase energy consumption.increase energy consumption.

In summary the DI overheads outweigh In summary the DI overheads outweigh the savings, hence BD methods are the savings, hence BD methods are most effective for low-power most effective for low-power applications.applications.


! Perform. Efficiency BD! Perform. Efficiency BD

real

com

puta

tion

tim

e

20100 50 1030 20

lib: w

orst

vs.

typ

cros

stal

k, IR

dro

ppro

cess

var

iation

cloc

k sk

ewunbal

ance

d

stag

es

[Cortadella, ICCD’04]

%501

FF

Fperf tt

tE


! Perform. Efficiency NCL! Perform. Efficiency NCL

no safety margins necessaryno safety margins necessary

but additional delay but additional delay ttdlydly for: for: ACK path ACK path (feedback required!)(feedback required!) completion detectioncompletion detection additional circuit complexityadditional circuit complexity

and NULL waves halve throughputand NULL waves halve throughput

*%)50(%50)(2

dlyF

Fperf tt

tE

*[Cortadella, ICCD’04]


! Perform. Efficiency FSL! Perform. Efficiency FSL

everything like in NCLeverything like in NCL

but:but: double throughputdouble throughput

%100

dlyF

Fperf tt

tE

*[Cortadella, ICCD’04]


Perf. Effic. - ComparisonPerf. Effic. - Comparison

Perf. EfficiencyPerf. Efficiency

sync.sync. 44%44%

BDBD < 50%< 50%

NCLNCL < 50 %< 50 %

FSLFSL < 100%< 100%


! Composability! Composability

BD is similar to the synchronous case: BD is similar to the synchronous case: Delays must be adjusted just like the clockDelays must be adjusted just like the clock

DI circuits work DI circuits work under all conditionsunder all conditions, , interface spec can be reduced to the interface spec can be reduced to the function (plus handshake protocol).function (plus handshake protocol).

If a If a certain execution timecertain execution time/performance /performance must be guaranteed, however, timing must be guaranteed, however, timing analysis is again necessary. BUT:analysis is again necessary. BUT:

Even if the operation is too slow for any Even if the operation is too slow for any reason, the circuit will not fail to operate!reason, the circuit will not fail to operate!

No metastability issues! Instead handshake No metastability issues! Instead handshake required at all interfaces.required at all interfaces.


How DI is DI?How DI is DI?

Basic cells are Basic cells are internally SDI internally SDI (at best)(at best) Obligatory feedbackObligatory feedback

On module level DIOn module level DI is attainable, but is attainable, but Inevitable (?) forkInevitable (?) fork

makes ACK path makes ACK path „unsafe“„unsafe“

Reg design criticalReg design critical

&


! Robustness! Robustness

All async techniques:All async techniques: timing is distributed, clock no more single timing is distributed, clock no more single

point of failurepoint of failure

DI only:DI only: robust timing due to closed-loop controlrobust timing due to closed-loop control graceful degratation in case of violationgraceful degratation in case of violation multi-rail coding of signalsmulti-rail coding of signals

complexity of interacting control loopscomplexity of interacting control loops larger arealarger area


Syn versus FSLSyn versus FSL

synsyn

FSLFSL

Fault Fault injectioninjection

[Thesis Rahbaran]


! Testability! Testability

Scan chain is an extremely powerful Scan chain is an extremely powerful concept; hard to beatconcept; hard to beat

Asynchronous circuits (including BD) Asynchronous circuits (including BD) are said to be much harder to testare said to be much harder to test

Only punctual concepts and ad-hoc Only punctual concepts and ad-hoc solutions availablesolutions available


Further PropertiesFurther Properties

„„Correctness by design“ (DI only)Correctness by design“ (DI only)

Beneficial EMR behaviorBeneficial EMR behavior

Conceptual elegance (DI only)Conceptual elegance (DI only)

Readiness for future technologies Readiness for future technologies (quantum, bio, optical, …)(quantum, bio, optical, …)


need to determine clock periodneed to determine clock period circuit functionality is technology dependent circuit functionality is technology dependent considerable design efforts, large design considerable design efforts, large design

loopsloops need to make worst-case assumptionsneed to make worst-case assumptions

necessarily pessimisticnecessarily pessimistic no robustness wrt. exceeding themno robustness wrt. exceeding them

need to maintain global synchronyneed to maintain global synchrony clock distribution problemsclock distribution problems power consumption problemspower consumption problems

Gain of Delay InsensitiveGain of Delay Insensitive


Current statusCurrent status

working 16-bit processor „ASPEAR“ working 16-bit processor „ASPEAR“ (on FPGA platform) in FSL (on FPGA platform) in FSL

working design flow based on working design flow based on Synopsys Synopsys

formal investigation of delayformal investigation of delay insensitivity (Modelchecking) insensitivity (Modelchecking)

experimental comparison ofexperimental comparison of robustness:SPEAR versus ASPEAR robustness:SPEAR versus ASPEAR


Our visionsOur visions

autonomous sensor nodeautonomous sensor node no crystal oscillatorno crystal oscillator UART-like communicationUART-like communication low power (by diverse means)low power (by diverse means) high robustness (harsh environments)high robustness (harsh environments)

develop „tailored“ lib cells / ASICdevelop „tailored“ lib cells / ASIC delay insensitive memorydelay insensitive memory (exp.) comparison with other (exp.) comparison with other

approachesapproaches


Conclusion for asyn:Conclusion for asyn:

benefits forbenefits for low activation Applications (low activation Applications ()) high robustnesshigh robustness technologies with unknown timingtechnologies with unknown timing largely varying operatring conditionslargely varying operatring conditions

not good fornot good for small feature sizes (static current!)small feature sizes (static current!) low arealow area real-timereal-time high speed (?)high speed (?)

Advanced Digital Design Asynchronous Design: DI Methods by A. Steininger and M. Delvai Vienna...

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