Advanced Architectures for Predistortion Linearization of...

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J. Stevenson Kenney September 9, 2002 C S T Advanced Architectures for Predistortion Linearization of RF Power Amplifiers J. Stevenson Kenney, Youngcheol Park, and Wangmyong Woo School of Electrical and Computer Engineering Georgia Institute of Technology Presented at The IEEE Topical Workshop on Power Amplifiers September 9, 2002 La Jolla, CA

Transcript of Advanced Architectures for Predistortion Linearization of...

Page 1: Advanced Architectures for Predistortion Linearization of ...pasymposium.ucsd.edu/papers2002/SKenney2002PAWorkshop.pdf · Advanced Architectures for Predistortion Linearization of

J. Stevenson Kenney

September 9, 2002

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Advanced Architectures for Predistortion Linearization

of RF Power Amplifiers

J. Stevenson Kenney, Youngcheol Park, and Wangmyong WooSchool of Electrical and Computer Engineering

Georgia Institute of Technology

Presented atThe IEEE Topical Workshop on Power Amplifiers

September 9, 2002La Jolla, CA

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Acknowledgement

• This work was supported in part by Danam USA, San Jose, CA.

and by

• The Yamacraw Design Center, an economic development project funded by the State of Georgia.

• Thanks also to Sirenza Microdevices, and Ericsson USA for donating the power amplifiers used in this study.

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Outline

• Introduction to Predistortion• LUT Updates using Sub-sampling

Receivers• RF Envelope Predistortion• Summary and Conclusions

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Predistortion Concept

PA response after predistortion algorithm

PA Response

Input operating range without Pre-D

Input operating range with Pre-D

Average power

Peak power

PAPR

This back-off value is determined to give no

significant nonlinear region for peak input power

This back-off value is (Ideal limiter saturation point-PAPR

of input signal)

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Correction Techniques for Cellular Base StationsCorrection Techniques for Cellular Base Stations

Correction Technologies

Correction Capability*

Correction Bandwidth

Relative Cost

Feed Forward 25-35 dB > 100 MHz High

Envelope Feedback 10-20 dB < 5 MHz Med

Analog Pre-Distortion 5-10 dB > 25 MHz Low

Adaptive Pre-D 10-20 dB > 50 MHz Med

Correction Technologies

Correction Capability*

Correction Bandwidth

Relative Cost

Feed Forward 25-35 dB > 100 MHz High

Envelope Feedback 10-20 dB < 5 MHz Med

Analog Pre-Distortion 5-10 dB > 25 MHz Low

Adaptive Pre-D 10-20 dB > 50 MHz Med

* IMD Correction based on 8-Tone Continuous Random Phase

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Predistortion Linearization

Depends on DSP computational

capability

GoodModerateDigital Baseband Pre-D

No I/Q streamrequired

ModerateModerateAdaptive Analog Pre-D

(Work function)

Simple Implementation

LowHighOpen Loop Analog Pre-D

CommentsRelative IMD Correction

BandwidthPredistortionTechnology

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Baseband Pre-DistortionBaseband Pre-Distortion

• Adaptive Filter to Minimize MSE• ADC/DAC Requirements:

– 20 MHz BW ⇒ 100 MHz with 5th order IMD– 3X over sample ⇒ 300 Msps (on both I and Q)

• DSP Speed: >6⋅108 MAC/sec– 0.18 µm CMOS: ~1.5 nW/MAC– ⇒ ~1W DC power– LUT update must also be performed

• Adaptive Filter to Minimize MSE• ADC/DAC Requirements:

– 20 MHz BW ⇒ 100 MHz with 5th order IMD– 3X over sample ⇒ 300 Msps (on both I and Q)

• DSP Speed: >6⋅108 MAC/sec– 0.18 µm CMOS: ~1.5 nW/MAC– ⇒ ~1W DC power– LUT update must also be performed

DSP Pre-D

PAI/Q Stream Input

Σ

DAC

ADC

RF Output

Error Signal

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Adapted from R. H. Walden, Performance Trends for Analog-to-Digital Converters, IEEE Communications Magazine, February 1999, pp. 96 - 101.

Trends in Analog-to-Digital Converter Technology

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Pre-D Results with Low Power Amplifier (0.5W Class-AB GaAs HFET)

Without Pre-D With Pre-D

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Disadvantages of Baseband Pre-D

• Sampling Requirements• DSP speed (power)• Digital I/Q input stream required• LUT update must be performed in

background

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Outline

• Introduction to Predistortion• LUT Updates using Sub-sampling

Receivers• RF Envelope Predistortion• Summary and Conclusions

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Sampling in Predistorters

• A predistorter samples signals at the input and output of a power amplifier to identify its AM-AM, AM-PM characteristics.

PA

RFDownconverter

A/D Converter

Sample & Hold Circuit

DSP

RFDownconverter

A/D Converter

Sample & Hold Circuit

PredistorterInput Signal

ffOutput Signal

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Input Nyquist Rate

• Input Nyquist rate is whenfIF +BW/2=fs-fIF – BW/2

• Again, this is equivalent to the second figure in terms of aliasing

• Therefore, this is 33% of the output Nyquist Rate, considering 3rd order IMD.

0 fs

0 fs’

fIFfs- fIF

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Input Nyquist Rate

• The original signal can be reconstructed from the sampled signal if the signal is sampled so that its spectrum is not overlapped in frequency domain.

∑∞

−∞= −−

=k ss

sss TkTt

TkTtkTxtx

/)(]/)(sin[

)()(π

πwhere os

s

FFT

21

≥=

• Input Nyquist rate is the sampling frequency when the highest frequency of the input signal coincides with the lowest frequency of the image signal.

0 fsfIF fs- fIF

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Output Nyquist Rate

• With predistortion systems, the analog-to-digital conversion at the output of a PA is traditionally done with ‘above’ Output-Nyquist rate in order to avoid the aliasing at the output spectrum.

0fsfIFfL fH fs- fIF fH,i

= fL,i

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Sub-sampling

0 fs=10fIF=2fL fH=3.84

8

fL,i=6.2

fH,i

fs=10MHz

0 fs=5.01fIF=2

fL

fL,i=1.17

fH,i

fs=5.01MHz(67% overlapped)

fs

fIF=2fL fH

BPF

fs<3.55(More than 133% overlapped)

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Sampling Requirements for Nonlinear System Identification

• The goal of the sampling system is the pre-D system is not to reconstruct signals, but to identify the nonlinear distortion.

• Therefore, it is not necessary to do Nyquistrate sampling.

• According to the Generalized Sampling Theorem*, a nonlinear system may be accurately identified if the output signal is sampled at the input Nyquist rate.

*John Tsimbinos, and Kenneth V. Lever, “Sampling Frequency Requirements for Identification and Compensation of Nonlinear Systems,” in Proc. ICASSP, vol. III, 1994, pp. 513-516.

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Basic Operation of the Generalized Sampling Theorem

NonlinearMapping

g(⋅) = f--1 (⋅)

Samplertk=kTs

x(t)y(t) y(tk) g(y(tk)) LPF

NonlinearMapping

f- (⋅)

x(t) y(t) = f(x(t))

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Sub-Sampling ArchitectureADS Simulation

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Sub-Sampling ArchitectureADS Simulations (cont.)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

mag(CH1)

0.0

0.2

0.4

0.6

0.8

1.0

mag

(CH

2)

0 2 4 6 8 10

Mega_Hertz

-150

-100

-50

0

SC

H1

SC

H2

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

mag(CH1)

0.0

0.1

0.2

0.3

0.4

0.5

mag

(CH

2)

0 2 4 6 8 10

Mega_Hertz

-150

-100

-50

0

SC

H1

SC

H2

Figure 1: Simulated AM-AM Characteristic when fs= 10 MHz (includes 3rd order distortions).

Figure 2: Frequency Spectrum when fs = 10 MHz (includes 3rd order distortions).

Figure 3: Simulated AM-AM Characteristic when fs = 5 MHz (70% of output spectrum is overlapped).

Figure 4: Frequency Spectrum when fs = 5 MHz (70% of output spectrum is overlapped).

Input Signal

Aliased Signal

Input Signal

Aliased Signals

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Sub-sampling Architecture Test Bed

IF Filter

Lo

PulseGenerator

LPF

880MHz

S/H Circuit

CH1

HP89410

CH2

ErrPowerAmplifier

PCHP4432

IF Filter

Lo

PulseGenerator

LPF

880MHz

S/H Circuit

CH1

HP89410

CH2

ErrPowerAmplifier

PCPCHP4432HP4432

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Measurement Results

0

0.1

0.2

0.3

0.4

0.5

0 0.1 0.2 0.3 0.4 0.5 0.6

Vin [V]

Vo

ut

[V]

0

0.1

0.2

0.3

0.4

0.5

0 0.1 0.2 0.3 0.4 0.5 0.6

Vin [V]V

ou

t [V

]

Figure 6: Measured AM-AM Characteristic of SHF-0189 when fs = 10 MHz (includes 3rd order distortions).

Figure 7: Measured AM-AM Characteristic of SHF-0189 when fs = 5.3 MHz (67% of output spectrum is overlapped).

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Indirect Learning Predistortion Architecture

Squares Least of methodby calculated

)( of estimate an is)( and

PA,of functiontransfer nonlinear theis )f( where

)),(()()(

)),(()(:Algorithm Basic

1- ⋅⋅

⋅−=

=

fg

nygnzne

nzfny

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Predistortion Results

0

2

4

6

8

10

12

14

-100-50050100150200

Overlapped Spectrum of Output Signal [%]

AC

PR

Impr

ovem

ent

[dB

]

ACPR Improvement Using Subsampling Predistortion Architecture (Negative values in x-axis indicates sampling above Nyquist rate of the output signal)

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Predistortion Results (cont.)Sirenza SHF-0589: 2W GaAs HFET PA

Figure: ACPR@885kHz measurements over Pin variations.

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Predistortion Results (cont.)Motorola MRF-9180 170W Si LDMOS

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Impact of Memory Effects

“Memoryless” PA PA with Strong Memory Effects

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Impact of Memory Effects (cont.)

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Outline

• Introduction to Predistortion• LUT Updates using Sub-sampling

Receivers• RF Envelope Predistortion• Summary and Conclusions

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RF Envelope Predistortion

• Predistortion is performed directly on the modulated RF carrier using a high-speed vector modulator

• VMOD is driven by a look-up table (LUT) that is indexed by the instantaneous input power level

• Kusunoki, et al., demonstrated 6-7 dB ACPR improvement without adaptive feedback*

*S.Kusunoki, et al., “Power Amplifier Module with Digital Adaptive Predistortion for Cellular Phone, 2002 IEEE MTT-S Int. Microwave Symp. Dig., pp. 765-8, Seattle, WA, June 4-6, 2002.

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Adaptive RF Envelope Pre-Distortion Test BedAdaptive RF Envelope Pre-Distortion Test Bed

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FPGA LUT Implementation(Xilinx Vertex-II)

§ LVDS: Low Voltage Differential Signaling§ UART: Universal Asynchronous Receiver Transmitter§ DCM: Digital Clock Manager

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RF Envelope Pre-DistortionADS Simulations

847.6 847.8 848.0 848.2 848.4 848.6 848.8 849.0 849.2 849.4 849.6 849.8 850.0 850.2 850.4 850.6 850.8 851.0 851.2 851.4 851.6 851.8 852.0 852.2 852.4847.4 852.6

-85

-80

-75

-70

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

-90

-10

Mega_Hertz

(a) 2x Sampling

(b) w/o Pre-D

(c) 4x Sampling

(d) Source

dBm

-20

-10

0

10

20

30

6 7 8 9 10 11 12 13 14

nBits

AC

PR

Impr

ovem

ent,

dB

ADC for DSPADC for LUTDAC for VMOD

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RF Envelope Pre-D Test Bed

LUTτ

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Signal Integrity ADC-LUT-DAC Path

10MHz Sine Signal RS-232

10bit/100MHz

12bit/100MHz

ADC EV Board[AD9214](105MHz)

LUT Board

Agilent 1692A 68ch LA

DAC EV Board[AD9765](125MHz)

PC

I

Q

TDS 3054 DPO(500MHz, 5GS/s)

Agilent 33120AF/AWG (15MHz)

Testbed diagram

LUTin

LUTout

Linear function loaded into LUT

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Signal Integrity ADC-LUT-DAC Path (cont.)

(3-a) 10MHz input, No filtering

(3-b) 10MHz input, Filtering (fc=20MHz)

(3-c) Glitch due to the crosstalk of data lines and overflow

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Outline

• Introduction to Predistortion• LUT Updates using Sub-sampling

Receivers• RF Envelope Predistortion• Summary and Conclusions

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Summary and Conclusions

• Sub-sampling architecture developed to reduce sampling and processing requirements– Sample rate ≥ 2 x BW of input signal– Memory effects may increase this

• RF Envelope pre-D is an alternative to baseband digital pre-D– No digital I/Q stream required– Lower power, high BW