ADVALOG Day 8 (Memory and Storage 3)

7/31/2019 ADVALOG Day 8 (Memory and Storage 3)

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AUGUST 11, 2012

ADONIS S. SANTOS, ECE

InstructorFirst Asia Institute of Technology and Humanities


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Random Access Memories (RAMs)

Dynamic RAMs

Basic DRAM Organization

Types of DRAMs

FPM DRAMs

EDO DRAMs BEDO DRAMs

SDRAMs


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Dynamic memory cells store a data bit in a small capacitorrather than in a latch.

A MOS DRAM cell

A typical DRAM cellconsists of a single MOStransistor (MOSFET) anda capacitor.

The transistor acts as aswitch and the capacitorstores the data bit.


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Advantage the type of cell is very simple compare to SRAM cell

allows very large memory arrays to be constructed on achip at a lower cost per bit

Disadvantage Storage capacitor cannot hold its charge over an extended

period of time Additional memory circuitry and complicated the

operation

Much slower access time as compared to SRAM


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R/W is LOW

DIN line must beHIGH

HIGH on the ROWline

The transistor actsas a closed switchconnecting thecapacitor to the bit

line which allowsthe capacitor tocharge to apositive voltage.

Writing a 1 into the DRAM memory cell


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Writing a 0 into the DRAM memory cell

R/W is LOW

DIN line must be LOW

HIGH on the ROWline

The transistor acts asa closed switchconnecting thecapacitor to the bitline.

If the capacitor isstoring a 0, itremains uncharged,or if it is storing a 1, itdischarges.


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Reading a 1 into the DRAM memory cell

R/W is HIGH

HIGH on the ROWline

The transistor actsas a closed switchconnecting thecapacitor to the bitline and thus to theoutput buffer

(sense amplifier),so the data bitappears on thedata output line(DOUT).


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Refreshing a stored 1 in the DRAM memory cell

R/W is HIGH

REFRESH line isHIGH

HIGH on the ROWline

A path from thecharged capacitorto refresh bufferthrough the outputbuffer is createdallowing the storedbit to be appliedback to thecapacitor thusreplenishing thecapacitor.


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The major application of DRAMs is in the mainmemory of computers.

Features common to most DRAMs (1M x 1 bitDRAM)

Address Multiplexing

Read and Write Cycles Fast Page Mode

Refresh Cycles


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Simplified block diagram of a 1M x 1 DRAM


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DRAMs use a technique called address multiplexing toreduce the number of address lines.

The ten address lines are time multiplexed at the beginning

of a memory cycle by the row address select (RAS) and thecolumn address select ( CAS) into two separate 10-bitaddress fields.

Basic timing for address multiplexing

Row address is latchedwhen RAS is LOW.

Column address is latchedwhen CAS is LOW.


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At the beginning of each read memory cycle, RAS and CAS go active(LOW) to multiplex the row and column addresses into the latches anddecoders.

For a read cycle, the R/W input is HIGH.

Read cycle timing


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At the beginning of each write memory cycle, RAS and CAS go active(LOW) to multiplex the row and column addresses into the latches anddecoders.

For a write cycle, the R/W input is LOW.

Write cycle timing


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Apage is a section of memory available at a single rowaddress and consists of all the columns in a row.

Fast page mode allows fast successive read or write

operations at each column address in a selected row.

Fast page mode timing for a read operation


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A row address is first loaded by RAS going LOW andremaining LOW while CAS is toggled between HIGH andLOW.

A single row address is selected and remains selected whileRAS is active.

Each successive CAS selects another column in the selectedrow.

After a fast page mode cycle, all of the addresses in theselected row have been read from or written into, dependingon R/W.

When CAS goes to its nonasserted state (HIGH), it disablesthe data outputs. Therefore, the transition of CAS to HIGHmust occur only after valid data are latched by the external

system.


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Charge degrades (leaks off) with time and temperature. Typical refresh period of a DRAM is 8 ms to 16 ms Some devices have refresh period that can exceed 100 ms.

The two types of refresh operations:

RAS-only refresh consists of a RAS transition to the LOW (active) state, which latches the

address of the row to be refreshed while CAS remains HIGH (inactive)throughout the cycle.

CAS before RAS refresh initiated by CAS going LOW before RAS goes LOW. This sequence

activates an internal refresh counter that generates the row address to berefreshed. This address is switched by the data selector into the rowdecoder.


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Two basic refresh modes for refresh operation

Burst refresh

all rows in the memory array are refreshed

consecutively each refresh period with normal read andwrite operations suspended.

Distributed refresh

each row is refreshed at intervals interspersed betweennormal read or write cycles.

Example: The memory in 1M x 1 DRAM has 1024 rows andan 8 ms refresh period. Find the refresh period of each row.

Each row must be refreshed every 8 ms/1024 = 7.8 us whendistributed refresh is used.


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Major Types of DRAMS

Fast Page Mode (FPM) DRAM Extended Data Output (EDO) DRAM

Burst Extended Data Output (BEDO) DRAM

Synchronous (S) DRAM.


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Fast Page Mode DRAM

most common

has been the type used in computers until the

development of the EDO DRAM

Accessing memory addresses in the same row (on

the same page) thus saves time over pure random

accessing. CAS signal timing limits the rate at which the

columns within a page can be addressed.


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Extended Data Output DRAM

sometimes called hyper page mode DRAM

Similar to FPM DRAM except that CAS signaldeassertion state does not affect valid data

Current address is held until CAS is asserted again.

It speeds up the access time.


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Burst Extended Data Output DRAM

an EDO DRAM with address burst capability

The concept is the same as with synchronous burstSRAM that the address burst feature allows up to

four addresses to be internally generated from a

single external address.

It saves some access time.


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Synchronous DRAM

operation is synchronized with the system clock whichalso runs the microprocessor in a computer system.

The DRAM latches addresses, data, and controlinformation from the processor under control of the

system clock.

This allows the processor to handle other taskswhile the memory read or write operations are in

progress.


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References Thomas L. Floyd, Digital Fundamentals, 9th Edition, Prentice Hall

M. Morris Mano, Michael D. Ciletti, Digital Design, 4th Edition,Prentice Hall

Next Meeting

Lecture Topics Read-Only Memories (ROMs), Programmable ROMs

ADVALOG Day 8 (Memory and Storage 3)

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