adt_ec-chip-sol

7/28/2019 adt_ec-chip-sol

1/9

EC-N/PTDM Echo Cancelation Digital Signal Processor Solutions

NOVEMBER 2008

Device Overview 2009 ADAPTIVE DIGITAL TECHNOLOGIES, INC. all rights reserved

High Density Packet Echo

CANCELLATION CHIP SOLUTION

The Adaptive Digital Echo Cancellation Chips offer a complete solution designed to enable designers to increase the value

of their end product thus providing a superior voice experience to the customer. Adaptive Digitals EC-N/P chip solutions

provide all of the essential voice quality features needed to create sophisticated telephony equipment. The Echo

Cancellation and Packet Echo Cancellation chips combine Adaptive Digitals field-proven DSP software with Texas

Instruments Incorporated (TI) high performance fixed-point TMS320C64x+ DSPs.

Adaptive Digitals EC chips address critical performance issues such as echo, latency, and packet loss, greatly reducing the

impact of these impairments. The inclusion of Adaptive Digitals AT&T certified carrier grade G.168 Plus packet echo

canceller, which has the unique ability to handle round-trip delays of up to 512 milliseconds coupled with a built-in

awareness and handling of packet-loss, makes the VoIP suite unparalleled in quality.

1 HARDWARE FEATURES - TI TMS320C6424 DSP

High-Performance

- 400-/500-/600-/700-MHz, C64x+Clock Rate

- Eight 32-Bit C64x+ Instructions/Cycle

- 2.5-, 2-, 1.67-, 1.43-ns Instruction Cycle Time

16-Bit Host-Port Interface (HPI)

Enhanced Direct-Memory-Access (EDMA) Controller

(64 Independent Channels)

C64x+ L1/L2 Memory Architecture

Two Multichannel Buffered Serial Ports

10/100 Mb/s Ethernet MAC (EMAC)

Multichannel Audio Serial Port (McASP0)

IEEE-1149.1 (JTAG) Boundary-Scan-Compatible

On-Chip ROM Bootloader

Up to 111 General-Purpose I/O (GPIO) Pins

Port count: 64

3.3-V and 1.8-V I/O, 1.2-V Internal

3.3-V and 1.8-V I/O, 1.05-V Internal

This solution is based upon the TI TMS320C6424 DSP. The C6424 device is based on the third-generation high-

performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI),

making these DSPs an excellent choice for digital signal processor applications.

UART

OSC

PLLs/Clock Generator

Power/SleepController

Pin Multiplexing

Sys tem Con t ro l

JT AG I n t e r f a ce

C64x+ DSP CPU

128 KB L2 RAM

32 KBL 1 Pgm

Boot ROM

DS P

80 KBL 1 Data

McASP 12C UARTMcBSP

EDMA

GPIO

HPI

Watchdog

TimerPWM

General

Purpose

Timer

PCI

(33 MHz)VLYNQ

EMAC

with

MDIO

DDR2

Mem Ct lr

(32b)

As yn c EM IF/

NAND/

(16b)

McASP

PERIPHERALS

Sys tem

Prog ram/Da ta Sto rageC o n n e c t i v i t y

Se r ia l I n te r faces

Sw i t ch e d C e n t r a l R e so u r c e ( SC R )


2/9

EC-N/PTDM Echo Cancelation Digital Signal Processor Solution

NOVEMBER 2008

Device Overview 2009 ADAPTIVE DIGITAL TECHNOLOGIES, INC. all rights reserved2

1.1 HARDWARE FEATURES - TI TMS320C6452 DSP

High-Performance

- 720, 900--MHz, C64x+Clock Rate

- Eight 32-Bit C64x+ Instructions/Cycle- 1.39, 1.11-ns Instruction Cycle Time

1 32/16-Bit Host-Port Interface (HPI)

Enhanced Direct-Memory-Access (EDMA) Controller (64

Independent Channels)

C64x+ L1/L2 Memory Architecture

Two Telecom Serial Interface Ports (TSIP0/1)

Multichannel Audio Serial Port (McASP0)

Ten Serializers and SPDIF (DIT) Mode


On-Chip ROM Bootloader 32 General-Purpose I/O (GPIO) Pins (Multiplexed With

Other Device Functions)

Power

3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -900)

The TMS320TCI6452 DSP is a multicore device with large, on-chip shared memory, a DDR interface and Serial RapidIO for

inter-DSP communications. Gigabit Ethernet is embedded for native connectivity to IP-based systems. The TCI6486 is ideal

for high-density transcoding in mobile video distribution systems.

1.1 HARDWARE FEATURES - TI TMS320C6455 DSP

High-Performance

- 720/850/-MHz, 1/1.2 GHzC64x+Clock Rate

- Eight 32-Bit C64x+ Instructions/Cycle

- 1.39-, 1.17, 1-, and 0.83-ns Instruction Cycle Time

Enhanced Turbo Decoder Coprocessor (TCP2)

DDR2 Memory Controller

Enhanced Direct-Memory-Access 3 (EDMA3)

64 Independent Channels

64-Bit External Memory Interface (EMIFA)

Two Multichannel Buffered Serial Ports

10/100/1000 Mb/s Ethernet MAC (EMAC)

32-/16-Bit Host-Port Interface (HPI)

One Inter-Integrated Circuit (I2C) Bus

IEEE-1149.1 (JTAG)

Boundary-Scan-Compatible

UART

PLL1 and PLL1

Controller

Device Config Logic

Sys tem Cont ro l

C64x+ DSP CPU

2096KB L2 RAM

32 KB

L 1 Pgm

32KB L2 ROM

DSP

32 KB

L 1 D

12CMcBSP EDMA

3.0

GPIO

16

HPI

VCP2

General

Purpose

Timers (64b)

PCI

(66 MHz)

FPGA

CPLD

ASICs,

etc.

EMAC

with

MDIO

DDR2

Mem Ct lr

(32b)

EMIFA

(64b)

PER I PH ER AL S

Sys tem

Program/Data S torageC o n n e c t i v i t y

Ser ia l In ter faces

Sw i t ch e d C e n t r a l R e so u r ce ( SC R )

UTOPIA TCP2

TI TMS320C6455 DSP

Boot

Conf igurat ion

Timers

(4 64-bit or 8 32-bit)

or

3 Port Ethernet SwitchSubsystem

SGMII

x2

VLYNQ

EMIFA 16-bit

McASP

UART

SPI

12C

TSIP0

TSIP1

PCI66

UHPI

Switched Central Resource

EDMA 3.0

CC

TC TC TC TC

L1D 32KB

C64x+ Mega

L1P 32KB

L2 RAM

1408KB

L2 ROM

64KB

PLL

JTAG

GPIO x32


3/9


NOVEMBER 2008

Device Overview3

This solution is based upon TMS320C6455 DSP. The TMS320C6455 DSP has proven itself in demanding applications,

including video and telecom infrastructures. Using 90-nm process technology, the C6455 supports as many as 9,600 MIPS

at a 1.2-GHz clock rate. The C6455 also features Serial RapidIO for high-speed, low latency interprocessor

communications, critical in real-time systems such as video processing equipment.

1.2 HARDWARE FEATURES - TI TMS320TCIC6486 DSP

Six On-Chip TMS320C64x+ Megamodules

Endianess: Little Endian, Big Endian

High-Performance

- 500 MHz/625 MHz

- Eight 32-Bit Instructions/Cycle

Dedicated SPLOOP Instruction

Enhanced Direct-Memory-Access (EDMA) Controller

(64 Independent Channels)

32-Bit DDR2 Memory Controller

Two 1x Serial RapidIO Links

UTOPIA Level 2 Slave ATM Controller

L1/L2 Memory Architecture

- 256K-Bit (32K-Byte) L1P Program

- 256K-Bit (32K-Byte) L1D RAM/Cache

Three Telecom Serial Interface Ports (TSIPs)

- Each TSIP is 8 Links of 8 Mbps per direction

Two 10/100 Mb/s Ethernet MACs (EMACs)

16-Bit Host-Port Interface (HPI)


On-Chip ROM Bootloader

16 General-Purpose I/O (GPIO) Pins

This solution is based upon TMS320TCI6486 DSPThe TMS320TCI6486 device has six 500-MHz-optimized

TMS320C64x+ megamodules, which combinehigh performance with the lowest power dissipation per port. The C64x+

megamodules are thehighest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The

C64x+megamodule is based on the third-generation high-performance, advanced

2 SOFTWARE FEATURES - ADAPTIVE DIGITAL

EC Certified by AT&T Voice Quality Lab

ITU G.168-2002 Compliant

DTMF detect

Low Throughput Delay (500 microseconds)

Adapts to background noise continuously

Adaptive Non-linear processor

Comfort Noise Generator

No divergence due to double-talk

G.164/G.165 Tone Disabler

Programmable Aggressiveness

Adapts to background noise continuously

Scalable port count

Programmable maximum gain/loss

Programmable Output Target Level

3 CHANNEL DENSITY


4/9


NOVEMBER 2008


A p p l i c a t i o n S o l u t i o nP r o d u c tN u m b e r / S i l i c o n

C h a n n e lC o u n t

Description

NECEC-N-24/48/64

TMS320C6424V

24, 48, 64

C64x+ core

400-, 500-, 600-MHz C64x+ Clock Rate

1, 16-Bit Host-Port Interface (HPI)10/100 Mb/s EMAC2 McBSPs

NECEC-N-96

TMS320C6452V96

C64x+ core

720, 900-MHz C64x+ Clock Rate

32-/16-Bit Host-Port Interface

64 32-bit General-Purpose Registers

Five Configurable Video Ports

NECEC-N-224

TMS320C6455V224

C64x+ core

720-MHz, 850-MHz, 1-GHz, & 1.2-GHz Clock Rate


10/100/1000 Mb/s EMACs2 McBSPsTDME

choCancellation

NECEC-N-256/320

TMS320C6472256, 320

6 C64X+ Megamodules (cores) @ 500 MHz ea.

608 KB L2 RAM3 TSIP (Telecom Serial Ports)10/100/1000 Mb/s EMAC

A p p l i c a t i o n S o l u t i o nP r o d u c tN u m b e r / S i l i c o n

C h a n n e lC o u n t Description

PECEC-P-24/32

TMS320C6424V64

C64x+ core

400-, 500-, 600-MHz C64x+ Clock Rate

1, 16-Bit Host-Port Interface (HPI)

10/100 Mb/s EMAC2 McBSPs

PEC EC-P-48/64TMS320C6452V

96

C64x+ core

720, 900-MHz C64x+ Clock Rate32-/16-Bit Host-Port Interface

64 32-bit General-Purpose Registers

Five Configurable Video Ports

PECEC-P-224

TMS320C6455V

224C64x+ core

720-MHz, 850-MHz, 1-GHz, & 1.2-GHz Clock Rate


10/100/1000 Mb/s EMAC, 2 McBSPs

PacketEchoCancellation

PECEC-P-128

TMS320C6472320

6 C64X+ Megamodules (cores) @ 500 MHz ea. 32 KB

L1P RAM, 32 KB L1D RAM

608 KB L2 RAM3 TSIP (Telecom Serial Ports)

32 bit DDR2 @ 533 MHz

10/100/1000 Mb/s Ethernet MAC (EMAC)

4 FUNCTIONAL DESCRIPTION


5/9


NOVEMBER 2008

Device Overview5

The EC-N uses two TDM serial ports, one for the receive side of the canceller and the other for the send side of the

canceller. The TDM serial ports are fully programmable to allow connection to nearly any type of serial bus.

NOTE

The EC-N includes Adaptive Digitals proprietary voice quality enhancement algorithms including noise reduction and automaticlevel control. These features, in conjunction with the echo canceller, ensure maximum voice quality.

Serial Port

0

Serial Port

1

EC-N A0 EC-N B0

EC-N AN EC-N BN

"A" Side "B" Side

TDM A TDM B

HPI

Ports

B0

B1

.

.

.

BN

Ports

A0

A1

.

.

.

AN

Rece ive

Rece i ve

* Multi channel Buffered Serial Port

Fi gur e 1: Chi p Bl ock Di agr am

The chip is controlled by an external microprocessor via the chips host port interface. Control and status information

passes between the two processors over the HPI.

The PCM data enters and leaves the DSP via two of its serial ports. The VQE chip processes many circuits of full-duplex

voice data. A circuit is therefore connected to two bi-directional PCM ports, referred to as the A port and B port for that

circuit. Each of these two ports occupies a time slot on one of the DSPs multi-channel serial ports. Each of these serial

ports is connected to a TDM bus on the users board.

Lets follow circuit 0, for example, from the A side to the B side. Circuit As PCM data (A0) is placed on the host boards

TDM A highway on the first time slot configured for the VQE chips multi-channel buffered serial port 0. The The PCM

data is sent to the Send In side of VQE A0 block. The VQE A0 block performs the voice quality enhancement algorithms

for the A side. The output of the VQE A0 block on the Receive Out (Rout) side are fed to the VQE B0 blocks Receive In

(Rin) side. In this direction, the VQE B0 block passes the PCM data through without modifying it. The PCM data is sent to

serial port 1 and placed on time slot 0 on the TDM B highway.


6/9


NOVEMBER 2008


The data path from the B-side to the A- side is exactly opposite.

Control

Processor

Packet Network

EC-N

DSP

1

EC-N

DSP

2

EC-N

DSP

n. . .

HPI / Ethernet

TDM Serial Stream

E

T

H

E

R

N

E

THost Processor

Fi gur e 3: EC-N system block diagram

EC-N system consists of a host control processor connected to one or more DSPs loaded with VoIP software. The host

processor typically connects to a communication network and the DSPs typically connect to one or more TDM serial

streams. Figure (2) shows a block diagram for a typical EC-N system.

4.1 Channel Type

TDM to TDM Channel Type

TDM to TDM channel types provide a linkage between two analog phones. They are full duplex channels used to transfer

PCM data between TDM slots. These channels are typically used for PCM echo cancellation or time slot interchanging.

They are implemented as two functions (forward and reverse channels) within a single thread of processing as shown in

figure 4.

The TDM to TDM channel in a DSP can be dynamically setup as any type at run time. Frame sizes, audio codec types, and

tone detection types are selected when a channel is setup from capabilities configured at build time.

All channels are designed to operate as full duplex channels. A full duplex channel may be configured to operate as a half

duplex by setting the end points of one-half of the full duplex channel to NULL end-points.

The number of channels available in a DSP is dependent on the capabilities selected at build time


7/9


NOVEMBER 2008

Device Overview7

Fi gur e 4: TDM t o TDM Channel

TDM to TDM Processing. Each function inputs 8 kHz PCM samples from a serial port time slot and buffers as many

samples as needed to perform echo cancellation. When enough samples are buffered, the PCM input data is passed

through the echo canceller and again buffered for output. The buffered output samples are then delivered to a TDM slot.

Both echo canceller algorithms are independent options selectable at channel setup. The conference composite function

buffers the normalized sum of all conference members input data into a frame buffer. The samples are buffered until there

are enough samples to build an output frame. When enough samples are buffered, the samples are optionally passed

through the tone detector (TD) and the voice activity detector (VAD).

EC-N notifies the host at the start and end of each tone. If tone relay is enabled, tone packets are generated for each frame

until the tone ends; an end of tone packet is generated when the tone stops.

Voice activity detection is optionally performed when no tone is detected. A silence packet is generated when VAD does not

detect voice activity,

Voice encoding is optionally performed whenever tone or silence packets are NOT generated. The channels encoder type

identifies which vocoder will be used. The vocoder output is formatted and packed into the vocoders packet payload and

sent to the host for transmission.

PCM data is optionally transferred to a TDM slot.

The tone detection, tone relay, and voice activity detection algorithms are independent options selectable at channel setup.

Output packets and tone event packets are generated with the same frequency as the conferences frame size.

Input

Serial

Port/Slot

1

PCM

Frame

Buffer

PCM

Echo

Cancel

1

8 kHz

PCM In

Bulk

Delay

Bulk

Delay

PCM

Frame

Buffer

8 kHz

PCM Out

Output

Serial

Port/Slot

2

Input

Serial

Port/Slot

2

PCM

Frame

Buffer

PCM

Echo

Cancel

2

8 kHz

PCM In

PCM

Frame

Buffer

8 kHz

PCM Out

Output

Serial

Port/Slot

1


8/9


NOVEMBER 2008


5 EC-N APIs

The EC-NAPIs are the interface between a users application program and EC-N DSP cores. The APIs execute in a host

control processor connected to the DSP via the DSPs Host Port Interface (HPI). The APIs support multiple DSP cores anduse a DSP Identifier to select a particular core. The association between a DSP Identifier and a particular DSP core is made

by the user modified EC-N support functions.

The APIs are provided as ANSI C source code.

6 REFERENCES

1. Adaptive Digital Technologies G.PAK Users Guide

2. Texas Instruments TMS320C6424 Fixed-Point Digital Signal Processor (literature numberSPRS347C)

3. Texas Instruments TMS320C6455 Fixed-Point Digital Signal Processor (literature numberSPRS276H)

4. Texas Instruments TMS320C648x Digital Signal Processor (literature numberSPRU894D)

Adaptive Digital is a strategic member of the Texas Instruments Developer Network.

CONTACT INFORMATION

Web:Email:Tel:Toll Free:Fax:

Address:

www.adaptivedigital.cominformation@adaptivedigital.com610.825.01821.800.340.2066610.825.7616525 Plymouth Road, Suite 316, Plymouth WoodsPlymouth Meeting, PA 19462

IMPORTANT NOTICE: Data subject to change, for the most up to date information visit our website. Customers are advised to obtain the most current andcomplete information about Adaptive Digital products and services before placing orders.

All trademarks are property of their respective owners.


9/9


NOVEMBER 2008

Device Overview9

adt_ec-chip-sol

Documents

Transcript of adt_ec-chip-sol