Adsp Manual

8/21/2019 Adsp Manual

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TMS320C54xx processors retain in the basic Harvard architecture of theirpredecessor,

TMS320C25, but have several additional features, which iprove their perforance over it! "i#ure$ shows a functional bloc% dia#ra of TMS320C54xx processors! The& have one pro#ra and

three data eor& spaces with separate buses,which provide siultaneous accesses to pro#ra

instruction and two data operands and enables writin# of result at the sae tie! 'art ofthe eor& is ipleented on(chip and consists of cobinations of )*M, dual(access )+

M, and sin#le(access )+M! Transfers between the eor& spaces are also possible!

The central processin# unit C'-. of TMS320C54xx p rocessors consists of a 40(

bit arithetic lo#ic unit +/-., two 40(bit accuulators, a barrel shifter, a $x$ultiplier, a 40(bitadder, data address #eneration lo#ic 1+. with its ownarithetic unit, and pro#ra address

#eneration lo#ic '+.! These aor functionalunits are supported b& a nuber of re#isters andlo#ic in the architecture! + powerful instruction set with a hardware(supported, sin#le(instruction

repeat and bloc% repeat operations, bloc% eor& ove instructions, instructions that pac% two

or three siultaneous reads, and arithetic instructions with parallel store and load a%e thesedevices ver& efficient for runnin# hi#h(speed 1S' al#oriths!

Several peripherals, such as a cloc% #enerator, ahardware tier, a wait state #enerator,parallel 67* ports, and serial 67* ports, are also provided on(chip! These peripherals a%e it

convenient to interface the si#nal processors to the outside world!6n these followin# sections, weexaine in detail the various architectural features of the TMS320C54xx fail& of processors

block diagram of dsp processors-diagram

Bus Structure:The perforance of a processor #ets enhanced with the provision of ultiple buses to

provide siultaneous access to various parts of eor& or peripherals! The 54xx architecture is

built around four pairs of $8(bit buses with each pair consistin# of an address bus and a data bus! +s

shown in "i#ure $,these are The pro#ra bus pair '+9, '9. which carries the instruction codefro the pro#ra eor&!

Three data bus pairs C+9, C9: 1+9, 19: and+9, 9.: which interconnected the

various units within the C'-! 6n +ddition the pair C+9, C9 and 1+9, 19 are used to read fro

the data eor&, while The pair +9, 9 : carries the data to be written to the eor&! The ;54xxcan #enerate up to two data(eor& addresses per c&cle usin# the two auxiliar& re#ister arithetic

unit +)+-0 and +)+-$. in the 1+ bloc%! This enables accessin# two operandssiultaneousl&!

Central Processing Unit (CPU): The ;54xx C'- is coon to all the ;54xx devices!The


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hi#h(order word bits(3$($8., and low(order word bits $5(0., which can be stored and retrieved

individuall&!ach accuulator is eor&(apped and partitioned!6t can be confi#ured as thedestination re#isters! The #uard bits are used as a head ar#in for coputations!

Cpu diagram

9arrel shifter> provides the capabilit& to scale the data durin# an operand read or write!o overheadis re@uired to ipleent the shift needed for the scalin# operations!The


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can be #loball& enabled7disabled and can be individuall& as%ed throu#h the interrupt as%

re#ister 6M).! 'endin# interrupts are indicated in the interrupt fla# re#ister 6").! "ordetailed inforation on the structure of the interrupt vector table, the 6M) and the 6"), see

the device(specific data sheets!

Status !egisters (S"#$ S"%)

The status re#isters, ST0 and ST$, contain the status of the various conditions and odes for

the


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address if the bloc% of pro#ra eor& is to be repeated when operatin# in the repeat ode!

/nterrupt !egisters (/M!$ /0!)

The interrupt(as% re#ister 6M). is used to as% off specific interrupts individuall& at re@uiredties! The interrupt(fla# re#ister 6"). indicates the current status of the interrupts!

Processor-Mode Status !egister (PMS")

The processor(ode status re#ister 'MST. controls eor& confi#urations of the


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*&periment no

+ fast "ourier transfor ""T. is an efficient al#orith to copute the discrete "ourier transfor

1"T. and its inverse! There are an& distinct ""T al#oriths involvin# a wide ran#e ofatheatics, fro siple coplex nuber arithetic to #roup theor& and nuber theor&!

+ 1"T decoposes a se@uence of values into coponents of different fre@uencies! This operation isuseful in an& fields see discrete "ourier transfor for properties and applications of the

transfor. but coputin# it directl& fro the definition is often too slow to be practical! +n ""T isa wa& to copute the sae result ore @uic%l&> coputin# a 1"T of points in the naive wa&,

usin# the definition, ta%es *2. arithetical operations, while an ""T can copute the sae result

in onl& * lo# . operations! The difference in speed can be substantial, especiall& for lon# datasets where a& be in the thousands or illionsEin practice, the coputation tie can be reduced

b& several orders of a#nitude in such cases, and the iproveent is rou#hl& proportional to 7

lo#.! This hu#e iproveent ade an& 1"T based al#oriths practical: ""Ts are of #reatiportance to a wide variet& of applications, fro di#ital si#nal processin# and solvin# partial

differential e@uations to al#oriths for @uic% ultiplication of lar#e inte#ers!

The ost well %nown ""T al#oriths depend upon the factoriAation of , but there are ""Ts with* lo# . coplexit& for all , even for prie ! Man& ""T al#oriths onl& depend on the fact

that fft(al#orith is an th priitive root of unit&, and thus can be applied to analo#ous transfors

over an& finitue field, such as nuber theoretic transfors! Since the inverse 1"T is the sae as the1"T, but with the opposite si#n in the exponent and a $7 factor, an& ""T al#orith can easil& be

adapted for it!

'rocedure

ote> *nce &ou install the Code Coposer Studio v 3!3 software, the two icons will displa& in

des%top

Setup Code Coposer Studio v3!3

Code Coposer Studio

$! *pen Setup Code Coposer Studio v3!3!

2! 6n S&ste Confi#uration, select the board then G )eove all G &es!

6n fail&, select C2Fxx! 6n platfor, select xds$00 usb eulator!

6n ndianness, select little!

Select "2F$2 =1S$00 -S9 ulator G add G save @uit G no!

ote> The above two steps onl& for first tie to setup the processor in CCS!

3! *pen Code Coposer Studio v3!3!

4! 'roect G ew!


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'roect nae > t&pe the proect nae! /ocation > 9rowse, select the proect location !

'roect T&pe > xecutable!out.

Tar#et > TMS320C2F==! G "inish!

5! "ile G ew G Source file!

T&pe the pro#ra in untitled window!

8! "ile G Save!

9rowse our proect location then t&pe our proect nae!c !c extension is ust. G save!

! 'aste the followin# two cd files in our proect folder!

"2F$2IA1S'I)+MIln%!cd 1S'2F$xIHeadersInon96*S!cd

1S'2F$xIlobalBariable1efs!c

F! 'roect G +dd files to proect!

6n file of t&pe > +ll files

Ctrl J Select the followin# files ( proectnae!c

( 1S'2F$xIlobalBariable1efs!c ( "2F$2IA1S'I)+MIln%!cd

( 1S'2F$xIHeadersInon96*S!cd G open!

?! 'roect G 9uild *ption!

6n copiler tab, select 'reprocessor

6nclude search path(i. > C>KtidcsKc2FK1S'2F$xKv$20K1S'2F$xIheadersKinclude

6n lin%er tab, select libraries

Search path(i. > C>KCCStudioIv3!3KC2000Kc#toolsKlib

6ncl libraries(l. > rts2F00Il!lib!

6n lin%er tab, select 9asic

Stac% SiAe(stac%. > 0x400 G o%!


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$0! 'roect G 9uild or. )ebuild all!

$$! Connections for TMS320"2F$2 %it

Connect 5v adpter to TMS320"2F$2 %it! Connect usb cable to TMS320"2F$2 %it fro pc!

'ower on the TMS320"2F$2 %it!

$2! 1ebu# G connect!

$3! "ile G /oad 'ro#ra G 9rowse and select the proectnae!out file G open

$4! 1ebu# G o ain!

$5! Biew G eor&

nter +n +ddress > 0x3"?200 G nter!

T&pe the input!

"or exaple

0x3"?200 0x000$

0x3"?20$ 0x0002 0x3"?202 0x0003

0x3"?203 0x0004

0x3"?204 0x0004 0x3"?205 0x0003

0x3"?208 0x0002 0x3"?20 0x000$

$8! Biew G Latch window G watch$!

T&pe the followin# arra& variable!

=r real part output. =i ia#inar& part output.

$! 1ebu# G )un!

$F! 1ebu# G Halt

$?! See the output at followin# location, Biew G eor&

nter +n +ddress > 0x3"?2$0 G nter!real part output.

"or exaple


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0x3"?2$0 0x00$4 0x3"?$$$ 0x"""9 (5.

0x3"?$$2 0x0000

0x3"?$$3 0x0000 0x3"?2$0 0x0000

0x3"?2$0 0x0000 0x3"?2$0 0x0000

0x3"?2$0 0x"""9 (5.

20! Biew G eor&

nter +n +ddress > 0x3"?220 G nter!ia#inar& part output.

"or exaple

0x3"?220 0x0000 0x3"?$2$ 0x""" (2.

0x3"?$22 0x0000 0x3"?$23 0x0000

0x3"?220 0x0000 0x3"?220 0x0000

0x3"?220 0x0000

0x3"?220 0x0002

2$! *r see the ouput at watch window!

watch(window((a(hexadecial(values

ote> watch window will show exact decial values, processor eor& location will show ahexadecial values!

'ro#ra

include N1S'2F$xI1evice!hN

include Oath!hP

define '6 3!$4$5?

void 6nitS&ste.:


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float xQFR,tQFR,s$QFR,s2rQFR,s2iQFR,=rQFR,=iQFR,rQFR,iQFR:

const float L0r $,

L0i 0,

L$r 0!0,

L$i (0!0,

L2r 0,

L2i ($,

L3r (0!0,

L3i (0!0:

void ain.

U

int V6nput,V)ealIout,V6a#Iout:

int i0,0:

6nput int V.0x003"?200:

)ealIout int V.0x003"?2$0:

6a#Iout int V.0x003"?220:

6nitS&ste.:

fori0:iOF:iJJ.

U

tQiR 0:

tQiR V6nput J i.:


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W

77 9it reversal process

xQ0R tQ0R:

xQ$R tQ4R:

xQ2R tQ2R:

xQ3R tQ8R:

xQ4R tQ$R:

xQ5R tQ5R:

xQ8R tQ3R:

xQR tQR:

77 sta#e one process

s$Q0R int.xQ0R J xQ$R V L0r..:

s$Q$R int.xQ0R ( xQ$R V L0r..:

s$Q2R int.xQ2R J xQ3R V L0r..:

s$Q3R int.xQ2R ( xQ3R V L0r..:



s$Q8R int.xQ8R J xQR V L0r..:

s$QR int.xQ8R ( xQR V L0r..:

77 sta#e two process


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s2rQ0R s$Q0R J s$Q2R V L0r..:

s2iQ0R 0:

s2rQ$R s$Q$R:

s2iQ$R s$Q3R V L2i.:

s2rQ2R s$Q0R ( s$Q2R V L0r..:

s2iQ2R 0:

s2rQ3R s$Q$R:

s2iQ3R ( s$Q3R V L2i.:


s2iQ4R 0:

s2rQ5R s$Q5R:

s2iQ5R s$QR V L2i.:


s2iQ8R 0:

s2rQR s$Q5R:

s2iQR (s$QR V L2i.:

77 output

77 coplex ultiplication for 9 V Ln

rQ0R s2rQ4R V L0r. ( s2iQ4R V L0i.:

iQ0R s2rQ4R V L0i. J s2iQ4R V L0r.:

rQ$R s2rQ5R V L$r. ( s2iQ5R V L$i.:

iQ$R s2rQ5R V L$i. J s2iQ5R V L$r.:


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include N1S'2F$xI1evice!hN

include Oath!hP

define '6 3!$4$5?

void 6nitS&ste.:

float xQFR,tQFR,s$QFR,s2rQFR,s2iQFR,=rQFR,=iQFR,rQFR,iQFR:

const float L0r $,

L0i 0,

L$r 0!0,

L$i (0!0,

L2r 0,

L2i ($,

L3r (0!0,

L3i (0!0:

void ain.

U

int V6nput,V)ealIout,V6a#Iout:

int i0,0:

6nput int V.0x003"?200:

)ealIout int V.0x003"?2$0:

6a#Iout int V.0x003"?220:


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6nitS&ste.:

fori0:iOF:iJJ.

U

tQiR 0:

tQiR V6nput J i.:

W

77 9it reversal process

xQ0R tQ0R:

xQ$R tQ4R:

xQ2R tQ2R:

xQ3R tQ8R:

xQ4R tQ$R:

xQ5R tQ5R:

xQ8R tQ3R:

xQR tQR:

77 sta#e one process

s$Q0R int.xQ0R J xQ$R V L0r..:

s$Q$R int.xQ0R ( xQ$R V L0r..:





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s$Q8R int.xQ8R J xQR V L0r..:

s$QR int.xQ8R ( xQR V L0r..:

77 sta#e two process


s2iQ0R 0:

s2rQ$R s$Q$R:

s2iQ$R s$Q3R V L2i.:


s2iQ2R 0:

s2rQ3R s$Q$R:

s2iQ3R ( s$Q3R V L2i.:


s2iQ4R 0:

s2rQ5R s$Q5R:

s2iQ5R s$QR V L2i.:


s2iQ8R 0:

s2rQR s$Q5R:

s2iQR (s$QR V L2i.:

77 output

77 coplex ultiplication for 9 V Ln


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rQ$R s2rQ5R V L$r. ( s2iQ5R V L$i.:

iQ$R s2rQ5R V L$i. J s2iQ5R V L$r.:



rQ3R s2rQR V L3r. ( s2iQR V L3i.:

iQ3R s2rQR V L3i. J s2iQR V L3r.:



rQ5R s2rQ5R V L$r. ( s2iQ5R V L$i.:

iQ5R s2rQ5R V L$i. J s2iQ5R V L$r.:



rQR s2rQR V L3r. ( s2iQR V L3i.:

iQR s2rQR V L3i. J s2iQR V L3r.:

77 coplex addition for + J 9Ln


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0:

fori0:iO4:iJJ.

U

=rQiR s2rQR J rQiR:

=iQiR s2iQR J iQiR:

JJ:

W

77 coplex subtraction for + ( 9Ln

0:

fori4:iOF:iJJ.

U

=rQiR s2rQR ( rQiR:

=iQiR s2iQR ( iQiR:

JJ:

W

77 sendin# output arra& to eor& location

fori0:iOF:iJJ.

U

V)ealIout JJ =rQiR:

V6a#Iout JJ =iQiR:

W


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for::.:

W

void 6nitS&ste.

U

+//*L:

S&sCtrl)e#s!L1C) 0x008F: 77 Setup the watchdo#

77 0x008F to disable the Latchdo# , 'rescaler $

77 0x00+" to *T disable the Latchdo#, 'rescaler 84

S&sCtrl)e#s!SCS) 0: 77 Latchdo# #enerates a )ST

S&sCtrl)e#s!'//C)!bit!16B $0: 77 Setup the Cloc% '// to ultipl& b& 5

S&sCtrl)e#s!H6S'C'!all 0x$: 77 Setup Hi#hspeed Cloc% 'rescaler to divide b& 2

S&sCtrl)e#s!/*S'C'!all 0x2: 77 Setup /owspeed C/oc% 'rescaler to divide b& 4

77 'eripheral cloc% enables set for the selected peripherals!

S&sCtrl)e#s!'C/DC)!bit!B+C/D0:

S&sCtrl)e#s!'C/DC)!bit!B9C/D0:

S&sCtrl)e#s!'C/DC)!bit!SC6+C/D0:

S&sCtrl)e#s!'C/DC)!bit!SC69C/D0:

S&sCtrl)e#s!'C/DC)!bit!MC9S'C/D0:

S&sCtrl)e#s!'C/DC)!bit!S'6C/D0:

S&sCtrl)e#s!'C/DC)!bit!C+C/D0:


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S&sCtrl)e#s!'C/DC)!bit!+1CC/D0:

16S:

W



rQ3R s2rQR V L3r. ( s2iQR V L3i.:

iQ3R s2rQR V L3i. J s2iQR V L3r.:



rQ5R s2rQ5R V L$r. ( s2iQ5R V L$i.:

iQ5R s2rQ5R V L$i. J s2iQ5R V L$r.:



rQR s2rQR V L3r. ( s2iQR V L3i.:

iQR s2rQR V L3i. J s2iQR V L3r.:

77 coplex addition for + J 9Ln

0:

fori0:iO4:iJJ.

U


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=rQiR s2rQR J rQiR:

=iQiR s2iQR J iQiR:

JJ:

W

77 coplex subtraction for + ( 9Ln

0:

fori4:iOF:iJJ.

U

=rQiR s2rQR ( rQiR:

=iQiR s2iQR ( iQiR:

JJ:

W

77 sendin# output arra& to eor& location

fori0:iOF:iJJ.

U

V)ealIout JJ =rQiR:

V6a#Iout JJ =iQiR:

W

for::.:

W


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void 6nitS&ste.

U

+//*L:

S&sCtrl)e#s!L1C) 0x008F: 77 Setup the watchdo#

77 0x008F to disable the Latchdo# , 'rescaler $

77 0x00+" to *T disable the Latchdo#, 'rescaler

84

S&sCtrl)e#s!SCS) 0: 77 Latchdo# #enerates a )ST

S&sCtrl)e#s!'//C)!bit!16B $0: 77 Setup the Cloc% '// to ultipl& b& 5

S&sCtrl)e#s!H6S'C'!all 0x$: 77 Setup Hi#hspeed Cloc% 'rescaler to divide b& 2

S&sCtrl)e#s!/*S'C'!all 0x2: 77 Setup /owspeed C/oc% 'rescaler to divide b& 4

77 'eripheral cloc% enables set for the selected peripherals!

S&sCtrl)e#s!'C/DC)!bit!B+C/D0:

S&sCtrl)e#s!'C/DC)!bit!B9C/D0:

S&sCtrl)e#s!'C/DC)!bit!SC6+C/D0:

S&sCtrl)e#s!'C/DC)!bit!SC69C/D0:

S&sCtrl)e#s!'C/DC)!bit!MC9S'C/D0:

S&sCtrl)e#s!'C/DC)!bit!S'6C/D0:

S&sCtrl)e#s!'C/DC)!bit!C+C/D0:

S&sCtrl)e#s!'C/DC)!bit!+1CC/D0:

16S:

W


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experient n0!?

M 4: X 1eciation factor

"p F0: X 'assband(ed#e fre@uenc&"st $00: X Stopband(ed#e fre@uenc&

+p 0!$: X 'assband pea%(to(pea% ripple+st F0: X Miniu stopband attenuation

"s F00: X Saplin# fre@uenc&

Hfd1eci fdesi#n!deciatorM,YlowpassY,"p,"st,+p,+st,"s.

Hfd1eci

MultirateT&pe> Y1eciatorY

)esponse> Y/owpassY1eciation"actor> 4

Specification> Y"p,"st,+p,+stY

1escription> U4x$ cellWoraliAed"re@uenc&> false

"s> F00"sIin> F00

"sIout> 200"pass> F0

"stop> $00

+pass> 0!$+stop> F0

H1eci desi#nHfd1eci,Ye@uirippleY, YS&ste*bectY, true.:

easureH1eci.

HSpec dsp!Spectru+nal&Aer!!! X Spectru scope

Y'lot+sTwoSidedSpectruY, false, !!! YSpectral+vera#esY, 50, Y*verlap'ercentY, 50, !!!

YTitleY, Y1eciator with e@uiripple lowpass filterY,!!!

Y/iitsY, Q(50, 0R, YSaple)ateY, "s7MV2.:

while Zis1oneHSource. inputSi# stepHSource.: X 6nput

deciatedSi# stepH1eci, inputSi#.: X 1eciator stepHSpec, upsapledeciatedSi#,2..: X Spectru X The upsaplin# is done to increase =(liits of Spectru+nal&Aer

X be&ond $7M.V"s72 for better visualiAationend

releaseHSpec.:

resetHSource.:

ans

Saple )ate > F00 HA

'assband d#e > F0 HA3(d9 'oint > F5!82$ HA

8(d9 'oint > F!F4?2 HA


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Stopband d#e > $00 HA

'assband )ipple > 0!0?24$4 d9Stopband +tten! > F0!3$35 d9

Transition Lidth > 20 HA


23/28

=')6MT * F

clear all: close all:

Xexaple bandliited rando input paraeters

x filterfir$0,!$.,$,randn$,$024..:

up 3: X6nterpolation factor

cutoff !3:

intorder 8:h$ intfiltup, intorder, cutoff.: Xideal filter

h$ upVh$7suh$.:

h2 fir$2VupVintorder(2,cutoff.: Xordinar& /'"

h2 upVh27suh2.:

Xupsaple

xIup Aeros$,len#thx.Vup.:xIup$>up>end. x:

xIf$ filterh$,$,xIup.:

xIf2 filterh2,$,xIup.:

fi#ure:

subplot3,$,$.:holdplotxIf$,Yo((Y.:

plotxIf2,Yr!(Y.:

le#endYideal outputY,Yfir$ outputY.:

subplot3,$,2.:plotxIf$(xIf2.:

le#endYerrorY.:

subplot3,$,3.:hold

ploth$,Y!(Y.:ploth2,Yr!(Y.:

le#endYideal filterY,Yfir$ filterY.:

3 3 m-file to illustrate simple interpolation and3 decimation operations (Program 4B5%$ p67%)3 0ile name: prog4b%5m3 An /llustration of interpolation b' a factor of 7 30s8%###9 3 sampling freuenc'A8%5;9 3 relatipi>f%>t)?B>cos(=>pi>f=>t)9 3 generate signal


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'8interp(&$7)9 3 interpolate signal b' 7stem(&(%:=;)) 3 plot original signal&label(@2iscrete time$ n" @)'label(@/nput signal let)?B>cos(=>pi>f=>t)9 3 generate signal'8resample(&$7$%)9 3 interpolate signal b' 7stem(&(%:=;)) 3 plot original signal&label(@2iscrete time$ n" @)'label(@/nput signal le


25/28

%5 P!+!AM " *!/0D 2*C/MA"/,

A/M: To verif& 1eciation and 6nterpolation of a #iven Se@uences

S0"EA!* !*FU/!*2: M+T /+9 !0

P!+!AM 2*SC!/P"/,: The saplin# rate alteration that is eplo&ed to #enerate a newse@uence with a saplin# rate lower than that of a #iven se@uence! Thus, if xQnR is a se@uence with

a saplin# rate of "T HA and it is used to #enerate another se@uence &QnR with a desired saplin#

rate of "TY HA, then the saplin# rate alteration ratio is #iven b& "T

Y 7 "T )!

6f ) O $, the saplin# rate is decreased b& a process called decimation and it results in a se@uencewith a lower saplin# rate!

The deciation can be carried out b& usin# the pre(defined coands deciate!

MA"GAB C2*:X 1C6M+T6*

clc:

clear all:close all:

dispY/et us ta%e a sinusoidal se@uence which has to be deciated> Y.:

finputYnter the si#nal fre@uenc& f> Y.:fsinputYnetr the saplin# fre@unec& fs> Y.:

TinputYnter the duration of the si#nal in seconds T> Y.:

dt$7fs:tdt>dt>T

Mlen#tht.:cos2VpiVfVt.:

rinputYnter the factor b& which the saplin# fre@uenc& has to be reduced r> Y.:ddeciate,r.:

fi#ure$.:

subplot3,$,$.:plott,.:

#rid:xlabelYt((PY.:

&labelY+plitude((PY.:titleYSinusoidal si#nal before saplin#Y.:subplot3,$,2.:

ste.:

#rid:xlabelYn((PY.:

&labelY+plitudes of ((PY.:titleYSinusoidal si#nal after saplin# before deciationY.:

subplot3,$,3.:

sted.:#rid:

titleYSinusoidal after deciationY.:xlabelYn7r((PY.:

&labelY+plitude of d((PY.:


26/28

U"PU":/et us ta%e a sinusoidal se@uence which has to be deciated>

nter the si#nal fre@uenc& f> 2netr the saplin# fre@unec& fs> $00

nter the duration of the si#nal in seconds T> $nter the factor b& which the saplin# fre@uenc& has to be reduced r> 2

+!APHS:

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-1

0

1

t-->

A m p l i t u d e - - >

Sinusoidal signal before sampling

0 10 20 30 40 50 60 70 80 90 100-1

0

1

n--> A m p l i t u d e s o f m - - >

Sinusoidal signal after sampling before decimation

0 5 10 15 20 25 30 35 40 45 50-1

0

1Sinusoidal after decimation

n/r--> A m p l i t u d e o f m d - - >

/,0*!*,C* : The onl& constraint about the pro#ra is that the factors of deciation orinterpolation should be an inte#ers! 6f we want to chan#e the saplin# fre@uenc& b& a factor whichis not an inte#er it can be done b& usin# the coand resaple b& which we can chan#e the

saplin# rate b& a factor 6 7 1! "or this we have to interpolate b& an inte#er factor 6 and then

deciate b& an inte#er factor 1

!*SUG" : The 1eciation of #iven se@uences is verified and #raphs are plotted!


27/28

A/M: To verif& 6nterpolation of a #iven Se@uence!

S0"EA!* !*FU/!*2: M+T /+9 !0

P!+!AM 2*SC!/P"/,: The saplin# rate alteration that is eplo&ed to #enerate a newse@uence with a saplin# rate hi#her than that of a #iven se@uence! Thus, if xQnR is a se@uence with

a saplin# rate of "T HA and it is used to #enerate another se@uence &QnR with a desired saplin#

rate of "TY HA, then the saplin# rate alteration ratio is #iven b& "T

Y 7 "T )!

6f ) P $, the process is called interpolation and results in a se@uence with a hi#her saplin# rate!

The interpolation can be carried out b& usin# the pre(defined coand interp respectivel&!

MA"GAB C2*:

X6T)'*/+T6*

clc:clear all:

close all:

dispY/et us ta%e a sinusoidal se@uence which has to be interpolated> Y.:finputYnter the si#nal fre@uenc& f> Y.:

fsinputYnetr the saplin# fre@unec& fs> Y.:TinputYnter the duration of the si#nal in seconds T> Y.:

dt$7fs:

tdt>dt>TMlen#tht.:

cos2VpiVfVt.:rinputYnter the factor b& which the saplin# fre@uenc& has to be increased r> Y.:

dinterp,r.:

fi#ure$.:subplot3,$,$.:

plott,.:#rid:

xlabelYt((PY.:

&labelY+plitude((PY.:

titleYSinusoidal si#nal before saplin#Y.:subplot3,$,2.:ste.:

#rid:

xlabelYn((PY.:&labelY+plitudes of ((PY.:

titleYSinusoidal si#nal after saplin# before interpolationY.:

subplot3,$,3.:sted.:

#rid:titleYSinusoidal after interpolationY.:

xlabelYn x r((PY.:&labelY+plitude of d((PY.:


28/28

U"PU":/et us ta%e a sinusoidal se@uence which has to be interpolated>nter the si#nal fre@uenc& f> 2

netr the saplin# fre@unec& fs> $00

nter the duration of the si#nal in seconds T> $nter the factor b& which the saplin# fre@uenc& has to be increased r> 2

+!APHS:

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-1

0

1

t-->

A m p l i t u d e - - >

Sinusoidal signal before sampling

0 10 20 30 40 50 60 70 80 90 100-1

0

1

n--> A m p l i t u d e s o f m - - >

Sinusoidal signal after sampling before interpolation

0 20 40 60 80 100 120 140 160 180 200-2

0

2Sinusoidal after interpolation

n x r--> A m p l i t u d e o f m d - - >

/,0*!*,C* : The onl& constraint about the pro#ra is that the factors of deciation or

interpolation should be an inte#ers! 6f we want to chan#e the saplin# fre@uenc& b& a factor whichis not an inte#er it can be done b& usin# the coand resaple b& which we can chan#e the

saplin# rate b& a factor 6 7 1! "or this we have to interpolate b& an inte#er factor 6 and thendeciate b& an inte#er factor 1

!*SUG" : The 6nterpolation of #iven se@uences is verified and #raphs are plotted!

Adsp Manual

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