ADS1x48EVM Evaluation Module

User’s GuideADS1x48EVM Evaluation Module

ABSTRACT

The ADS1x48 evaluation module (EVM) allows users to evaluate the functionality of the Texas Instruments' 16-bit ADS1148 or the 24-bit ADS1248. ADS1x48 refers to what is common to both devices and EVMs. Any differences in operation between the devices or EVMs are listed separately. The ADS1x48 devices are highly integrated delta-sigma ADCs that include a programmable gain amplifier, a 2.048-V voltage reference, an internal oscillator, dual current sources (IDACs), and several system-monitoring features. Each ADS1x48 device has inputs that can be configured as seven single-ended or four differential inputs. All of these features integrated into the ADS1x48 devices enable precision measurement for many types of analog temperature sensors including thermocouples, resistance temperature detectors (RTDs), and thermistors. This user’s guide describes both the EVM hardware platform and the graphical user interface (GUI) software used to configure and operate the device. This user’s guide also includes the EVM schematic diagram, board layout, and bill of materials. The EVM platform eases the evaluation of the ADS1x48 device with hardware, software, and computer connectivity through the universal serial bus (USB) interface.

Throughout this document, the abbreviation EVM and the term evaluation module are synonymous with the ADS1x48EVM.

ADS1x48 Evaluation Module (ADS1248EVM Shown)

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ADS1x48EVM Evaluation Module 1

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Table of Contents1 Introduction.............................................................................................................................................................................52 Getting Started With the ADS1x48EVM................................................................................................................................ 63 ADS1x48EVM Overview......................................................................................................................................................... 7

3.1 Analog and Digital Power Supplies.................................................................................................................................... 73.2 Voltage Reference Options................................................................................................................................................ 93.3 Clock Options...................................................................................................................................................................103.4 Digital Interface.................................................................................................................................................................113.5 Analog Input Connections................................................................................................................................................ 12

4 ADS1x48EVM GUI................................................................................................................................................................. 284.1 Home................................................................................................................................................................................284.2 Data Capture....................................................................................................................................................................314.3 Register Map....................................................................................................................................................................33

5 Bill of Materials, Printed Circuit Board Layout, and Schematic.......................................................................................365.1 Bill of Materials.................................................................................................................................................................365.2 Printed Circuit Board Layout............................................................................................................................................ 385.3 Schematic........................................................................................................................................................................ 41

6 Revision History................................................................................................................................................................... 42

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List of FiguresFigure 1-1. ADS1x48EVM Functional Block Diagram................................................................................................................. 5Figure 2-1. Connecting the ADS1x48EVM to the PAMB Board...................................................................................................6Figure 3-1. LED Indicators D1 and D5.........................................................................................................................................7Figure 3-2. Jumper (JP1) Selects AVDD on the ADS1x48EVM.................................................................................................. 8Figure 3-3. ADS1x48EVM VREF Options (Yellow) and Test Points (Red).................................................................................. 9Figure 3-4. ADC Clock Options on the ADS1x48EVM.............................................................................................................. 10Figure 3-5. ADS1x48EVM-to-PAMBoard Connections.............................................................................................................. 11Figure 3-6. ADS1x48EVM Analog Input Terminal Blocks (J5, Left; J6, Right)...........................................................................12Figure 3-7. Thermocouple Input Structure on the ADS1x48EVM..............................................................................................13Figure 3-8. Using REF5025 (input J5:3) to Bias a Thermocouple............................................................................................. 13Figure 3-9. Thermistor Input Structure on the ADS1x48EVM....................................................................................................15Figure 3-10. Connecting a Thermistor to the J5 Terminal Block on the ADS1x48EVM.............................................................15Figure 3-11. PCB Layout for J5 Terminal Block Showing Copper Pours for CJC Measurement...............................................16Figure 3-12. RTD Input Structure on the ADS1x48EVM............................................................................................................17Figure 3-13. Connection Diagram for a 2-Wire RTD Using a Low-Side RREF .......................................................................... 19Figure 3-14. Connection Diagram for a 2-Wire RTD Using a High-Side RREF ..........................................................................20Figure 3-15. Connection Diagram for a 3-Wire RTD Using One IDAC and a Low-Side RREF ..................................................21Figure 3-16. Connection Diagram for a 3-Wire RTD Using One IDAC and a High-Side RREF ................................................. 22Figure 3-17. Connection Diagram for a 3-Wire RTD Using Two IDACs and a Low-Side RREF ................................................ 23Figure 3-18. Connection Diagram for a 3-Wire RTD Using Two IDACs and a High-Side RREF ................................................24Figure 3-19. Connection Diagram for a 4-Wire RTD Using a Low-Side RREF .......................................................................... 25Figure 3-20. Connection Diagram for a 4-Wire RTD Using a High-Side RREF ..........................................................................26Figure 3-21. Using the TC± Inputs on J5 as General-Purpose Signal Inputs............................................................................27Figure 4-1. Browser Extension and TI Cloud Agent Installation................................................................................................ 28Figure 4-2. ADS1x48EVM GUI Home Page.............................................................................................................................. 29Figure 4-3. Connected Hardware Information........................................................................................................................... 29Figure 4-4. File Menu.................................................................................................................................................................30Figure 4-5. Data Capture Window............................................................................................................................................. 31Figure 4-6. Capture Settings Slide-Out......................................................................................................................................31Figure 4-7. Capture Statistics.................................................................................................................................................... 32Figure 4-8. Time Domain Plot....................................................................................................................................................32Figure 4-9. Histogram Plot.........................................................................................................................................................33Figure 4-10. Register Map......................................................................................................................................................... 34Figure 4-11. Register Read and Write Controls.........................................................................................................................34Figure 4-12. Auto Read Options................................................................................................................................................ 35Figure 4-13. Register Write Options.......................................................................................................................................... 35Figure 5-1. Composite PCB Layout........................................................................................................................................... 38Figure 5-2. Top Silkscreen......................................................................................................................................................... 39Figure 5-3. Top Layer.................................................................................................................................................................39Figure 5-4. Internal Ground Layer 1.......................................................................................................................................... 39Figure 5-5. Internal Ground Layer 2.......................................................................................................................................... 39Figure 5-6. Bottom Layer........................................................................................................................................................... 40Figure 5-7. Bottom Silkscreen................................................................................................................................................... 40Figure 5-8. ADS1x48EVM Schematic........................................................................................................................................41

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List of TablesTable 1-1. Related Documentation.............................................................................................................................................. 5Table 3-1. Summary of ADS1x48EVM VREF Options.................................................................................................................9Table 3-2. ADS1x48EVM Header Pinout and Description......................................................................................................... 11Table 3-3. ADS1x48EVM Terminal Block Input Description (J5 and J6)....................................................................................12Table 3-4. ADS1x48EVM Terminal Block (J6) to ADC Connections..........................................................................................17Table 3-5. ADS1x48EVM Settings for Different RTD Types...................................................................................................... 26Table 5-1. Bill of Materials..........................................................................................................................................................36

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1 IntroductionThe ADS1x48EVM is a fully assembled evaluation platform designed to highlight the ADS1x48 features and modes of operation that make this device suitable for measuring analog temperature sensors. The EVM sits on top of an accompanying precision ADC motherboard (PAMBoard) used as a USB-to-PC GUI communication bridge. This board combination also serves as an example implementation of connecting a microcontroller (MCU) to communicate with the ADS1x48 device through a serial-peripheral interface (SPI). Figure 1-1 shows a functional block diagram for the ADS1x48EVM.

Note

The ADS1x48EVM requires an external controller to evaluate the ADS1x48 device.

The PAMBoard is controlled by commands received from the ADS1x48EVM GUI, and returns data to the GUI for display and analysis. If the PAMBoard is not used, the EVM plug-in module format allows for an alternative external host to communicate with the ADS1x48 through the pin headers J1 through J4. Header connections are identified in Section 5.2 and listed in Table 3-2.

The combined ADS1x48EVM and PAMBoard incorporate the following features:

• ADS1x48, a 16- or 24-bit delta-sigma ADC with eight input channels• Input terminal block and jumper configurations that enable easy measurement of many types of analog

temperature sensors• Analog voltage (AVDD) selection of 3.3-V or 5-V operation for the ADS1x48• Multiple voltage reference options: 2.048-V reference integrated into the ADS1x48, discrete REF5025,

ratiometric reference for RTD measurements, or external reference supplied via the input terminal blocks• Internal or external clock selection• SPI for communication and configuration

Analog Header and

Terminal Block

Analog Inputs

and RC FilterADC

Analog Power

Source

PAMBboard

Digital Interface

PAMBoard

Power

EEPROM

Device ID

SPI /

GPIO I2C

AVDD

3.3 V

5 V

DVDD

REF50252.5 VREF

Figure 1-1. ADS1x48EVM Functional Block Diagram

Table 1-1 lists documents related to the ADS1x48EVM.

Table 1-1. Related DocumentationDevice Literature Number

ADS1248 SBAS426

ADS1148 SBAS453

REF5025 SBOS410

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https://www.ti.com/lit/ds/symlink/ads1247.pdf

https://www.ti.com/lit/ds/symlink/ads1148.pdf

https://www.ti.com/lit/ds/symlink/ref5025.pdf

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2 Getting Started With the ADS1x48EVMThe following list of steps provides an overview to quickly get the ADS1x48EVM setup and operational. The subsequent sections in this document expand on each step in order to explain in detail the available features on the ADS1x48EVM and the corresponding GUI. Links are provided to navigate from this quick-start guide to the appropriate section at each step, where applicable.

1. Remove the ADS1x48EVM, PAMBoard, and USB cable from the ADS1x48EVM box.2. If necessary, connect the ADS1x48EVM to the PAMBoard as shown in the left image in Figure 2-1.3. Set the ADS1x48EVM jumpers to the desired location:

a. Powerb. Clockc. RTD connections (if applicable)

4. Connect the micro-USB-to-USB cable from the PAMBoard directly to a USB port on the computer. Do not connect the cable through a USB hub.

5. Open up the web-based GUI available on the EVM landing page (ADS1148EVM-PDK or ADS1248EVM-PDK).a. First-time users may be prompted to download and install the browser extension for Firefox™ or

Chrome™ and the TI Cloud Agent Application. Installing the TI Cloud Agent is a one-time download and installation.

6. Refresh the GUI such that a green signal displays and the Hardware Connected indicator shows in the bottom status ribbon (see Figure 4-2).

7. Select the desired ADC reference voltage.8. Connect your sensors or signals to the input terminal blocks (J5 and J6).9. Capture and analyze data using the GUI.

Figure 2-1. Connecting the ADS1x48EVM to the PAMB Board

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3 ADS1x48EVM OverviewVarious onboard components are used to provide power to, communicate with, and interface the analog input to the ADS1x48 device.

3.1 Analog and Digital Power SuppliesThe ADS1x48 supports a wide unipolar analog supply voltage (AVDD) range from 2.7 V to 5.5 V and a bipolar AVDD of ±2.5 V. The ADS1x48EVM AVDD can be set to either 3.3 V or 5 V. Power is supplied from the USB 5-V source to the PAMBoard. However, the USB power-supply voltage is not consistent from PC to PC. A DC/DC converter on the PAMBoard increases the USB output to 5.5 V. A linear low-dropout (LDO) regulator uses this 5.5-V output to provide clean and stable 5-V and 3.3-V supplies from the PAMBoard to the ADS1x48EVM.

Two LEDs light up on the PAMBoard, as shown in Figure 3-1, when the USB cable is plugged into the computer. The top LED (D1) indicates that the ADS1x48EVM is ready to communicate with the GUI. The bottom LED (D5) indicates that the 5-V output is active.

Figure 3-1. LED Indicators D1 and D5

Jumper JP1 selects the ADS1x48 AVDD voltage. When jumper JP1 is in the left position (see Figure 3-2), AVDD on the ADS1x48 is set to 5 V. When the jumper JP1 is set to the right position, AVDD is set to 3.3 V.

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Figure 3-2 also shows two diodes on the ADS1x48EVM that help indicate when power is valid. The top diode (D1) denotes that the 3.3-V output is active. The bottom diode (D2) indicates that AVDD is active after the shunt selection on jumper JP1 is made.

The ADS1x48 devices accept a digital supply voltage (DVDD) range from 2.7 V to 5.25 V. On the ADS1x48EVM, the ADS1x48 DVDD is a fixed value of 3.3 V. As with AVDD, this 3.3-V DVDD is sourced from the USB power-supply voltage and is used as the PAMBoard DVDD.

Figure 3-2. Jumper (JP1) Selects AVDD on the ADS1x48EVM

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3.2 Voltage Reference OptionsThe ADS1x48 is a highly flexible ADC that can accept multiple voltage reference (VREF) options. First, the ADS1x48 integrates a low-noise, 2.048-V reference to help reduce overall component count. Moreover, this internal VREF voltage is supplied externally via the ADS1x48 REFOUT pin and is available on terminal block J5. The ADS1x48 also has two sets of differential VREF inputs defined as REFP0, REFN0 and REFP1, REFN1. All of these options are selected via the MUX1 register in the ADS1x48.

The ADS1x48EVM supports four different VREF options to offer maximum flexibility. Table 3-1 details these four options. Figure 3-3 shows the location of each VREF option (highlighted in yellow) as well as each VREF test point (highlighted in red).

Table 3-1. Summary of ADS1x48EVM VREF OptionsVREF Mode VREF Input

Channel Voltage Location Test Point Comment

Internal — 2.048 V U3 Output on J5 (REFOUT) —

External

REF5025 REFP0, REFN0 2.5 V U2 Output on J5 (REF5025) —

Ratiometric REFP1, REFN1 Variable R11 REFP1, REFN1 Used for RTD measurements

User-provided REFP1, REFN1 Variable J6 (REFP1, REFN1) REFP1, REFN1 Remove R11

Figure 3-3. ADS1x48EVM VREF Options (Yellow) and Test Points (Red)





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3.3 Clock OptionsThe ADS1x48 integrates a 4.096-MHz clock oscillator to provide the clock signal to the ADC. Additionally, the ADS1x48 offers an external CLK input pin if an external clock signal is required. Choose between these flexible clock options using the JP2 header on the ADS1x48EVM.

Enable the internal oscillator by connecting the shunt to the JP2-3 pin on the JP2 header. This pin is marked GND on the ADS1x48EVM silkscreen. Enable an external clock by connecting the shunt to the JP2-1 pin on the JP2 header. This pin is marked EXT_CLK on the ADS1x48EVM silkscreen. When the external clock option is chosen, provide the external clock signal via the J4-40 pin on the J4 header. This pin and jumper JP2 are highlighted in Figure 3-4.

Figure 3-4. ADC Clock Options on the ADS1x48EVM




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3.4 Digital InterfaceThe ADS1x48 devices support the digital SPI and functional modes as detailed in the 24-bit ADS1248 data sheet or the 16-bit ADS1148 data sheet. As stated in Section 3.1, the PAMBoard operates at a 3.3-V logic level provided by the host computer and the ADS1x48EVM board uses this same 3.3-V logic level for DVDD.

Digital interface connections from the ADS1x48EVM to the PAMBoard include power, I2C, SPI, and a GPIO connection used to trigger an interrupt at the end of conversion that signifies new data are available. The digital connections are highlighted in the silkscreen shown in Figure 3-5 and are described in detail in Table 3-2. Use these connection points for troubleshooting the SPI communication with a logic analyzer or to attach an external MCU to control the ADS1x48EVM without the PAMBoard.

Figure 3-5. ADS1x48EVM-to-PAMBoard Connections

Table 3-2. ADS1x48EVM Header Pinout and DescriptionDescription Connector Connector Description Description Connector Connector Connector

3.3 V

J1:1 J3:21 5 V J4:40 J2:20

GND

J1:2 J3:22 GND J4:39 J2:19

J1:3 J3:23 J4:38 J2:18

J1:4 J3:24 RESET J4:37 J2:17

J1:5 J3:25 J4:36 J2:16

J1:6 J3:26 J4:35 J2:15 DIN

SPI SCLKJ1:7 J3:27 J4:34 J2:14

DOUT/DRDYJ1:8 J3:28 START J4:33 J2:13

I2C SCL J1:9 J3:29 J4:32 J2:12 SPI CS

I2C SDA J1:10 J3:30 DRDY J4:31 J2:11 SPI CS





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3.5 Analog Input ConnectionsThe ADS1x48EVM is designed for easy interface to external temperature sensors using the two screw terminal blocks (J5 and J6). Connector J5 provides connections for thermocouples and thermistors as well as the 2.048-V output voltage from the ADS1x48 integrated reference and the dedicated 2.5-V output from the REF5025. Connector J6 includes a pair of differential reference inputs for connecting an external voltage reference source to the ADC as well as three dedicated terminals for connecting a 2-, 3-, or 4-wire RTD. Table 3-3 summarizes the channel input connections for J5 and J6. Both connectors are clearly labeled on the PCB silkscreen for easy input connection identification. Figure 3-6 shows the input layout.

Table 3-3. ADS1x48EVM Terminal Block Input Description (J5 and J6)Terminal Block Input Label Description

J5:1 TC+ Positive thermocouple, general-purpose input

J5:2 TC– Negative thermocouple, general-purpose input

J5:3 REF5025 2.5-V output from REF5025

J5:4 REFOUT 2.048-V output from ADS1x48 integrated VREF

J5:5 NTC+ Positive thermistor input

J5:6 NTC– Negative thermistor input

J6:1 REFP1 Positive external VREF input to ADC

J6:2 REFN1 Negative external VREF input to ADC

J6:3 RTD_A RTD connection point A

J6:4 RTD_B RTD connection point B

J6:5 RTD_C RTD connection point C

J6:6 GND Analog ground

Figure 3-6. ADS1x48EVM Analog Input Terminal Blocks (J5, Left; J6, Right)

The following sections describe how to connect each different analog temperature sensor to its respective connector, beginning with terminal block J5.




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3.5.1 Connecting a Thermocouple to J5 on the ADS1x48EVM

Connect an external thermocouple directly to the J5:1 and J5:2 inputs on the J5 terminal block, which represent the TC+ and TC– nets, respectively. The differential filter for this differential input pair has a cutoff frequency of 1.93 kHz. Additionally, each input has a common-mode filter with a cutoff frequency of 38.63 kHz. TC+ and TC– are connected through the filter resistors to two analog inputs (AIN4 and AIN5, respectively) on the ADS1x48. Figure 3-7 shows the portion of the ADS1x48EVM schematic with J5 and the thermocouple input structure.

10.0MR24

DNP

AVDD

10.0MR23

DNP

4.12k

R16

4.12k

R13

0.01uFC101000pF

C3

1000pFC4

1

2

3

4

5

6

J5

REFOUTREF5025

TC+

TC-

NTC+NTC-

TC+TC-

AIN4

AIN5

GND

GND

Figure 3-7. Thermocouple Input Structure on the ADS1x48EVM

Although thermocouples are self-powered, these components must be biased in order to avoid floating beyond the input range of the PGA integrated into the ADC. The ADS1x48EVM offers multiple ways to bias the thermocouple so that the output voltage can be successfully read by the ADC.

The first method uses pullup and pulldown resistors, which are labeled in Figure 3-7 as R24 and R23, respectively. These resistors are do not place (DNP) and therefore do not come installed on the EVM. To use the pullup and pulldown resistor method, install 1-MΩ to 10-MΩ resistors in the aforementioned locations. With these resistors installed, the thermocouple output voltage is centered at AVDD / 2, which puts the output voltage in the middle of the common-mode range of the PGA integrated into the ADS1x48. Additionally, using pullup and pulldown resistors enables continuous sensor break detection. If one of the thermocouple wires breaks, AIN4 is pulled to AVDD and AIN5 is pulled to GND, resulting in a full-scale input that can be detected in a separate firmware routine.

The second thermocouple-biasing method supported by the ADS1x48EVM uses one of the two reference voltage output pins to bias TC–. For example, Figure 3-8 shows that connecting an external jumper between the TC– input (J5:2) and the REF5025 output (J5:3) biases the thermocouple voltage to 2.5 V.

REFOUT

REF5025

TC+

TC±

Thermocouple

External

Jumper

AIN4

AIN5

+2.5 V

+2.048 V

Figure 3-8. Using REF5025 (input J5:3) to Bias a Thermocouple

If AVDD = 5 V in the configuration shown in Figure 3-8, the thermocouple output voltage is now centered in the middle of common-mode range of the PGA integrated in the ADS1x48. If AVDD is instead chosen to be 3.3 V,





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connect the external jumper between the REFOUT pin (J5:4) and the TC– input to bias the thermocouple output voltage to 2.048 V. Although this voltage is not equal to AVDD / 2 = 1.65 V, connecting TC– to REFOUT when AVDD = 3.3 V enables a wider PGA common-mode voltage swing compared to using the REF5025 output. An external bias voltage can also be directly connected to TC–.

One challenge with the biasing scheme in Figure 3-8 is that this configuration does not offer continuous wire-break detection. Instead, a separate diagnostic measurement can be made, or the pullup resistor (R24) in Figure 3-7 can be populated to help perform this function. To learn more about different thermocouple biasing schemes as well as how to measure these sensors with precision ADCs, see the A Basic Guide to Thermocouple Measurements application report. This document also discusses the need for cold junction compensation (CJC), which is used in conjunction with the thermocouple voltage to derive the measured temperature. The ADS1x48EVM includes provisions for a CJC measurement using a thermistor, which is discussed in more detail in the next section.

The steps for setting up a thermocouple measurement with the ADS1x48EVM are summarized below:

1. Connect the sensor to the TC± terminals on J52. Select a biasing scheme:

a. For pullup and pulldown resistor biasing, populate R24 and R23, respectivelyb. For constant voltage biasing:

i. Connect an external jumper between TC– and REF5025 or REFOUTii. Apply an external voltage to TC–

3. Choose the ADC measurement channels to be MUX_SP[2:0] = AIN4 and MUX_SN[2:0] = AIN54. Select the ADC reference source (REF5025, internal VREF, or external VREF)




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3.5.2 Connecting a Thermistor to J5 on the ADS1x48EVM

Unlike a thermocouple, thermistors are not self-powered and require a constant voltage or current source to operate. Typically, constant voltage is preferred because the thermistor impedance can vary from hundreds of ohms at low temperature to hundreds of thousands of ohms at high temperature (or vice versa for a thermistor with a negative temperature coefficient). A resistor is then added in series with the thermistor to create a resistor divider that can be measured by an ADC.

Connect an external thermistor directly to the J5:5 and J5:6 pins on the J5 terminal block, which represent the NTC+ and NTC– nets, respectively. The differential filter for this differential input pair has a cutoff frequency of 1.93 kHz. Additionally, each input has a common-mode filter with a cutoff frequency of 38.63 kHz. NTC+ and NTC– are connected through the filter resistors to two analog inputs (AIN6 and AIN7, respectively) on the ADS1x48. Figure 3-9 shows the portion of the ADS1x48EVM schematic with J5 and the thermistor input structure.

0.01uFC121000pF

C7

1000pFC8

4.12k

R21

4.12k

R22

1

2

3

4

5

6

J5

10.0kR17

REFOUTREF5025

NTC+

NTC-

NTC+NTC-

TC+TC-

AIN6

AIN7

10.0kR14

DNP

GND

GND

10k

t°RT1DNP

Figure 3-9. Thermistor Input Structure on the ADS1x48EVM

Figure 3-9 shows two DNP components: a thermistor (RT1) and a 10-kΩ linearization resistor (R14). RT1 can be used for CJC for thermocouple measurements (see Section 3.5.2.1). R14 helps linearize the thermistor output voltage over a smaller temperature range. See section 2.8.2 in the A Basic Guide to Thermocouple Measurements application report to learn more about the benefits of using a linearization resistor when measuring a thermistor. Finally, resistor R17 in Figure 3-9 is the bias resistor used in conjunction with the external resistor to form a resistor divider. Resistor R17 is chosen to be 10 kΩ because 10 kΩ is a commonly-used nominal thermistor impedance. Choosing both resistors to have the same nominal impedance balances the resistor divider at 25°C.

As stated earlier in this section, thermistors are not self-powered and require a bias source to operate. As Figure 3-10 shows, connect the constant voltage output from REFOUT to NTC+ via an external jumper to bias the sensor. Alternatively, NTC+ can be connected to the REF5025 output instead. In either case, ensure that the reference output used to bias the resistor divider is the same reference selected for the ADC measurements.

External

Jumper

R17

NTC±

NTC+

REF5025

REFOUT

NTC

AIN6

AIN7

+2.5 V

+2.048 V

Figure 3-10. Connecting a Thermistor to the J5 Terminal Block on the ADS1x48EVM







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The steps for setting up a thermistor measurement with the ADS1x48EVM are summarized below:

1. Connect the sensor to the NTC± terminals on J52. Connect an external jumper between NTC+ and REF5025 or REFOUT3. Populate R14 with a 10-kΩ resistor if necessary4. Choose the ADC measurement channels to be MUX_SP[2:0] = AIN6 and MUX_SN[2:0] = AIN75. Select the ADC reference source to be the same constant voltage output from step #2

3.5.2.1 Using Thermistor RT1 for Thermocouple Cold Junction Compensation

The ADS1x48EVM board includes provisions for using a PCB-mounted thermistor to measure the cold junction of a thermocouple connected to the TC+ and TC– inputs on J5. As Figure 3-11 shows, top- and bottom-layer copper pours create an isothermal bridge between the NTC± and TC± inputs. This bridge helps ensure that thermistor RT1 measures the same temperature as the thermocouple cold junction at inputs J5:1 and J5:2, enabling a more accurate thermocouple measurement.

Figure 3-11. PCB Layout for J5 Terminal Block Showing Copper Pours for CJC Measurement

As discussed in Section 3.5.2 and in Figure 3-9, thermistor RT1 is not populated by default on the ADS1x48EVM. Choose a 10-kΩ NTC thermistor in a 0603 package for this component. To measure the thermistor voltage, follow the steps outlined at the end of Section 3.5.2, noting that step #1 (connect the sensor) is satisfied by soldering the thermistor (RT1) to the PCB. Also, the ADS1x48 is a multiplexed ADC and therefore can only measure one single-ended or differential input per conversion cycle. As a result, the thermocouple and CJC measurements must be taken separately and then manipulated in software to determine the resulting temperature. To learn more about CJC as well as how to use this value to determine the true measured temperature, see the A Basic Guide to Thermocouple Measurements application report.




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3.5.3 Connecting an RTD to J6 on the ADS1x48EVM

The RTD input connections on J6 are J6:3, J6:4, and J6:5, which correspond to the RTD_A, RTD_B, and RTD_C nets, respectively. Additionally, terminal block J6 provides a pair of differential reference inputs, REFP1 and REFN1, which correspond to inputs J6:1 and J6:2, respectively. The RTD_A, RTD_B and REFP1, REFN1 input pairs have a differential filter with a cutoff frequency of 1.93 kHz. Additionally, each of these inputs has a common-mode filter with a cutoff frequency of 38.63 kHz. Figure 3-12 shows the RTD input structure on the ADS1x48EVM, and Table 3-4 describes the mapping between the terminal block connections, schematic net names, and the analog pins on the ADS1x48. Some nets may connect to multiple analog pins on the ADS1x48.

REFP1REFN1

REFP1

REFN1

4.12k

R20

4.12k

R28

0.01uFC18

1000pFC21

1000pFC11

AIN3

AIN2

680

R18 IEXC2

RTD_A

RTD_B

RTD_ARTD_B

680

R29 IEXC1

RTD_C

AIN1

AIN0

RTD_C

0.01uFC51000pF

C2

1000pFC6

4.12k

R10

4.12k

R12

4.02kR11

GND

GND

GND

1

2

3

4

5

6

J6

GND

GND

JP3

JP4

JP5

JP6

Figure 3-12. RTD Input Structure on the ADS1x48EVM

Table 3-4. ADS1x48EVM Terminal Block (J6) to ADC ConnectionsConnector Net Name ADS1x48 Input Connection Description

J6:1 REFP1REFP1 External reference input (positive)

AIN1 Analog input 1

J6:2 REFN1REFN1 External reference input (negative)

AIN0 Analog input 0

J6:3 RTD_AAIN2 Analog input 2

IEXC2 Excitation current source #2

J6:4 RTD_BAIN3 Analog input 3

IEXC1 Excitation current source #1

J6:5 RTD_C IEXC1 Excitation current source #1

J6:6 GND n/a Analog ground

In Figure 3-12, resistor R11 is the reference resistor (RREF) that is placed in series with the RTD and connected to the ADS1x48 external reference inputs, as described in Table 3-4. An excitation current supplied by one of the two IDACs integrated into the ADS1x48 flows through RREF and the RTD, creating a ratiometric relationship





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between the analog input and reference voltages. As a result, the absolute IDAC accuracy is less critical and the system performance improves. However, choose the IDAC current magnitude and the total circuit impedance to ensure that the ADC IDAC compliance voltage is met. For additional information regarding ratiometric references, RTD measurement circuits using precision ADCs, and important specifications including compliance voltage, see the A Basic Guide to RTD Measurements application report.

R11 is chosen to be 4.02 kΩ in order to accommodate high-impedance RTDs at high temperature ranges. For example, a Pt1000 at 850°C has a typical impedance of approximately 3.9 kΩ. If a smaller measurement range is required, replace R11 with a different resistor in an 0805 package or remove R11 and use an external resistor connected between REFP1 and REFN1 on J6. Choose a high accuracy, low-drift resistor to ensure best system performance.

All common RTD configurations can be measured with the ADS1x48EVM, including:

• 2-wire RTD using a low-side RREF• 2-wire RTD using a high-side RREF• 3-wire RTD using one IDAC and a low-side RREF• 3-wire RTD using one IDAC and a high-side RREF• 3-wire RTD using two IDACs and a low-side RREF• 3-wire RTD using two IDACs and a high-side RREF• 4-wire RTD using a low-side RREF• 4-wire RTD using a high-side RREF

The ADS1x48EVM accomplishes maximum flexibility using jumpers JP3, JP4, JP5, and JP6 (see Figure 3-12) in conjunction with different analog inputs and IDAC routing. The following subsections detail the appropriate connections and settings to enable each RTD configuration using the ADS1x48EVM. Each subsection contains a connection diagram where the red lines indicate how current flows in the circuit. Moreover, the red text indicates which jumpers are populated and which current sources are biasing the RTD, and the blue text indicates the measurement channels. This information is summarized in Section 3.5.3.9.





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3.5.3.1 Connecting a 2-Wire RTD Using a Low-Side RREF to J6 on the ADS1x48EVM

Figure 3-13 shows how to connect a 2-wire RTD using a low-side RREF configuration to J6.

AIN1

REFP1

REFN1

AIN0

REFP1

REFN1

RTD

RTD_A

RTD_B

RTD_C

IEXC1

AIN3

AIN2

JP3

JP4

JP5

IEXC2IEXC2

IDAC

JP6

Figure 3-13. Connection Diagram for a 2-Wire RTD Using a Low-Side RREF

Figure 3-13 also shows that for this RTD configuration, the RTD is connected to REFP1 and RTD_B. Additionally, jumpers JP3 and JP4 are connected whereas jumpers JP5 and JP6 are disconnected. Finally, the IEXC1 current source is enabled and the measurement is taken between AIN3 and AIN1. Table 3-5 summarizes the necessary connections and ADC configuration settings.





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3.5.3.2 Connecting a 2-Wire RTD Using a High-Side RREF to J6 on the ADS1x48EVM

Figure 3-14 shows how to connect a 2-wire RTD using a high-side RREF configuration to J6.

REFP1

REFN1

AIN0

REFP1

REFN1

RTD

RTD_A

RTD_B

RTD_C

IEXC1

AIN3

AIN2

JP3

JP4

JP5

IEXC2IEXC2

AIN1

IDAC

JP6

Figure 3-14. Connection Diagram for a 2-Wire RTD Using a High-Side RREF

Figure 3-14 also shows that for this RTD configuration, the RTD is connected to REFN1 and RTD_B. Additionally, jumpers JP4, JP5, and JP6 are connected whereas jumper JP3 is disconnected. Finally, the AIN1 pin on the ADS1x48 is configured to be a current source and the measurement is taken between AIN0 and AIN3. Table 3-5 summarizes the necessary connections and ADC configuration settings.




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3.5.3.3 Connecting a 3-Wire RTD Using One IDAC and a Low-Side RREF to J6 on the ADS1x48EVM

Figure 3-15 shows how to connect a 3-wire RTD using one IDAC and a low-side RREF configuration to J6.

REFP1

REFN1

AIN0

REFP1

REFN1

RTD

RTD_A

RTD_B

RTD_C

IEXC1

AIN3

AIN2

JP3

JP4

JP5

IEXC2IEXC2

AIN1

IDAC

JP6

Figure 3-15. Connection Diagram for a 3-Wire RTD Using One IDAC and a Low-Side RREF

Figure 3-15 also shows that for this RTD configuration, the RTD is connected to REFP1, RTD_A, and RTD_B. Additionally, jumpers JP3 and JP4 are connected whereas jumpers JP5 and JP6 are disconnected. Moreover, the IEXC1 current source is enabled. Finally, this specific configuration requires two measurements for lead-wire cancellation: the first is between AIN3 and AIN2, and the second is between AIN2 and AIN1. Table 3-5 summarizes the necessary connections and ADC configuration settings.





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3.5.3.4 Connecting a 3-Wire RTD Using One IDAC and a High-Side RREF to J6 on the ADS1x48EVM

Figure 3-16 shows how to connect a 3-wire RTD using one IDAC and a high-side RREF configuration to J6.

REFP1

REFN1

AIN0

REFP1

REFN1

RTD_A

RTD_B

RTD_C

IEXC1

AIN3

AIN2

JP3

JP4

JP5

IEXC2IEXC2RTD

AIN1

IDAC

JP6

Figure 3-16. Connection Diagram for a 3-Wire RTD Using One IDAC and a High-Side RREF

Figure 3-16 also shows that for this RTD configuration, the RTD is connected to REFN1, RTD_A, and RTD_B. Additionally, jumpers JP4, JP5, and JP6 are connected whereas jumper JP3 is disconnected. Moreover, the AIN1 pin on the ADS1x48 is configured to be a current source. Finally, this specific configuration requires two measurements for lead-wire cancellation: the first is between AIN0 and AIN2 and, the second is between AIN2 and AIN3. Table 3-5 summarizes the necessary connections and ADC configuration settings.




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3.5.3.5 Connecting a 3-Wire RTD Using Two IDACs and a Low-Side RREF to J6 on the ADS1x48EVM

Figure 3-17 shows how to connect a 3-wire RTD using two IDACs and a low-side RREF configuration to J6.

REFP1

REFN1

AIN0

REFP1

REFN1

RTD

RTD_A

RTD_B

RTD_C

IEXC1

AIN3

AIN2

JP3

JP4

JP5

IEXC2IEXC2

AIN1

IDAC

JP6

Figure 3-17. Connection Diagram for a 3-Wire RTD Using Two IDACs and a Low-Side RREF

Figure 3-17 also shows that for this RTD configuration, the RTD is connected to REFP1, RTD_A, and RTD_B. Additionally, jumpers JP3 and JP4 are connected whereas jumpers JP5 and JP6 are disconnected. Finally, the IEXC1 and IEXC2 current sources are enabled and the measurement is taken between AIN3 and AIN2. Table 3-5 summarizes the necessary connections and ADC configuration settings.





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3.5.3.6 Connecting a 3-Wire RTD Using Two IDACs and a High-Side RREF to J6 on the ADS1x48EVM

Figure 3-18 shows how to connect a 3-wire RTD using two IDACs and a high-side RREF configuration to J6.

REFP1

REFN1

AIN0

REFP1

REFN1

RTD_A

RTD_B

RTD_C

IEXC1

AIN3

AIN2

JP3

JP4

JP5

RTD

IEXC2IEXC2

AIN1

IDAC

JP6

Figure 3-18. Connection Diagram for a 3-Wire RTD Using Two IDACs and a High-Side RREF

Figure 3-18 also shows that for this RTD configuration, the RTD is connected to REFN1, RTD_A, and RTD_B. Additionally, jumpers JP4, JP5, and JP6 are connected whereas jumper JP3 is disconnected. Finally, the AIN1 pin on the ADS1x48 is configured to be a current source and is used in conjunction with the IEXC1 current source, while the measurement is taken between AIN0 and AIN2. Table 3-5 summarizes the necessary connections and ADC configuration settings.




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3.5.3.7 Connecting a 4-Wire RTD Using a Low-Side RREF to J6 on the ADS1x48EVM

Figure 3-19 shows how to connect a 4-wire RTD using a low-side RREF configuration to J6.

REFP1

REFN1

AIN0

REFP1

REFN1

RTD

RTD_A

RTD_B

RTD_C

IEXC1

AIN3

AIN2

JP3

JP4

JP5

IEXC2IEXC2

AIN1

IDAC

JP6

Figure 3-19. Connection Diagram for a 4-Wire RTD Using a Low-Side RREF

Figure 3-19 also shows that for this RTD configuration, the RTD is connected to REFP1, RTD_A, RTD_B, and RTD_C. Additionally, jumper JP3 is connected whereas jumpers JP4, JP5, and JP6 are disconnected. Finally, the IEXC1 current source is enabled and the measurement is taken between AIN3 and AIN2. Table 3-5 summarizes the necessary connections and ADC configuration settings.





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3.5.3.8 Connecting a 4-Wire RTD Using a High-Side RREF to J6 on the ADS1x48EVM

Figure 3-20 shows how to connect a 4-wire RTD using a high-side RREF configuration to J6.

REFP1

REFN1

AIN0

REFP1

REFN1

RTD

RTD_A

RTD_B

RTD_C

IEXC1

AIN3

AIN2

JP3

JP4

JP5

IEXC2IEXC2

AIN1

IDAC

JP6

Figure 3-20. Connection Diagram for a 4-Wire RTD Using a High-Side RREF

Figure 3-20 also shows that for this RTD configuration, the RTD is connected to REFN1, RTD_A, RTD_B, and RTD_C. Additionally, jumpers JP5 and JP6 are connected whereas jumpers JP3 and JP4 are disconnected. Finally, the AIN1 pin on the ADS1x48 is configured to be a current source and the measurement is taken between AIN2 and AIN3. Table 3-5 summarizes the necessary connections and ADC configuration settings.

3.5.3.9 Summary of ADS1x48EVM RTD Configuration Settings

Table 3-5 summarizes the required IDAC, jumper, and analog input channel settings to measure each RTD configuration using the ADS1x48EVM.

Table 3-5. ADS1x48EVM Settings for Different RTD TypesRTD No. of IDACs RREF IDAC Channels JP3 JP4 JP5 JP6 AINP AINN

2-wire1 Low-side IEXC1 On On Off Off AIN3 AIN1

1 High-side AIN1 Off On On On AIN0 AIN3

3-wire

1 Low-side IEXC1 On On Off OffAIN3(1) AIN2(1)

AIN2(2) AIN1(2)

1 High-side AIN1 Off On On OnAIN0(1) AIN2(1)

AIN2(2) AIN3(2)

2 Low-side IEXC1, IEXC2 On On Off Off AIN3 AIN2

2 High-side AIN1, IEXC2 Off On On On AIN0 AIN2

4-wire1 Low-side IEXC1 On Off Off Off AIN3 AIN2

1 High-side AIN1 Off Off On On AIN2 AIN3

(1) First measurement.(2) Second measurement.




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3.5.4 Connecting a General-Purpose Input to J5 on the ADS1x48EVM

Although the ADS1x48EVM is designed for measuring all types of analog temperature sensors, general-purpose input signals can be applied to the ADS1x48 through the TC± inputs on the J5 terminal block. Figure 3-21 shows the input structure used for the TC± inputs.

10.0MR24

DNP

AVDD

10.0MR23

DNP

4.12k

R16

4.12k

R13

0.01uFC101000pF

C3

1000pFC4

1

2

3

4

5

6

J5

REFOUTREF5025

TC+

TC-

NTC+NTC-

TC+TC-

AIN4

AIN5

GND

GND

Figure 3-21. Using the TC± Inputs on J5 as General-Purpose Signal Inputs

As Figure 3-21 shows, resistors R24 and R23 are not populated by default, resulting in a set of analog inputs that are only subject to the differential filter cutoff frequency of 1.93 kHz and the common-mode filter cutoff frequency of 38.63 kHz. The TC± inputs can therefore be used for any general input signal as long as the ADS1x48 absolute input and common-mode range requirements are satisfied. Select the AIN4 and AIN5 inputs on the ADS1x48 to measure a voltage connected to the TC± inputs.





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4 ADS1x48EVM GUIThe ADS1x48EVM requires a communication driver that is installed automatically. However, this FAQ can help troubleshoot driver-related issues if any arise.

The following steps describe the ADS1x48 GUI software installation:

1. Connect the micro-USB-to-USB cable from the PAMBoard directly to a USB port on the computer. Do not connect the cable through a USB hub.

2. Open up the web-based GUI available on the EVM landing page (ADS1148EVM-PDK or ADS1248EVM-PDK).a. First-time users may be prompted to download and install the browser extension for Firefox™ or

Chrome™ and the TI Cloud Agent Application as shown in Figure 4-1. Installing the TI Cloud Agent is a one-time download and installation.

3. Refresh the GUI such that a green signal displays and the Hardware Connected indicator shows in the bottom status ribbon (see Figure 4-2).

Figure 4-1. Browser Extension and TI Cloud Agent Installation

When connected, the ADS1x48EVM GUI has multiple pages to help navigate and control the ADS1x48EVM:

• Home• Data Capture• Register Map

The following sections step through each GUI page in more detail.

4.1 HomeThe Home page is the GUI start-up landing page. The Home page provides a high-level overview of the ADS1x48 including a device description and a 3D view of the EVM PCB. Highlighted in orange in the upper-left corner of Figure 4-2 is a vertical Navigation bar for the various GUI pages, including:

• Home• Data Capture• Register Map

The horizontal Menu bar at the top of the GUI shows the following menu options, which are highlighted in blue in Figure 4-2 and are discussed in more detail in Section 4.1.1:

• File• Options• Tools• Help

Quick links to Support Resources are shown at the bottom of the Home page. These links are highlighted in purple in Figure 4-2 and include the EVM user's guide, schematic, and ADC data sheet. Finally, a successfully connected EVM displays as Device Connected in the top left and as Hardware Connected in the status ribbon. Both of these indicators are highlighted in green in Figure 4-2.

ADS1x48EVM GUI www.ti.com



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Figure 4-2. ADS1x48EVM GUI Home Page

One other important feature of the Home page is an information icon next to the device name. Clicking the icon, as shown in Figure 4-3, displays specific information regarding the ADS1x48EVM.

Figure 4-3. Connected Hardware Information

www.ti.com ADS1x48EVM GUI




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4.1.1 Menu Bar

The Menu bar across the top of the GUI displays the device name used on the EVM along with a number of drop-down menu options.

4.1.1.1 File Menu

The File drop-down menu displays the available options shown in Figure 4-4. These options include:

• Program Device: Only necessary if an important firmware change is required• Analysis Data:

– Save data: Save the Analysis Data to a comma-separated values (CSV) formatted file for further analysis using external programs

– Load data: Loads a saved data file back into the GUI for further review or analysis• Register Data

– Save register: Save the register data for a specific configuration– Load register: Load a previously saved register map configuration

Figure 4-4. File Menu

4.1.1.2 Options Menu

The Options drop-down provides a way to display the current COM port settings in a pop-up dialog with options to change the COM port or reconfigure the settings as necessary.

4.1.1.3 Tools Menu

The Tools drop-down menu offers access to the Log pane that displays an activity log at the bottom of the GUI. Clicking the book icon in the status ribbon displays the same information as selecting Log pane in the Tools menu.

4.1.1.4 Help Menu

The Help drop-down menu displays the following options:

• E2E Support Forum links to the E2E forum in order to ask questions or search for answers• View README.md displays pertinent start-up information not necessarily included in this guide• About displays specific information regarding the GUI and EVM hardware to help confirm that the latest

version of the GUI is being used




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4.2 Data CaptureThe Data Capture icon selects the available charting options for displaying conversion data. The data options, as shown in Figure 4-5, include the Time Domain, Histogram, and FFT displays. However, the FFT plot and information may have little meaning because the ADS1x48 is primarily a dc measurement device.

Figure 4-5. Data Capture Window

A slide-out menu (as shown in Figure 4-6) is viewable on the right side of the Chart window. By clicking the Show Capture Settings slide-out, various configurations and displays are selectable. The drop-down menus available in the Capture Settings slide-out are:

• Select data rate for the data output conversion rate• Select MUXP channels and Select MUXN channels for choosing the desired input channels to be measured• Select PGA for choosing the required input signal amplification• SELFOCAL button for performing a device (ADC) offset calibration

Figure 4-6. Capture Settings Slide-Out

To collect data, select the number of Samples to collect in the upper right corner of the capture window. To capture data, press the Collect Data button next to the Samples setting (shown in Figure 4-5).

Conversion data collects when the Collect Data button is pressed, after which the button changes to read Stop Collect. Pressing the Stop Collect button stops the collection of conversion data; otherwise the data are collected for the chosen number of Samples. The number of Samples can be changed prior to pressing Collect Data by directly entering the desired number of samples or by clicking on the up and down arrows. The number of samples cannot be changed while data are being collected.





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When the Collect Data operation is complete, the data displays the calculated channel statistics and a plot of the data in the chart window. Various icons for viewing the data include zoom, pan, and home. The home icon restores the graph to show all data collected. The viewing icons are underneath the statistics information on the right side of the GUI.

4.2.1 Time Domain and Histogram Statistics

The Time Domain and Histogram plots share the same statistical information shown in Figure 4-7:

• Input Channels selected• Min code within the data set• Max code within the data set• Mean code value within the data set• Std Dev representing the standard deviation within the data set• Pk-to-Pk representing the total noise peak-to-peak within the data set• Eff. Res representing the effective resolution as number of bits with the value in parenthesis showing the

noise-free number of bits

Figure 4-7. Capture Statistics

4.2.2 Time Domain Plot

The Time Domain plot displays the sample count number in the X-axis. The Y-axis is displayed as either codes or volts with the selection in a drop-down menu. The Y-axis drop-down menu displays next to the charting icons near the right side of the GUI below the statistics. Figure 4-8 shows the Time Domain plot and its features.

Figure 4-8. Time Domain Plot




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4.2.3 Histogram Plot

The Histogram plot in Figure 4-9 shows the number of occurrences that a code or group of codes appear. User selection includes a choice of:

• # of Bins selects the number of bins to include in the plot• Bin Size selects the number of unique codes to include in each bin

Figure 4-9. Histogram Plot

The # Bins and Bin Size are selectable options and display next to the charting icons near the right side of the GUI below the statistics.

4.2.4 FFT Statistics and Plot

The FFT plot displays the following statistics:

• Input Channels selected• Fundamental frequency• Fundamental power• Noise floor• SNR or signal-to-noise ratio• SFDR or spurious-free dynamic range• THD or total harmonic distortion• SINAD or signal-to-noise and distortion• ENOB or effective number of bits• Harmonics

The FFT plot is rather meaningless for dc input voltages. However, a low-frequency ac signal can be analyzed and the FFT plot displayed.4.3 Register MapThe Register Map window contains information about the how the ADS1x48 is configured. A number of control buttons and drop-down menus exist to configure the Register Map read and write operations.

Throughout the Register Map window question mark icons appear. Clicking on these icons provides details pertaining to the items in the locations where they appear. See Figure 4-10 for more details.





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Figure 4-10. Register Map

As shown in Figure 4-10, the ADS1x48 devices have many configurable registers. Configure these registers by using the drop-down menu and clickable options shown in the Field View menu on the right side of the GUI window. The Field View menu replicates the register setting information provided in the ADS1x48 data sheets. Reference these documents for additional information about or questions related to the specific ADC register settings.

Instead of using the Field View menu, the 1's and 0's can also be double-clicked in the Bits menu to toggle the bit settings. As the bit settings change, the Field View options also change to the corresponding register setting.

4.3.1 Register Read and Write Options

Figure 4-11 highlights the top of the Register Map window where reading from and writing to registers is controlled. The default behavior has the Auto Read register function turned off as well as performs an Immediately Write operation on the Config register when options change. All read and write options are discussed in more detail in the next sections.

Figure 4-11. Register Read and Write Controls




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4.3.1.1 Read Register Options

As stated in the previous section, the default GUI configuration has the Auto Read functionality turned off and instead manually reads the registers using the READ REGISTER and READ ALL REGISTERS buttons. The READ REGISTER button reads only the selected register. The READ ALL REGISTERS button reads all available ADS1x48 registers. The advantage of manually reading the register contents is reduced USB communication between the ADS1x48EVM and the GUI.

The registers can be read automatically from the ADS1x48 at a variety of intervals from once per second to as fast as possible. As shown in Figure 4-12, the intervals can be reviewed and selected using the Auto Read drop-down menu. The READ REGISTER and READ ALL REGISTER button options are only enabled when the Auto Read selection is turned off.

Figure 4-12. Auto Read Options

4.3.1.2 Write Register Options

The GUI default option for register writes is Immediate Write. When Immediate Write is selected, any register configuration changes are immediately written from the GUI to the ADS1x48 device. Using the Immediate Write option ensures that what is being displayed in the register map view is how the ADS1x48 is configured. If the write register drop-down menu selection is for a Deferred Write as shown in Figure 4-13, then the write register buttons WRITE REGISTER and WRITE ALL REGISTERS are enabled. Similar to the functionality of the read register buttons, the WRITE REGISTER button writes the configuration for the currently selected register. Comparatively, selecting the WRITE ALL REGISTERS button writes to all configurable registers.

Figure 4-13. Register Write Options





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5 Bill of Materials, Printed Circuit Board Layout, and SchematicThis section contains the ADS1x48EVM bill of materials (BOM), printed-circuit board (PCB) layout, and board schematic.

5.1 Bill of MaterialsTable 5-1 lists the bill of materials (BOM) for the ADS1x48EVM.

Table 5-1. Bill of MaterialsDesignator Quantity Description Part Number ManufacturerC1, C5, C10, C12, C18 5 CAP, CERM, 0.01 uF, 25

V, +/- 5%, C0G/NP0, 0603C0603H103J3GACTU Kemet

C2, C3, C4, C6, C7, C8, C11, C21

8 CAP, CERM, 1000 pF, 100 V, +/- 5%, C0G/NP0, 0603

GRM1885C2A102JA01D MuRata

C9, C14, C15, C19, C23, C24

6 CAP, CERM, 10 uF, 25 V, +/- 20%, X5R, 0603

GRT188R61E106ME13D MuRata

C13, C20, C22 3 CAP, CERM, 0.1 uF, 25 V, +/- 10%, X7R, 0603

C0603C104K3RACTU Kemet

C16, C17 2 CAP, CERM, 1 uF, 25 V, +/- 10%, X7R, 0603

C0603C105K3RACTU Kemet

D1, D2 2 LED, Green, SMD 150060GS75000 Wurth Elektronik

J1/J3, J2/J4 2 Receptacle, 2.54mm, 10x2, Tin, TH

SSQ-110-03-T-D Samtec

J5, J6 2 Terminal Block, 3.5mm, 6x1, Tin, TH

0393570006 Molex

JP1, JP2 2 Header, 100mil, 3x1, Gold, TH

TSW-103-07-G-S Samtec

JP3, JP4, JP5, JP6 4 Header, 2mm, 2x1, Tin, TH

TMM-102-01-T-S Samtec

R1, R2, R7, R8, R17 5 RES, 10.0 k, 1%, 0.1 W, 0603

RC0603FR-0710KL Yageo

R3 1 RES, 470, 5%, 0.1 W, 0603

RC0603JR-07470RL Yageo

R4 1 RES, 390, 1%, 0.1 W, 0603

RC0603FR-07390RL Yageo

R5, R9, R27 3 RES, 100 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

CRCW0603100KFKEA Vishay-Dale

R6, R25 2 RES, 0.1, 1%, 0.1 W, AEC-Q200 Grade 1, 0603

ERJ-L03KF10CV Panasonic

R10, R12, R13, R16, R20, R21, R22, R28

8 RES, 4.12 k, 1%, 0.1 W, 0603

RC0603FR-074K12L Yageo

R11 1 RES, 4.02 k, 0.1%, 0.125 W, 0805

RT0805BRD074K02L Yageo America

R15 1 RES, 470 k, 1%, 0.1 W, 0603


R18, R29 2 RES, 680, 1%, 0.1 W, 0603

RC0603FR-07680RL Yageo

R19, R30, R31, R32, R33, R34, R35

7 RES, 47, 5%, 0.1 W, AEC-Q200 Grade 0, 0603

CRCW060347R0JNEA Vishay-Dale

R26 1 RES, 1.1, 5%, 0.125 W, AEC-Q200 Grade 0, 0805

ERJ-6GEYJ1R1V Panasonic

SH-JP1, SH-JP2 2 Shunt, 100mil, Gold plated, Black

SNT-100-BK-G Samtec

SH-JP3, SH-JP4, SH-JP5, SH-JP6

4 Shunt, 2mm, Gold plated, Black

2SN-BK-G Samtec

TP1 1 Test Point, Miniature, Black, TH

5001 Keystone

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Table 5-1. Bill of Materials (continued)Designator Quantity Description Part Number ManufacturerTP2 1 Test Point, Miniature,

White, TH5002 Keystone

U1 1 I2C BUS EEPROM (2-Wire), TSSOP-B8

BR24G32FVT-3AGE2 Rohm

U2 1 3 µVpp/V Noise, 3 ppm/°C Drift Precision Series Voltage Reference, DGK0008A (VSSOP-8)

REF5025IDGKT Texas Instruments

U3 1 24-Bit (or 16-bit), 2kSPS, 8-Ch, Delta-Sigma ADC for Precision Sensor Measurement, PW0028A (TSSOP-28)

ADS1248IPWR (or ADS1148IPWR)

Texas Instruments

R14 0 RES, 10.0 k, 1%, 0.1 W, 0603


R23, R24 0 RES, 10.0 M, 1%, 0.1 W, AEC-Q200 Grade 0, 0603

CRCW060310M0FKEA Vishay-Dale

RT1 0 Thermistor NTC, 10k ohm, 3%, 0603

ERT-J1VR103H Panasonic

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5.2 Printed Circuit Board LayoutFigure 5-1 to Figure 5-7 depict the ADS1x48EVM PCB layout.

Red = top layer; blue = bottom layer; yellow = top silkscreen; internal GND layers not shown

Figure 5-1. Composite PCB Layout




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Figure 5-2. Top Silkscreen Figure 5-3. Top Layer

Figure 5-4. Internal Ground Layer 1 Figure 5-5. Internal Ground Layer 2





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Figure 5-6. Bottom Layer Figure 5-7. Bottom Silkscreen




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5.3 SchematicFigure 5-8 shows the ADS1x48EVM schematic.

GPIO !31

GPIO !32

GPIO !33

GPIO !34

Timer_Cap/GPIO !35

Timer_Cap/GPIO !36

PWM/GPIO !37

PWM/GPIO !38

PWM/GPIO !39

PWM/GPIO !40

GPIO !11

SPI_CS/GPIO !12

SPI_CS/GPIO !13

SPI_MISO14

SPI_MOSI15

RST16

GPIO17

GPIO !18

PWM/GPIO !19

GND20

J2/J4

SSQ-110-03-T-D

+3.3V1

Analog_In2

LP_UART_RX3

LP_UART_TX4

GPIO !5

Analog In6

SPI_CLK7

GPIO !8

I2C_SCL9

I2C_SDA10

+5V21

GND22

Analog_In23

Analog_In24

Analog_In25

Analog_In26

Analog_In/I2S_WS27

Analog_In/I2S_SCLK28

Analog_Out/I2S_SDout29

Analog_Out/I2S_SDin30

J1/J3

SSQ-110-03-T-D

3V3 5V

DINDOUT_DRDY

DVDD1

GND2

CLK3

RESET4

REFP0/GPIO05

REFN0/GPIO16

REFP17

REFN18

VREFOUT9

VREFCOM10

AIN0/IEXC11

AIN1/IEXC12

AIN4/IEXC/GPIO413

AIN5/IEXC/GPIO514

AIN6/IEXC/GPIO615

AIN7/IEXC/GPIO716

AIN2/IEXC/GPIO217

AIN3/IEXC/GPIO318

IEXC219

IEXC120

AVSS21

AVDD22

START23

CS24

DRDY25

DOUT/DRDY26

DIN27

SCLK28

ADS1248IPWR

U3

SCLKDINDRDYDOUT_DRDYCS

RESET

AVDD

START

GND

GND

3V3 AVDD

470kR15

100kR9

3V3

GND

AVDD

1

2

3

JP1

A01

A12

A23

VSS4

SDA5

SCL6

WP7

VCC8

U1

BR24G32FVT-3AGE2

10.0k

R1

10.0kR2

GND

GND

EEPROM_WE

SCL_LP

SDA_LP

3V3

1

2

3

JP2

CLK_EXT

CLK_EXT

DRDY

0.1R6

3V3AVDD

GNDSCLKEEPROM_WESCL_LPSDA_LP

IEXC1IEXC2

START

10.0kR7

10.0kR8

10.0MR24

DNP

AVDD

10.0MR23

DNP

4.12k

R16

4.12k

R13

REFOUT

0.01uFC10

0.01uFC12

1000pFC3

1000pFC4

1000pFC7

1000pFC8

0.1R25

CS

100kR27

100kR5

3V3

GND

390R4

4.12k

R21

4.12k

R22

1

2

3

4

5

6

J5

REFP1REFN1

0.01uF

C1

REFP1

REFN1

AIN3AIN4AIN5

AIN2

AIN6AIN7

4.12k

R20

4.12k

R28

0.01uFC18

1000pFC21

1000pFC11

10.0kR17

REFOUTREF5025

AIN3

AIN2

NTC+

NTC-

TC+

TC-

NTC+NTC-

TC+TC-

AIN4

AIN5

AIN6

AIN7

680

R18 IEXC2

RTD_A

RTD_B

RTD_ARTD_B

680

R29 IEXC1

RTD_C

AIN0AIN1

REF5025

AIN1

AIN0

RTD_C

0.01uFC51000pF

C2

1000pFC6

4.12k

R10

4.12k

R12

4.02kR11

10.0kR14

DNP

RESET

47R19

47R3447R33

47R35

47R3247R3147R30

GNDGND GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

1

2

3

4

5

6

J6

GND

GND

TP2

TP1

10k

t°RT1DNP

1.1R26

1µFC16

1µFC17

100nFC20

100nFC22

100nFC13

10µF

C9

10µF

C14

10µF

C19

10µF

C23

10µF

C15

10µF

C24

REF5025IDGKT

VIN2

TEMP3

GND4

TRIM/NR5

VOUT6

U2A

REF5025IDGKT

DNC1

NC7

DNC8

U2B

470R3

Green

21

D1

Green

21

D2

JP3

JP4

JP5

JP6

Figure 5-8. ADS1x48EVM Schematic





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6 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from September 10, 2021 to January 11, 2022 (from Revision * (September 2021) to Revision A (January 2022)) Page• Deleted inclusive terminology from document.................................................................................................... 5• Changed EVM landing page links to correct locations throughout document.................................................... 6

Revision History www.ti.com



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STANDARD TERMS FOR EVALUATION MODULES1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or

documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordancewith the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility

evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are notfinished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. Forclarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditionsset forth herein but rather shall be subject to the applicable terms that accompany such Software

1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or productionsystem.

2 Limited Warranty and Related Remedies/Disclaimers:2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License

Agreement.2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM

to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused byneglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that havebeen altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specificationsor instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality controltechniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.

2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or creditUser's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warrantyperiod to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair orreplace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall bewarranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) daywarranty period.

WARNINGEvaluation Kits are intended solely for use by technically qualified,professional electronics experts who are familiar with the dangers

and application risks associated with handling electrical mechanicalcomponents, systems, and subsystems.

User shall operate the Evaluation Kit within TI’s recommendedguidelines and any applicable legal or environmental requirementsas well as reasonable and customary safeguards. Failure to set up

and/or operate the Evaluation Kit within TI’s recommendedguidelines may result in personal injury or death or propertydamage. Proper set up entails following TI’s instructions for

electrical ratings of interface circuits such as input, output andelectrical loads.

NOTE:EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATIONKIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.

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3 Regulatory Notices:3.1 United States

3.1.1 Notice applicable to EVMs not FCC-Approved:FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or softwareassociated with the kit to determine whether to incorporate such items in a finished product and software developers to writesoftware applications for use with the end product. This kit is not a finished product and when assembled may not be resold orotherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the conditionthat this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit mustoperate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTIONThis device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may notcause harmful interference, and (2) this device must accept any interference received, including interference that may causeundesired operation.Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority tooperate the equipment.

FCC Interference Statement for Class A EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment isoperated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if notinstalled and used in accordance with the instruction manual, may cause harmful interference to radio communications.Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required tocorrect the interference at his own expense.

FCC Interference Statement for Class B EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residentialinstallation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordancewith the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interferencewill not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, whichcan be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or moreof the following measures:

• Reorient or relocate the receiving antenna.• Increase the separation between the equipment and receiver.• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.• Consult the dealer or an experienced radio/TV technician for help.

3.2 Canada3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247

Concerning EVMs Including Radio Transmitters:This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:(1) this device may not cause interference, and (2) this device must accept any interference, including interference that maycause undesired operation of the device.

Concernant les EVMs avec appareils radio:Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitationest autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doitaccepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concerning EVMs Including Detachable Antennas:Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna typeand its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary forsuccessful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna typeslisted in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibitedfor use with this device.

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3

Concernant les EVMs avec antennes détachablesConformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type etd'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillageradioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotroperayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Leprésent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans lemanuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antennenon inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation del'émetteur

3.3 Japan3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に

輸入される評価用キット、ボードについては、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page

3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certifiedby TI as conforming to Technical Regulations of Radio Law of Japan.

If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow theinstructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal

Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule forEnforcement of Radio Law of Japan,

2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect toEVMs, or

3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japanwith respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please notethat if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.

【無線電波を送信する製品の開発キットをお使いになる際の注意事項】開発キットの中には技術基準適合証明を受けていないものがあります。技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用

いただく。2. 実験局の免許を取得後ご使用いただく。3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・イ

ンスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル

3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

3.4 European Union3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):

This is a class A product intended for use in environments other than domestic environments that are connected to alow-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment thisproduct may cause radio interference in which case the user may be required to take adequate measures.

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4 EVM Use Restrictions and Warnings:4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT

LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling

or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety informationrelated to, for example, temperatures and voltages.

4.3 Safety-Related Warnings and Restrictions:4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user

guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable andcustomary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to inputand output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, orproperty damage. If there are questions concerning performance ratings and specifications, User should contact a TIfield representative prior to connecting interface electronics including input power and intended loads. Any loads appliedoutside of the specified output range may also result in unintended and/or inaccurate operation and/or possiblepermanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting anyload to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuitcomponents may have elevated case temperatures. These components include but are not limited to linear regulators,switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using theinformation in the associated documentation. When working with the EVM, please be aware that the EVM may becomevery warm.

4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with thedangers and application risks associated with handling electrical mechanical components, systems, and subsystems.User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronicand/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safelylimit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility andliability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors ordesignees.

4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes allresponsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility andliability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and localrequirements.

5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurateas possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites asaccurate, complete, reliable, current, or error-free.

6. Disclaimers:6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT

LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALLFAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUTNOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESSFOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADESECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.

6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BECONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL ORINTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THEEVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY ORIMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.

7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITSLICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANYHANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLYWHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGALTHEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

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8. Limitations on Damages and Liability:8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,

INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESETERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OFSUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL ORREINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OFUSE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TIMORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HASOCCURRED.

8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDEDHEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR INCONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAREVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARECLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not ina resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicableorder, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),excluding any postage or packaging costs.

10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating tothese terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive reliefin any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2019, Texas Instruments Incorporated

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ADS1x48EVM Evaluation Module

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