ADMC(F)341 DashDSP 28-Lead Flash and ROM Memory, Mixed … · 2019. 6. 5. · –2– REV. A...

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ADMC(F)341

DashDSP® 28-Lead Flash andROM Memory, Mixed-Signal DSPswith Enhanced Analog Front Enda

FUNCTIONAL BLOCK DIAGRAM

DSP is a registered trademark of Analog Devices, Inc.

FEATURES20 MHz Fixed-Point DSP Core

Single-Cycle Instruction Execution (50 ns)ADSP-21xx Family Code CompatibilityIndependent Computational Units

ALU, Multiplier/Accumulator, Barrel ShifterMultifunction InstructionsSingle-Cycle Context SwitchPowerful Program Sequencer

Zero Overhead LoopingConditional Instruction Execution

2 Independent Data Address GeneratorsMemory Configuration

512 � 16-Bit Data Memory RAM512 � 24-Bit Program Memory RAM4K � 24-Bit Program Memory ROM4K � 24-Bit Program Flash Memory (ADMCF341 Only)

3 Independent Flash Memory Sectors3584 � 24-Bit, 256 � 24-Bit, 256 � 24-Bit

Low Cost, Pin Compatible ROM Option16-Bit Watchdog TimerProgrammable 16-Bit Internal Timer with Prescaler2 Double-Buffered Serial Ports with SPI Mode SupportIntegrated Power-On Reset Function3-Phase 16-Bit PWM Generation Unit:

16-Bit Center-Based PWM GeneratorProgrammable PWM PulsewidthEdge Resolution to 50 ns153 Hz Minimum Switching FrequencyDouble/Single Duty Cycle Update Mode Control

Individual Enable and Disable for Each PWM OutputHigh Frequency Chopping Mode for Transformer

Coupled Gate DrivesExternal PWMTRIP Pin

Integrated 6-Channel ADC Subsystem3 Bipolar ISENSE Inputs with Programmable

Sample-and-Hold Amplifier and OvercurrentProtection (Usable as 3 Dedicated Analog Inputs)

Muxed Auxiliary Analog InputsInternal Voltage Reference (2.5 V)Acquisition Synchronized to PWM Switching

Frequency9-Pin Digital I/O Port

Bit Configurable as Input or OutputChange of State Interrupt Support

2 16-Bit Auxiliary PWM TimersSynthesized Analog OutputProgrammable Frequency0% to 100% Duty Cycle

2 Programmable Operational ModesIndependent Mode/Offset Mode

Motor TypesPermanent Magnet Synchronous Motors (PMSM)Brushless DC Motors (BDCM)AC Induction Motors (ACIM)

APPLICATIONSRefrigerator and Air Conditioner CompressorsWashing MachinesIndustrial Variable Speed DrivesHVAC

ISENSE AMPAND TRIP

PROGRAMSEQUENCERDAG 2DAG 1

DATAADDRESS

GENERATORS

ADSP-21xx BASEARCHITECTURE

PROGRAM MEMORY ADDRESS

MEMORY BLOCK

PROGRAM FLASHOR ROM MEMORY

4k � 24-BIT

DATA MEMORY ADDRESS

DATA MEMORY DATA

ARITHMETIC UNITS

SHIFTERALU MACPOR TIMER

SERIAL PORT

SPORT 1

SPORT 0PIO

2 � 16-BITAUXPWM

WATCH-DOG

TIMER

ANALOGINPUTS

VREF2.5V

SHA

TIMERS

PROGRAM MEMORY DATA

16-BITTHREE-PHASEPWM

MULTIPLEXED ON EXTERNAL PINS

7

9 2

3

3

6

MOTOR CONTROL PERIPHERALS

ADC SUBSYSTEM

http://www.analog.com

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ADMC(F)341–SPECIFICATIONSANALOG-TO-DIGITAL CONVERTERParameter Min Typ Max Unit Conditions/Comments

Signal Input 0.3 3.5 V VAUX0, VAUX1, VAUX2Resolution1 12 BitsLinearity Error2 3 4 BitsZero Offset3 –32 0 +7 mVComparator Delay 600 nsADC High Level Input Current2 +10 µA VIN = 3.5 VADC Low Level Input Current2 –10 µA VIN = 0.0 VNOTES1Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.22.44 kHz sample frequency, VAUX0, VAUX1, VAUX2.3Extrapolated point outside of operating range. 2.44 kHz sample frequency.Specifications subject to change without notice.

ISENSE AMPLIFIER–TRIPParameter Min Typ Max Unit Conditions/Comments

ISENSE Signal Operating Range –400 +400 mVISENSE Signal Input Range –800 +800 mVISENSE Gain –2.6 –2.51 –2.34 % VIN = –400 mV to +400 mVISENSE Gain Channel Matching 5.5 % VIN = –400 mV to +400 mVISENSE Gain Stability1 0.8 % VIN = –400 mV to +400 mVISENSE Linearity2 8 9 BitsISENSE Internal Offset Voltage2 1.68 1.87 2.1 VISENSE Internal Offset Stability2 2.1 %ISENSE Signal-to-Noise Ratio (SNRD)3 51 dBISENSE Signal-to-Noise Ratio Less Distortion 54 dB(SNR)3

ISENSE Total Harmonic Distortion3 –53 dBISENSE Input Current –200 +10 µA VIN = –400 mV to +400 mVISENSE Input Resistance 11.5 kΩTRIP Threshold Low –690 –430 mVTRIP Threshold High +430 +690 mVTRIP Minimum Pulsewidth4 5 µsNOTES1Variation of gain with VDD and temperature.2VIN = –400 mV to +400 mV.3fIN = 1 kHz sine wave, VIN = –400 mV to +400 mV, fS = 4 kHz.4High or low trip threshold.Specifications subject to change without notice.

CURRENT SOURCE1Parameter Min Typ Max Unit Conditions/Comments

Programming Resolution 3 BitsTuned Current2 91 100 109 µANOTES1For ADC calibration.20.3 V to 3.5 V ICONST voltage.Specifications subject to change without notice.

(VDD = 5%, GND = 0 V. For ADMCF341, TA = –40�C to +85�C.For ADMC341, TA = –40�C to +125�C. CLKIN = 10 MHz, unless otherwise noted.)

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ADMC(F)341

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VOLTAGE REFERENCEParameter Min Typ Max Unit Conditions/Comments

Voltage Level (VREF) 2.44 2.50 2.55 V –40°C to +85°C (ADMCF341 only)2.44 2.50 2.55 V –40°C to +125°C (ADMC341 only)

Drift 110 ppm/°CSpecifications subject to change without notice.

POWER-ON RESETParameter Min Typ Max Unit Conditions/Comments

Reset Threshold 3.20 3.65 4.10 VHysteresis 100 mVReset Active Timeout Period 3.2* ms

*216 CLKOUT cycles.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICSSymbol Parameter Min Typ Max Unit Conditions/Comments

VIL Low Level Input Voltage 0.8 VVIH High Level Input Voltage 2 VVOL Low Level Output Voltage1 0.4 V IOL = 2 mAVOL Low Level Output Voltage2 0.8 V IOL = 2 mAVOH High Level Output Voltage 4 V IOH = 0.5 mAIIL Low Level Input Current RESET Pin3 –100 µA VIN = 0 VIIL Low Level Input Current –10 µA VIN = 0 VIIH High Level Input Current RESET Pin3 30 µA VIN = VDDIIH High Level Input Current4 100 µA VIN = VDDIIH High Level Input Current 10 µA VIN = VDDIOZH High Level Three-State Leakage Current5 100 µA VIN = VDDIOZL Low Level Three-State Leakage Current5 –10 µA VIN = 0 VIDD Supply Current (Idle)6 35 mA VDD = 5.25 V (ADMC341 only)IDD Supply Current (Dynamic)6 60 mA VDD = 5.25 V (ADMC341 only)IDD Supply Current (Idle)6 55 mA VDD = 5.25 V (ADMCF341 only)IDD Supply Current (Dynamic)6 135 mA VDD = 5.25 V (ADMCF341 only)

NOTES1Output pins PIO0-PIO8, AH, AL, BH, BL, CH, CL.2XTAL pin.3Internal pull-up, RESET.4Internal pull-down, PWMTRIP, PIO0-PIO8.5Three-stateable pins: DT1, RFS0, TFS0, SCLK1.6Outputs not switching.


REV. A–4–

ADMC(F)341

FLASH MEMORY (ADMCF341 ONLY)Parameter Min Typ Max Unit Conditions/Comments

Endurance 10,000 Cycles Cycle = Erase/Program/VerifyData Retention 15 YearsProgram and Erase Operating Temperature 0 85 °CRead Operating Temperature –40 +85 °CSpecifications subject to change without notice.

TIMING PARAMETERSParameter Min Max Unit

Clock SignalsSignal tCK is defined as 0.5 tCKIN. The ADMC(F)341 uses an input clock witha frequency equal to half the instruction rate; a 10 MHz input clock (which isequivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz).When tCK values are within the range of 0.5 tCKIN period, they should besubstituted for all relevant timing parameters to obtain specification value asin the following example:

t t ns ns ns nsCKH CK= − = × − =0 5 10 0 5 50 10 15. .

Timing Requirements:tCKIN CLKIN Period 100 150 nstCKIL CLKIN Width Low 20 nstCKIH CLKIN Width High 20 ns

Switching Characteristics:tCKL CLKOUT Width Low 0.5 tCK – 10 nstCKH CLKOUT Width High 0.5 tCK – 10 nstCKOH CLKIN High to CLKOUT High 0 20 ns

Control SignalsSwitching Characteristics:

tRSP RESET Width Low 5 tCK* ns

PWM Shutdown SignalsSwitching Characteristics:

tPWMTPW PWMTRIP Width Low tCK ns

*Applies after power-up sequence is complete.


CLKIN

CLKOUT

tCKL

tCKIL

tCKH

tCKIH

tCKIN

tCKOH

Figure 1. Clock Signals

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ADMC(F)341

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TIMING PARAMETERSParameter Min Max Unit

Serial PortsTiming Requirements:

tSCK SCLK Period 100 nstSCS DR/TFS/RFS Setup before SCLK Low 15 nstSCH DR/TFS/RFS Hold after SCLK Low 20 nstSCP SCLKIN Width 40 ns

Switching Characteristics:tCC CLKOUT High to SCLKOUT 0.25 tCK 0.25 tCK + 20 nstSCDE SCLK High to DT Enable 0 nstSCDV SCLK High to DT Valid 30 nstRH TFS/RFSOUT Hold after SCLK High 0 nstRD TFS/RFSOUT Delay from SCLK High 30 nstSCDH DT Hold after SCLK High 0 nstSCDD SCLK High to DT Disable 30 nstTDE TFS (Alt) to DT Enable 0 nstTDV TFS (Alt) to DT Valid 25 nstRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 30 ns


tCC tCC

tSCS

tRDtRH

tSCDV tSCDE

tSCDD

tTDV

tRDV

CLKOUT

SCLK

DRRFSINTFSIN

RFSOUTTFSOUT

DT

TFS(ALTERNATE

FRAME MODE)

RFS(MULTICHANNEL MODE,

FRAME DELAY 0 [MFD = 0])

tSCP

tSCK

tSCPtSCH

tSCDH

tTDE

Figure 2. Serial Port Timing

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ADMC(F)341

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Although theADMC(F)341 features proprietary ESD protection circuitry, permanent damage may occur on devicessubjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommendedto avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS*Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 VSupply Voltage (AVDD) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 VInput Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 VOutput Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD +0.3 VADMCF341 Operating Temperature

Range (Ambient) . . . . . . . . . . . . . . . . . . . . –40°C to +85°CADMC341 Operating Temperature Range . –40°C to +125°CStorage Temperature Range . . . . . . . . . . . . –65°C to +150°CLead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C*Stresses greater than those listed may cause permanent damage to the device.

These are stress ratings only; functional operation of the device at these or anyother conditions greater than those indicated in the operational sections of thisspecification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect device reliability.

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Pin Type

1 PORTA6/DR1 I/O2 PORTA5/(FL1/DT1) I/O3 PORTA4/(SCLK1/SCLK0) I/O4 PORTA3/TFS0 I/O5 PORTA2/RFS0 I/O6 PORTA1/DT0 I/O7 PORTA0/DR0 I/O8 CLKIN I9 XTAL O

10 VDD SUP11 PWMTRIP I12 ISENSE3 I13 ISENSE2 I14 ISENSE1 I15 VAUX0 I16 VAUX1 I17 VAUX2 I18 ICONST O19 GND GND20 RESET I21 CH O22 CL O23 BH O24 BL O25 AH O26 AL O27 PORTA8/(AUX0/CLKOUT) I/O28 PORTA7/(AUX1/PWMSYNC) I/O

ORDERING GUIDE

PackageModel Temperature Range Instruction Rate Package Description Option

ADMCF341BR –40°C to +85°C 20 MHz 28-Lead Wide Body (SOIC) RW-28ADMCF341-EVALKIT N/A N/A Development Tool KitADMC341 YR-xxx-xxxx –40°C to +125°C 20 MHz 28-Lead Wide Body (SOIC) RW-28

PIN CONFIGURATION

TOP VIEW(Not to Scale)

ADMC(F)341

PORTA6/DR1 PORTA7/(AUX1/PWMSYNC)

PORTA5/(FL1/DT1) PORTA8/(AUX0/CLKOUT)

PORTA4/(SCLK1/SCLK0) AL

PORTA3/TFS0

PORTA2/RFS0 BL

PORTA1/DT0 BH

PORTA0/DR0

CH

XTAL RESET

VDD

ICONST

ISENSE2

1

3

4

5

6

7

8

9

10

11

12

13

14

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AH

CLKIN

GND

PWMTRIP

VAUX2

VAUX1

ISENSE1 VAUX0

ISENSE3

CL

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ADMC(F)341

–7–

GENERAL DESCRIPTIONThe ADMC(F)341 is a low cost, single-chip, DSP-basedcontroller suitable for permanent magnet synchronous motors,ac induction motors, and brushless dc motors. The ADMC(F)341integrates a 20 MHz, fixed-point DSP core with a complete setof motor control and system peripherals that permits fast,efficient development of motor controllers.

The DSP core of the ADMC(F)341 is completely code compat-ible with the ADSP-21xx DSP family and combines threecomputational units, data address generators, and a programsequencer. The computational units are an ALU, a multiplier/accumulator (MAC), and a barrel shifter. There are specialinstructions for bit manipulation, multiplication (x squared),biased rounding, and global interrupt masking. The systemperipherals are the power-on reset circuit (POR), the watchdogtimer, and two synchronous serial ports. The serial ports areconfigurable and double buffered, with hardware support forUART, SCI, and SPI port emulation. The ADMC(F)341 pro-vides 512 � 24-bit program memory RAM, 4K � 24-bitprogram memory ROM, 4K � 24-bit program FLASH memory,and 512 � 16-bit data memory RAM. The user code can bestored and executed from the flash memory. The program anddata memory RAM can be used for dynamic data storage orcan be loaded through the serial port from an external deviceas in other ADMCxxx family parts. The program memoryROM contains a monitor function as well as useful routines forerasing, programming, and verifying the flash memory.

The motor control peripherals of the ADMC(F)341 provide a12-bit analog data acquisition system with six analog inputchannels with three dedicated ISENSE inputs (combining internalamplification, sampling, and overcurrent PWM shutdown

features) and an internal voltage reference. In addition, a three-phase, 16-bit, center-based PWM generation unit can be usedto produce high accuracy PWM signals with minimal processoroverhead. The ADMC(F)341 also contains two 16-bit auxiliaryPWM timer outputs and nine lines of digital I/O.

Because the ADMC(F)341 has a limited number of pins, func-tions such as the auxiliary PWM timers and the serialcommunication ports are multiplexed with the nine program-mable digital input/output (PIO) pins. The pin functions can beindependently selected to allow maximum flexibility for differ-ent applications.

DSP CORE ARCHITECTURE OVERVIEWFigure 3 is an overall block diagram of the DSP core of theADMC(F)341. The flexible architecture and comprehensiveinstruction set allow the processor to perform multiple opera-tions in parallel. In one processor cycle (50 ns with a 10 MHzCLKIN) the DSP core can:

• Generate the next program address• Fetch the next instruction• Perform one or two data moves• Update one or two data address pointers• Perform a computational operation

This all takes place while the processor continues to:

• Receive and transmit through the serial ports• Decrement the interval timer• Generate three-phase PWM waveforms for a power inverter• Generate two signals using the 16-bit auxiliary PWM timers• Acquire four analog signals• Decrement the watchdog timer

PM ROM4K � 24

PM RAM512 � 24

BUSEXCHANGE

COMPANDINGCIRCUITRY

DATAADDRESS

GENERATOR#2

DATAADDRESS

GENERATOR#1

14

14

24

16

6

DM RAM512 � 16

R BUS

16

DMA BUS

PMA BUS

DMD BUS

PMD BUS

INSTRUCTIONREGISTER

INPUT REGS

OUTPUT REGS

SHIFTER

CONTROLLOGIC

SERIALPORT

RECEIVE REG

TRANSMIT REG

TIMERINPUT REGS

OUTPUT REGS

MAC

INPUT REGS

OUTPUT REGS

ALU

PROGRAMSEQUENCER

FLASHPROGRAMMEMORY4K � 24

Figure 3. DSP Core Block Diagram

REV. A–8–

ADMC(F)341The processor contains three independent computational units:the arithmetic and logic unit (ALU), the multiplier/accumulator(MAC), and the shifter. The computational units process 16-bitdata directly and have provisions to support multiprecisioncomputations. The ALU performs a standard set of arithmeticand logic operations, and provides support for division primi-tives. The MAC performs single-cycle multiply, multiply/add, andmultiply/subtract operations with 40 bits of accumulation. Theshifter performs logical and arithmetic shifts, normalization,denormalization, and derive-exponent operations. The shiftercan be used to efficiently implement numeric format control,including floating-point representations. The internal result (R)bus directly connects the computational units so that the outputof any unit may be the input of any unit on the next cycle.

A powerful program sequencer and two dedicated data addressgenerators ensure efficient delivery of operands to these compu-tational units. The sequencer supports conditional jumps andsubroutine calls and returns in a single cycle. With internal loopcounters and loop stacks, the ADMC(F)341 executes looped codewith zero overhead; no explicit jump instructions are required tomaintain the loop.

Two data address generators (DAGs) provide addresses forsimultaneous dual operand fetches from data memory and pro-gram memory. Each DAG maintains and updates four addresspointers (I registers). Whenever the pointer is used to accessdata (indirect addressing), it is post-modified by the value inone of four modifications (M registers). A length value may beassociated with each pointer (L registers) to implement auto-matic modulo addressing for circular buffers. The circularbuffering feature is also used by the serial ports for automaticdata transfers to and from on-chip memory. DAG1 generatesonly data memory addresses and provides an optional bit-reversalcapability. DAG2 may generate either program or data memoryaddresses but has no bit-reversal capability. Efficient data trans-fer is achieved with the use of five internal buses:

• Program memory address (PMA) bus• Program memory data (PMD) bus• Data memory address (DMA) bus• Data memory data (DMD) bus• Result (R) bus

Program memory can store both instructions and data, permittingthe ADMC(F)341 to fetch two operands in a single cycle—onefrom program memory and one from data memory. TheADMC(F)341 can fetch an operand from on-chip programmemory and the next instruction in the same cycle. TheADMC(F)341 writes data from its 16-bit registers to the 24-bitprogram memory using the PX register to provide the lowereight bits. When it reads data (not instructions) from 24-bitprogram memory to a 16-bit data register, the lower eight bitsare placed in the PX register.

The ADMC(F)341 can respond to a number of distinct DSPcore and peripheral interrupts. The DSP interrupts comprise aserial port receive interrupt, a serial port transmit interrupt, atimer interrupt, and two software interrupts. Additionally, themotor control peripherals include two PWM interrupts and aPIO interrupt.

Serial port 0 (SPORT0) provides a complete synchronous serialinterface with optional companding in hardware and a wide

variety of framed and unframed data transmit and receivemodes of operation. Serial port 1 (SPORT1) is available with alimited number of I/Os. It is mainly intended for codebooting toserial ROMs (SROM) and supporting the debugging tools.SPORT0 and SPORT1 can generate an internal programmableserial clock or accept an external serial clock.

A programmable interval counter is also included in the DSPcore and can be used to generate periodic interrupts. A 16-bitcount register (TCOUNT) is decremented every n processorcycles, where n – 1 is a scaling value stored in the 8-bit TSCALEregister. When the value of the counter reaches zero, an inter-rupt is generated, and the count register is reloaded from a16-bit period register (TPERIOD).

The ADMC(F)341 instruction set provides flexible data movesand multifunction (one or two data moves with a computation)instructions. Each instruction is executed in a single 50 nsprocessor cycle (for a 10 MHz CLKIN). The ADMC(F)341assembly language uses an algebraic syntax for ease of codingand readability. A comprehensive set of development toolssupports program development. For further information on theDSP core, refer to the ADSP-2100 Family User’s Manual, ThirdEdition, with particular reference to the ADSP-2171.

SERIAL PORTSThe ADMCF341 incorporates two complete synchronous serialports (SPORT1 and SPORT0) for serial communication andmultiprocessor communication.

Following is a brief list of capabilities of the ADMC(F)341SPORTs. Refer to the ADSP-2100 Family User’s Manual, ThirdEdition, for further details.

• SPORTs are bidirectional and have a separate, double-buffered transmit and receive section.

• SPORTs use an external serial clock or generate their ownserial clock internally.

• SPORTs have independent framing for the receive andtransmit sections. Sections run in a frameless mode or withframe synchronization signals internally or externallygenerated. Frame synchronization signals are active high orinverted, with either of two pulsewidths and timings.

• SPORTs support serial data-word lengths from 3 bits to16 bits and provide optional A-law and µ-law compandingaccording to ITU (formerly CCITT) recommendationG.711.

• SPORT receive and transmit sections can generate uniqueinterrupts on completing a data-word transfer.

• SPORTs can receive and transmit an entire circular bufferof data with only one overhead cycle per data-word. Aninterrupt is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receiveand transmit a 24-word or 32-word time-division multi-plexed, serial bitstream.

• SPORT0 can be configured as an SPI port (master modeonly). The clock phase and polarity are programmablethrough the MODECTRL register.

• SPORT1 is the default port for program/data memory bootloading and for development tools interface. The DT1/FL1pin can be configured as SROM/E2PROM reset signal.

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PIN FUNCTION DESCRIPTIONThe ADMC(F)341 is available in a 28-lead SOIC package.Table I describes the pins.

Table I. Pin List

Pin Group No. of Input/Name Pins Output Function

RESET 1 I Processor Reset InputSPORT11 2 I/O Serial Port 1 Pins (DT1/FL1,

DR1, SCLK1/SCLK02)SPORT01 5 I/O Serial Port 0 Pins (DT0, DR0

TFSO, SCLK1/SCLK02)CLKOUT 11 I/O Processor Clock OutputCLKIN, XTAL 2 I, O External Clock or Quartz

Crystal Connection PointPORTA0– 9 I/O Digital I/O Port PinsPORTA81

AUX0–AUX11 2 O Auxiliary PWM OutputsAH–CL 6 O PWM OutputsPWMTRIP 1 I PWM Trip SignalISENSE1– 3 I ISENSE InputsISENSE3VAUX0–VAUX2 3 I Auxiliary Analog InputsICONST 1 O ADC Constant Current

SourceVDD 1 I Power SupplyGND 1 I Ground

NOTES1Multiplexed pins, individually selectable through PORTA_SELECTand PORTA_DATA registers.

2SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRLRegister Bit 4.

INTERRUPT OVERVIEWThe ADMC(F)341 can respond to 18 different interrupt sourceswith minimal overhead, seven of which are internal DSP coreinterrupts and 11 are from the motor control peripherals. Theseven DSP core interrupts are SPORT1 receive (or IRQ0) andtransmit (or IRQ1), SPORT0 receive and transmit, the internaltimer, and two software interrupts. The motor control peripheralinterrupts are the nine programmable I/Os and two from thePWM (PWMSYNC pulse and PWMTRIP). All motor controlinterrupts are multiplexed into the DSP core through theperipheral IRQ2 interrupt. The interrupts are internally prioritizedand individually maskable. A detailed description of the entireinterrupt system of the ADMC(F)341 is presented later, followinga more detailed description of each peripheral block.

MEMORY MAPThe ADMC(F)341 has two distinct memory types: programand data. In general, program memory contains user code andcoefficients, while the data memory is used to store variablesand data during program execution. Three kinds of programmemory are provided on the ADMC(F)341: RAM, ROM, andFLASH. The motor control peripherals are memory mappedinto a region of the data memory space starting at 0x2000. Thecomplete program and data memory maps are given in Tables IIand III, respectively.

Table II. Program Memory Map

MemoryAddress Range Type Function

0x0000–0x002F RAM Internal Vector Table0x0030–0x01FF RAM User Program Memory0x0200–0x07FF Reserved0x0800–0x17FF ROM Reserved Program Memory0x1800–0x1FFF Reserved0x2000–0x20FF FLASH User Program Memory

Sector 00x2100–0x21FF FLASH User Program Memory

Sector 10x2200–0x2FFF FLASH User Program Memory

Sector 20x3000–0x3FFF Reserved

Table III. Data Memory Map

MemoryAddress Range Type Function

0x0000–0x1FFF Reserved0x2000–0x20FF Memory Mapped Registers0x2100–0x37FF Reserved0x3800–0x39FF RAM User Data Memory0x3A00–0x3BFF RAM Reserved0x3C00–0x3FFF Memory Mapped Registers

FLASH MEMORY SUBSYSTEMThe ADMC(F)341 has 4K � 24-bits of user-programmable,nonvolatile flash memory. A flash programming utility is providedwith the development tools, which perform the basic deviceprogramming operations: erase, program, and verify.

The flash memory array is portioned into three asymmetricallysized sectors of 256 words, 256 words, and 3584 words, labeledsector 0, sector 1, and sector 2, respectively. These sectors aremapped into external program memory address space.

Four flash memory interface registers are connected to the DSP.These 16-bit registers are mapped into the register area of datamemory space. They are named flash memory control register(FMCR), flash memory address register (FMAR), flash memorydata register low (FMDRL), and flash memory data registerhigh (FMDRH). These registers are diagrammed in Figure 22.They are used by the flash memory programming utility. Theuser program may read these registers, but should not modifythem directly. The flash programming utility provides a completeinterface to the flash memory.

It should be noted that the core accesses flash memory throughan external memory interface that multiplexes the programmemory and data memory buses into a single external bus.Therefore, if more than one external transfer must be made in thesame instruction, there will be at least one overhead cycle required.

REV. A–10–

ADMC(F)341Special Flash RegistersThe flash module has four nonvolatile 8-bit registers calledspecial flash registers (SFRs) that are accessible independent ofthe main flash array via the flash programming utility. Theseregisters are for general-purpose, nonvolatile storage. Whenerased, the special flash registers contain all 0s. To read specialflash registers from the user program, call the read_reg routinecontained in ROM. Refer to the ADMCF34x DSP MotorController Developers Reference Manual for an example.

Boot-from-Flash CodeA security feature is available in the form of a code that,when set, causes the processor to execute the program inflash memory at power-up or reset. In this mode, the flashprogramming utility and debugger are unable to communicatewith the ADMC(F)341. Consequently, the contents of theflash memory can be neither programmed nor read.

The boot-from-flash code may be set via the flash programmingutility, when the user’s program is thoroughly tested and loaded intoflash program memory at address 0x2200. The user’s program mustcontain a mechanism for clearing the boot-from-flash code if repro-gramming the flash memory is desired. The only way to clearboot-from-flash is from within the user program, by calling theflash_init or auto_erase_reg routines that are included in the ROM.The user program must be signaled in some way to call thenecessary routine to clear the boot-from-flash code. An examplewould be to detect a high level on a PIO pin during startupinitialization and then call the flash_init or auto_erase_reg routine.The flash_init routine will erase the entire user program in flashmemory before clearing the boot-from-flash code, thus ensuringthe security of the user program. If security is not a concern, theauto_erase_reg routine can be used to clear the boot-from-flashcode while leaving the user program intact.

Refer to the ADMCF34x DSP Motor Controller Developer’sReference Manual for further instructions and an example ofusing the boot-from-flash code.

FLASH PROGRAM BOOT SEQUENCEOn power-up or reset, the processor begins instruction execu-tion at address 0x0800 of internal program ROM. The ROMmonitor program that is located there checks the boot-from-flashcode. If that code is set, the processor jumps to location 0x2200in external flash program memory, where it expects to find theuser’s application program.

If the boot-from-flash code is not set, the monitor attempts toboot from an external device as described in the ADMCF34xDSP Motor Controller Developers Reference Manual.

SYSTEM INTERFACEFigure 4 shows a basic system configuration for the ADMC(F)341with an external crystal.

ADMC(F)341

XTAL

CLKIN

10MHz

CLKOUT

RESET

22pF

22pF

Figure 4. Basic System Configuration

Clock SignalsThe ADMC(F)341 can be clocked either by a crystal or a TTLcompatible clock signal. For normal operation, the CLKIN inputcannot be halted, changed during operation, or operated below thespecified minimum frequency. If an external clock is used, it shouldbe a TTL compatible signal running at half the instruction rate.The signal is connected to the CLKIN pin of the ADMC(F)341.In this mode, with an external clock signal, the XTAL pin must beleft unconnected. The ADMC(F)341 uses an input clock with afrequency equal to half the instruction rate; a 10 MHz input clockyields a 50 ns processor cycle (which is equivalent to 20 MHz).Normally, instructions are executed in a single processor cycle. Alldevice timing is relative to the internal instruction rate, which isindicated by the CLKOUT signal when enabled.

Because the ADMC(F)341 includes an on-chip oscillator feedbackcircuit, an external crystal may be used instead of a clock source,as shown in Figure 4. The crystal should be connected across theCLKIN and XTAL pins with two capacitors, as shown inFigure 4. A parallel-resonant, fundamental frequency, micropro-cessor grade crystal should be used. A clock output signal(CLKOUT) is generated by the processor at the processor’s cyclerate of twice the input frequency.

ResetThe ADMC(F)341 DSP core and peripherals must be correctlyreset when the device is powered up to ensure proper unitization.The ADMC(F)341 contains an integrated power-on-reset (POR)circuit that provides a complete system reset on power-up andpower-down. The POR circuit monitors the voltage on theADMC(F)341 VDD pin and holds the DSP core and peripheralsin reset while VDD is less than the threshold voltage level, VRST.When this voltage is exceeded, the ADMC(F)341 is held in resetfor an additional 216 DSP clock cycles (TRST in Figure 5). Duringthis time (TRST), the supply voltage must reach the recommendedoperating condition. On power-down, when the voltage on theVDD pin falls below VRST –VHYST, the ADMC(F)341 will bereset. Also, if the external RESET pin is actively pulled low atany time after power-up, a complete hardware reset of theADMC(F)341 is initiated.

VRST

VDD

RESET

VRST – VHYST

TRST

Figure 5. Power-On Reset Operation

The ADMC(F)341 sets all internal stack pointers to the emptystack condition, masks all interrupts, clears the MSTAT register,and performs a full reset of all of the motor control peripherals.Following a power-up, it is possible to initiate a DSP core andmotor control peripheral reset by pulling the RESET pin low.The RESET signal must be the minimum pulsewidth specification,tRSP. Following the reset sequence, the DSP core starts executingcode from the internal PM ROM located at 0x0800.

REV. A

ADMC(F)341

–11–

PWMTRIPOR

PWMSWT (0)OVER-

CURRENTTRIPPWM SHUTDOWN CONTROLLER

ANALOG BLOCK

PWMTRIP

ISENSE2

ISENSE1

ISENSE3

PWMSEG (8...0)

OUTPUTCONTROL

UNIT

GATEDRIVEUNIT

CLK

PWM DUTY CYCLEREGISTERS

PWM CONFIGURATIONREGISTERS

TO INTERRUPTCONTROLLER

THREE-PHASEPWM TIMING

UNIT

CLK RESETSYNC SYNC

PWMSYNC

CLKOUT

AHALBH

BLCHCL

PWMGATE (9...0)

PWMTM (15...0)PWMDT (9...0)PWMPD (9...0)PWMSYNCWT (7...0)MODECTRL (6)

PWMCHA (15...0)PWMCHB (15...0)PWMCHC (15...0)

Figure 6. Overview of the PWM Controller of the ADMC(F)341

DSP Control RegistersThe DSP core has a system control register, SYSCNTL,memory-mapped at DM (0x3FFF). SPORT1 must be configuredas a serial port by setting Bit 10. SPORT0 and SPORT1 areenabled by setting Bit 11 and Bit 12.

The DSP core has a wait state control register, MEMWAIT,memory-mapped at DM (0x3FFE). The default value of thisregister is 0xFFFF. For proper operation of the ADMC(F)341,this register must always contain the value 0x8000. This valuesets the minimum access time to the program memory.

The configurations of both the SYSCNTL and MEMWAITregisters of the ADMC(F)341 are shown in Figure 31.

THREE-PHASE PWM CONTROLLEROverviewThe PWM generator block of the ADMC(F)341 is a flexible,programmable three-phase PWM waveform generator that canbe programmed to generate the required switching patterns todrive a three-phase voltage source inverter for ac inductionmotors (ACIM) or permanent magnet synchronous motors(PMSM). In addition, the PWM block contains special functionsthat considerably simplify the generation of the required PWMswitching patterns for control of brushless dc motors (BDCM),including electronically commutated motors (ECM).

The six PWM output signals consist of three high side drivesignals (AH, BH, and CH) and three low side drive signals(AL, BL, and CL). The switching frequency, dead time, andminimum pulsewidths of the generated PWM patterns areprogrammable using, respectively, the PWMTM, PWMDT, andPWMPD registers. In addition, three registers (PWMCHA,

PWMCHB, and PWMCHC) control the duty cycles of thethree pairs of PWM signals.

Each of the six PWM output signals can be enabled or disabledby separate output enable bits of the PWMSEG register. Inaddition, three control bits of the PWMSEG register permitcrossover of the two signals of a PWM pair for easy control ofECM or BDCM. In crossover mode, the high side PWM signalsare diverted to the complementary low side output and the lowside signals are diverted to the corresponding high side outputs.

In many applications, there is a need to provide an isolationbarrier in the gate-drive circuits that turn on the power devicesof the inverter. In general, there are two common isolationtechniques: optical isolation using optocouplers, and trans-former isolation using pulse transformers. The PWM controllerof the ADMC(F)341 permits mixing of the output PWM signalswith a high frequency chopping signal to permit an easy interfaceto such pulse transformers. The features of this gate-drivechopping mode can be controlled by the PWMGATE register.There is an 8-bit value within the PWMGATE register thatdirectly controls the chopping frequency. In addition, highfrequency chopping can be independently enabled for the highside and the low side outputs using separate control bits in thePWMGATE register.

The PWM generator is capable of operating in two distinct modes:single update mode and double update mode. In single updatemode, the duty cycle values are programmable only once perPWM period so that the resultant PWM patterns are symmetricalabout the midpoint of the PWM period. In double update mode,a second updating of the PWM duty cycle values is implementedat the midpoint of the PWM period. In this mode, it is possible

REV. A–12–

ADMC(F)341to produce asymmetrical PWM patterns that produce lowerharmonic distortion in three-phase PWM inverters. This techniquealso permits the closed-loop controller to change the averagevoltage applied to the machine winding at a faster rate, allowingwider closed-loop bandwidths to be achieved. The operating modeof the PWM block (single or double update mode) is selected bya control bit in MODECTRL register.

The PWM generator of the ADMC(F)341 also provides aninternal signal that synchronizes the PWM switching frequencyto the A/D operation. In single update mode, a PWMSYNCpulse is produced at the start of each PWM period. In doubleupdate mode, an additional PWMSYNC pulse is produced atthe midpoint of each PWM period. The width of the PWMSYNCpulse is programmable through the PWMSYNCWT register.

The PWM signals produced by the ADMC(F)341 can be shutoff in a number of different ways. First, there is a dedicatedasynchronous PWM shutdown pin, PWMTRIP, that, whenbrought LOW, instantaneously places all six PWM outputs inthe OFF state. In addition, PWM shutdown is initiated whenthe voltage on any of the input pins (ISENSE) exceeds the tripthresholds (high or low) or the input is unconnected (floating).Because these two hardware shutdown mechanisms are asyn-chronous, and the associated PWM disable circuitry does notuse clocked logic, the PWM will shut down even if the DSPclock is not running. The PWM system may also be shut downfrom software by writing to the PWMSWT register.

Status information about the PWM system of the ADMC(F)341is available to the user in the SYSSTAT register. In particular,the state of PWMTRIP is available, as well as a status bit thatindicates whether the operation is in the first half or the secondhalf of the PWM period.

A functional block diagram of the PWM controller is shown inFigure 6. The generation of the six output PWM signals on pinsAH to CL is controlled by four important blocks:

• The three-phase PWM timing unit, which is the core of thePWM controller, generates three pairs of complementedand dead-time-adjusted center-based PWM signals.

• The output control unit allows the redirection of the outputsof the three-phase timing unit for each channel to either thehigh side or the low side output. In addition, the outputcontrol unit allows individual enabling/disabling of each ofthe six PWM output signals.

• The GATE drive unit provides the high chopping frequencyand its subsequent mixing with the PWM signals.

• The PWM shutdown controller manages the three PWMshutdown modes (via the PWMTRIP pin, the analog block,or the PWMSWT register) and generates the correctRESET signal for the timing unit.

The PWM controller is driven by a clock at the same frequencyas the DSP instruction rate, CLKOUT, and is capable of gener-ating two interrupts to the DSP core. One interrupt is generatedon the occurrence of a PWMSYNC pulse, and the other isgenerated on the occurrence of any PWM shutdown action.

Three-Phase Timing UnitThe 16-bit three-phase timing unit is the core of the PWMcontroller and produces three pairs of pulsewidth modulatedsignals with high resolution and minimal processor overhead.There are four main configuration registers (PWMTM,

PWMDT, PWMPD, and PWMSYNCWT) that determine thefundamental characteristics of the PWM outputs. In addition,the operating mode of the PWM (single or double updatemode) is selected by Bit 6 of the MODECTRL register. Theseregisters, in conjunction with the three 16-bit duty cycle reg-isters (PWMCHA, PWMCHB, and PWMCHC), control theoutput of the three-phase timing unit.

PWM Switching Frequency: PWMTM RegisterThe PWM switching frequency is controlled by the PWMperiod register, PWMTM. The fundamental timing unit ofthe PWM controller is tCK = 1/fCLKOUT, where fCLKOUT is theCLKOUT frequency (DSP instruction rate). Therefore, for a20 MHz CLKOUT, the fundamental time increment is 50 ns.The value written to the PWMTM register is effectively thenumber of tCK clock increments in half a PWM period. Therequired PWMTM value is a function of the desired PWMswitching frequency (fPWM) and is given by:

PWMTM

ff

ff

CLKOUT

PWM

CLKINT

PWM=

×=

2

Therefore, the PWM switching period, TS, can be written as:

T PWMTM tS CK= × ×2

For example, for a 20 MHz CLKOUT and a desired PWMswitching frequency of 10 kHz (TS = 100 µs), the correct valueto load into the PWMTM register is:

PWMTM x E= ×

× ×= =20 10

2 10 101000 0 3 8

6

3

The largest value that can be written to the 16-bit PWMTMregister is 0xFFFF = 65,535, which corresponds to a minimumPWM switching frequency of:

f HzPWM ,min ,

= ××

=20 102 65 535

1536

for a CLKOUT frequency of 20 MHz.

PWM Switching Dead Time: PWMDT RegisterThe second important PWM block parameter that must beinitialized is the switching dead time. This is a short delay timeintroduced between turning off one PWM signal (e.g., AH) andturning on its complementary signal (e.g., AL). This short timedelay is introduced to permit the power switch being turned offto completely recover its blocking capability before the comple-mentary switch is turned on. This time delay prevents a potentiallydestructive short-circuit condition from developing across thedc link capacitor of a typical voltage source inverter.

Dead time is controlled by the PWMDT register. The dead timeis inserted into the three pairs of PWM output signals. The deadtime, TD, is related to the value in the PWMDT register by:

T PWMDT t

PWMDTfD CK CLKOUT

= × × = ×2 2

Therefore, a PWMDT value of 0x00A (= 10) introduces a1 µs delay between the turn-off of any PWM signal (e.g., AH)and the turn-on of its complementary signal (e.g., AL). Theamount of the dead time can therefore be programmed in incre-ments of 2 tCK (or 100 ns for a 20 MHz CLKOUT).

REV. A

ADMC(F)341

–13–

The PWMDT register is a 10-bit register. For a CLKOUTrate of 20 MHz its maximum value of 0x3FF (= 1023) corre-sponds to a maximum programmed dead time of:

T t

s

D CKmax = × ×

= × × ×= µ

−

1023 2

1023 2 50 10

102

9sec

The dead time can be programmed to zero by writing 0 to thePWMDT register.

PWM Operating Mode: MODECTRL andSYSSTAT RegistersThe PWM controller of the ADMC(F)341 can operate in twodistinct modes: single update mode and double update mode.The operating mode of the PWM controller is determined bythe state of Bit 6 of the MODECTRL register. If this bit iscleared, the PWM operates in the single update mode. SettingBit 6 places the PWM in the double update mode. By default,following either a peripheral reset or power-on, Bit 6 of theMODECTRL register is cleared. This means that the defaultoperating mode is single update mode.

In single update mode, a single PWMSYNC pulse is producedin each PWM period. The rising edge of this signal marks thestart of a new PWM cycle and is used to latch new values fromthe PWM configuration registers (PWMTM, PWMDT, PWMPD,and PWMSYNCWT) and the PWM duty cycle registers(PWMCHA, PWMCHB, and PWMCHC) into the three-phasetiming unit. The PWMSEG register is also latched into theoutput control unit on the rising edge of the PWMSYNC pulse.In effect, this means that the parameters of the PWM signalscan be updated only once per PWM period at the start of eachcycle. Thus, the generated PWM patterns are symmetrical,centered around the midpoint of the switching period.

In double update mode, there is an additional PWMSYNCpulse produced at the midpoint of each PWM period. Therising edge of this new PWMSYNC pulse is again used to latchnew values of the PWM configuration registers, duty cycleregisters, and the PWMSEG register. As a result, it is possibleto alter both the characteristics (switching frequency, dead time,minimum pulsewidth, and PWMSYNC pulsewidth) and theoutput duty cycles at the midpoint of each PWM cycle. Conse-quently, it is possible to produce PWM switching patterns thatare no longer symmetrical, centered around the midpoint of theperiod (asymmetrical PWM patterns).

In double update mode, operation in the first half or the secondhalf of the PWM cycle is indicated by Bit 3 of the SYSSTATregister. In double update mode, this bit is cleared duringoperation in the first half of each PWM period (between therising edge of the original PWMSYNC pulse and the rising edgeof the new PWMSYNC pulse, which is introduced in doubleupdate mode). Bit 3 of the SYSSTAT register is set during thesecond half of each PWM period. If required, a user maydetermine the status of this bit during a PWMSYNC interruptservice routine.

The advantages of double update mode are that lower harmonicvoltages can be produced by the PWM process and widercontrol bandwidths are possible. However, for a given PWMswitching frequency, the PWMSYNC pulses occur at twice therate in the double update mode. Because new duty cycle valuesmust be computed in each PWMSYNC interrupt service rou-tine, there is a larger computational burden on the DSP indouble update mode.

Width of the PWMSYNC Pulse: PWMSYNCWT RegisterThe PWM controller of the ADMC(F)341 produces an internalPWM synchronization pulse at a rate equal to the PWM switchingfrequency in single update mode and at twice the PWM fre-quency in double update mode. This PWMSYNC synchronizesthe operation of the PWM unit with the A/D converter system.The width of this PWMSYNC pulse is programmable by thePWMSYNCWT register. The width of the PWMSYNC pulse,TPWMSYNC, is given by:

T t PWMSYNCWTPWMSYNC CK= × +( )1

which means that the width of the pulse is programmable fromtCK to 256 tCK (corresponding to 50 ns to 12.8 µs for a CLKOUTrate of 20 MHz). Following a reset, the PWMSYNCWTregister contains 0x27 (= 39) so that the default PWMSYNCwidth is 2.0 µs.PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHCRegistersThe duty cycles of the six PWM output signals are controlledby the three duty cycle registers, PWMCHA, PWMCHB, andPWMCHC. The integer value in the register PWMCHA con-trols the duty cycle of the signals on AH and AL. PWMCHBcontrols the duty cycle of the signals on BH and BL, andPWMCHC controls the duty cycle of the signals on CH andCL. The duty cycle registers are programmed in integer countsof the fundamental time unit, tCK, and define the desired on-timeof the high side PWM signal produced by the three-phase timingunit over half the PWM period. The switching signals producedby the three-phase timing unit are also adjusted to incorporatethe programmed dead time value in the PWMDT register.

The PWM is center-based. This means that in single updatemode, the resulting output waveforms are symmetrical andcentered in the PWMSYNC period. Figure 7 presents a typicalPWM timing diagram illustrating the PWM-related registers’(PWMCHA, PWMTM, PWMDT, and PWMSYNCWT) con-trol over the waveform timing in both half cycles of the PWMperiod. The magnitude of each parameter in the timing diagramis determined by multiplying the integer value in each registerby tCK (typically 50 ns). It may be seen in the timing diagramhow dead time is incorporated into the waveforms by movingthe switching edges away from the original values set in thePWMCHA register.

REV. A–14–

ADMC(F)341

PWMSYNC

AH

AL

PWMCHA PWMCHA

2 � PWMDT

PWMSYNCWT + 1

2 � PWMDT

SYSSTAT (3)

PWMTM PWMTM

Figure 7. Typical PWM Outputs of Three-PhaseTiming Unit in Single Update Mode

Each switching edge is moved by an equal amount (PWMDT �tCK) to preserve the symmetrical output patterns. ThePWMSYNC pulse, whose width is set by the PWMSYNCWTregister, is also shown. Bit 3 of the SYSSTAT register indicateswhich half cycle is active. This can be useful in double updatemode, as will be discussed later.

The resultant on-times of the PWM signals shown in Figure 7may be written as:

T PWMCHA PWMDT tAH CK= × − ×2 ( )

T PWMTM PWMCHA PWMDT tAL CK= × − − ×2 ( )

The corresponding duty cycles are:

dTT

PWMCHA PWMDTPWMTMAH

AH

S

= = −

d

TT

PWMTM PWMCHA PWMDTPWMTMAL

AL

S

= = − −

Obviously, negative values of TAH and TAL are not permittedbecause the minimum permissible value is zero, correspondingto a 0% duty cycle. In a similar fashion, the maximum value isTS, corresponding to a 100% duty cycle.

The output signals from the timing unit for operation in doubleupdate mode are shown in Figure 8. This illustrates a completelygeneral case where the switching frequency, dead time, and dutycycle are all changed in the second half of the PWM period. Ofcourse, the same value for any or all of these quantities could beused in both halves of the PWM cycle. However, it can be seenthat there is no guarantee that symmetrical PWM signals will beproduced by the timing unit in this double update mode.Additionally, it is seen that the dead time is inserted into the PWMsignals in the same way as in single update mode.

PWMCHA2

2 � PWMDT1 2 � PWMDT2

PWMSYNCWT2 + 1

PWMCHA1

PWMTM1 PWMTM2

PWMSYNCWT1 + 1

AH

AL

PWMSYNC

SYSSTAT (3)

Figure 8. Typical PWM Outputs of Three-PhaseTiming Unit in Double Update Mode

In general, the on-times of the PWM signals in double updatemode are defined by:

T

PWMCHA PWMCHA

PWMDT PWMDT T

AH

CK

=+ −

− ×(

)1 2

1 2

T

PWMTM PWMTM PWMCHA

PWMCHA PWMDT PWMDT t

AL

CK

=+ − −− − ×

(

)1 2 1

2 1 2

dTT

PWMCHA PWMCHAPWMTM PWMTM

PWMDT PWMDTPWMTM PWMTM

AHAH

S

= =

++

−++

1 2

1 2

1 2

1 2

dTT

PWMTM PWMTM PWMCHAPWMTM PWMTM

PWMCHA PWMDT PWMCHAPWMTM PWMTM

ALAL

S

= =+ +

+−

+ ++

1 2 1

1 2

2 1 1

1 2

because for the completely general case in double update mode,the switching period is given by:

T PWMTM PWMTM tS CK= + ×( )1 2Again, the values of TAH and TAL are constrained to lie betweenzero and TS.

PWM signals similar to those illustrated in Figure 7 and Figure 8can be produced on the BH, BL, CH, and CL outputs byprogramming the PWMCHB and PWMCHC registers in amanner identical to that described for PWMCHA.

The PWM controller does not produce any PWM outputs untilall of the PWMTM, PWMCHA, PWMCHB, and PWMCHCregisters have been written to at least once. After these registershave been written, the counters in the three-phase timing unitare enabled. Writing to these registers also starts the main PWMtimer. If, during initialization, the PWMTM register is writtenbefore the PWMCHA, PWMCHB, and PWMCHC registers,the first PWMSYNC pulse (and interrupt if enabled) will begenerated (1.5 × tCK × PWMTM) seconds after the initial writeto the PWMTM register in single update mode. In double updatemode, the first PWMSYNC pulse will be generated (tCK ×PWMTM) seconds after the initial write to the PWMTM registerin single update mode.

REV. A

ADMC(F)341

–15–

will remain OFF (0% duty cycle). Additionally, the AL signalwill be turned ON for the entire half period (100% duty cycle).

Output Control Unit: PWMSEG RegisterThe operation of the output control unit is managed by the 9-bitread/write PWMSEG register. This register sets two distinctfeatures of the output control unit that are directly useful in thecontrol of ECM or BDCM.

The PWMSEG register contains three crossover bits, one foreach pair of PWM outputs. Setting Bit 8 of the PWMSEGregister enables the crossover mode for the AH/AL pair ofPWM signals; setting Bit 7 enables crossover on the BH/BL pairof PWM signals; and setting Bit 6 enables crossover on theCH/CL pair of PWM signals. If crossover mode is enabled forany pair of PWM signals, the high side PWM signal from thetiming unit (for example, AH) is diverted to the associated lowside output of the output control unit so that the signal willultimately appear at the AL pin. Of course, the correspondinglow side output of the timing unit is also diverted to the comple-mentary high side output of the output control unit so that thesignal appears at pin AH. Following a reset, the three crossoverbits are cleared so that the crossover mode is disabled on allthree pairs of PWM signals.

The PWMSEG register also contains six bits (Bits 0 to 5) thatcan be used individually to enable or disable each of the sixPWM outputs. If the associated bit of the PWMSEG register isset, the corresponding PWM output is disabled regardless of thevalue of the corresponding duty cycle register. This PWM outputsignal will remain in the OFF state as long as the correspondingenable/disable bit of the PWMSEG register is set. The PWMoutput enable function gates the crossover function. After areset, all six enable bits of the PWMSEG register are cleared,thereby enabling all PWM outputs by default.

In a manner identical to the duty cycle registers, the PWMSEGis latched on the rising edge of the PWMSYNC signal so thatchanges to this register only become effective at the start of eachPWM cycle in single update mode. In double update mode, thePWMSEG register can also be updated at the midpoint of thePWM cycle.

In the control of an ECM, only two inverter legs are switched atany time, and often the high side device in one leg must beswitched on at the same time as the low side driver in a secondleg. Therefore, by programming identical duty cycles for twoPWM channels (for example, let PWMCHA = PWMCHB) andsetting Bit 7 of the PWMSEG register to cross over the BH/BLpair of PWM signals, it is possible to turn ON the high sideswitch of phase A and the low side switch of phase B at thesame time. In the control of an ECM, one inverter leg (phase Cin this example) is disabled for a number of PWM cycles. Thisdisable may be implemented by disabling both the CH and CLPWM outputs by setting Bits 0 and 1 of the PWMSEG register.This is illustrated in Figure 7, where it can be seen that both theAH and BL signals are identical, because PWMCHA = PWMCHB, and the crossover bit for phase B is set. In addition, theother four signals (AL, BH, CH, and CL) have been disabled bysetting the appropriate enable/disable bits of the PWMSEGregister. For the situation illustrated in Figure 9, the appropriatevalue for the PWMSEG register is 0x00A7. In ECM operation,because each inverter leg is disabled for a certain period of time,the PWMSEG register is changed based upon the position ofthe rotor shaft (motor commutation).

Effective PWM ResolutionIn single update mode, the same values of PWMCHA,PWMCHB, and PWMCHC are used to define the on-times inboth half cycles of the PWM period. As a result, the effectiveresolution of the PWM generation process is 2 tCK (or 100 ns for a20 MHz CLKOUT), since incrementing one of the duty cycleregisters by 1 changes the resultant on-time of the associated PWMsignals by tCK in each half period (or 2 tCK for the full period).

In double update mode, improved resolution is possible sincedifferent values of the duty cycle registers are used to define theon-times in both the first and second halves of the PWM period.As a result, it is possible to adjust the on-time over the wholeperiod in increments of tCK. This corresponds to an effectivePWM resolution of tCK in double update mode (or 50 ns for a20 MHz CLKOUT).

Table IV. Achievable PWM Resolution in Single and DoubleUpdate Modes

Resolution Single Update Mode Double Update Mode(Bit) (kHz) PWM Frequency (kHz) PWM Frequency

8 39.1 78.49 19.5 39.110 9.8 19.511 4.9 9.812 2.4 4.9

Minimum Pulsewidth: PWMPD RegisterIn many power converter switching applications, it is desirableto eliminate PWM switching pulses shorter than a certain width.It takes a finite time to both turn on and turn off modern powersemiconductor devices. Therefore, if the width of any of thePWM pulses is shorter than some minimum value, it may bedesirable to completely eliminate the PWM switching for thatparticular cycle.

The allowable minimum on-time for any of the six PWM outputsfor half a PWM period that can be produced by the PWMcontroller may be programmed using the PWMPD register. Theminimum on-time is programmed in increments of tCK so that theminimum on-time produced for any half PWM period, TMIN,is related to the value in the PWMPD register by:

T PWMPD tMIN CK= ×

A PWMPD value of 0x002 defines a permissible minimumon-time of 100 ns for a 20 MHz CLKOUT.

In each half cycle of the PWM, the timing unit checks the on-timeof each of the six PWM signals. If any of the times is found tobe less than the value specified by the PWMPD register, thecorresponding PWM signal is turned OFF for the entire halfperiod, and its complementary signal is turned completely ON.

Consider the example where PWMTM = 200, PWMCHA = 5,PWMDT = 3, and PWMPD = 10 with a CLKOUT of 20 MHz,while operating in single update mode. For this case, thePWM switching frequency is 50 kHz and the dead time is300 ns. The minimum permissible on-time of any PWM signalover one-half of any period is 500 ns. Clearly, for this example,the dead-time adjusted on-time of the AH signal for one-half aPWM period is (5–3) × 50 ns = 100 ns. Because this is less thanthe minimum permissible value, output AH of the timing unit

REV. A–16–

ADMC(F)341PWMCHA = PWMCHB

PWMTM PWMTM

AH

AL

BH

BL

2 � PWMDT2 � PWMDT

CH

CL

Figure 9. An Example of PWM Signals Suitable forECM Control. PWMCHA = PWMCHB, BH/BL are aCrossover Pair. AL, BH, CH, and CL Outputs areDisabled. Operation is in Single Update Mode.

Gate Drive Unit: PWMGATE RegisterThe gate drive unit of the PWM controller adds features thatsimplify the design of isolated gate drive circuits for PWMinverters. If a transformer-coupled power device gate driveamplifier is used, the active PWM signal must be chopped at ahigh frequency. The PWMGATE register allows the programmingof this high frequency chopping mode. The chopped activePWM signals may be required for the high side drivers only, forthe low side drivers only, or for both the high side and low sideswitches. Therefore, independent control of this mode for bothhigh side and low side switches is included with two separatecontrol bits in the PWMGATE register.

Typical PWM output signals with high frequency choppingenabled on both high side and low side signals are shown inFigure 10. Chopping of the high side PWM outputs (AH, BHand CH) is enabled by setting Bit 8 of the PWMGATE register.Chopping of the low side PWM outputs (AL, BL, and CL) isenabled by setting Bit 9 of the PWMGATE register. The highchopping frequency is controlled by the 8-bit word (GDCLK)written to Bits 0 to 7 of the PWMGATE register. The periodand the frequency of this high frequency carrier are:

T GDCLK tCHOP CK= × ( ) +[ ] ×4 1

ff

GDCLKCHOP

CLKOUT=× +( )[ ]4 1

The GDCLK value may range from 0 to 255, corresponding toa programmable chopping frequency rate from 19.5 kHz to 5 MHzfor a 20 MHz CLKOUT rate. The gate drive features must beprogrammed before operation of the PWM controller and typicallyare not changed during normal operation of the PWM control-ler. Following a reset, by default, all bits of the PWMGATEregister are cleared so that high frequency chopping is disabled.

PWMTM PWMTM

[4 � (GDCLK+1)]

2 � PWMDT 2 � PWMDT

PWMCHA PWMCHA

AH

AL

Figure 10. Typical PWM Signals With HighFrequency Gate Chopping Enabled on BothHigh Side and Low Side Switches. (GDCLK isthe Integer Equivalent of the Value in Bits 0to 7 of the PWMGATE Register.)

PWM ShutdownIn the event of external fault conditions, it is essential that thePWM system be instantaneously shut down. Two methods ofsensing a fault condition are provided by the ADMC(F)341.For the first method, a low level on the PWMTRIP pin initiatesan instantaneous, asynchronous (independent of DSP clock)shutdown of the PWM controller. This places all six PWMoutputs in the OFF state, disables the PWMSYNC pulse andassociated interrupt signal, and generates a PWMTRIP inter-rupt signal. The PWMTRIP pin has an internal pull-downresistor so that even if the pin becomes disconnected, the PWMoutputs will be disabled. The state of the PWMTRIP pin can beread from Bit 0 of the SYSSTAT register.

The second method for detecting a fault condition is throughthe ISENSE pins of the analog block of the ADMC(F)341. Whenthe voltage at any of the ISENSE pins exceeds the trip threshold(high or low), or the ISENSE pin is in high impedance (floating),PWMTRIP will be internally pulled low. The negative edge ofthe internal PWMTRIP will generate a shutdown in the samemanner as a negative edge on pin PWMTRIP.

It is possible through software to initiate a PWM shutdown bywriting to the 1-bit read/write PWMSWT register (0x2061).Writing to this bit generates a PWM shutdown in a manneridentical to the PWMTRIP or ISENSE pins. Following a PWMshutdown, it is possible to determine if the shutdown was gener-ated from hardware or software by reading the same PWMSWTregister. Reading this register also clears it.

Restarting the PWM after a fault condition is detected requiresclearing the fault and reinitializing the PWM. Clearing the faultrequires PWMTRIP to return to a high state and ISENSE to re-turn to a voltage in the ISENSE trip level range. After the fault hasbeen cleared, the PWM can be restarted by writing to registersPWMTM, PWMCHA, PWMCHB, and PWMCHC. After thefault is cleared and the PWM registers are initialized, internaltiming of the three-phase timing unit will resume, and the newduty cycle values will be latched on the next rising edge ofPWMSYNC.

PWM RegistersThe configuration of the PWM registers is described in Figures23, 24, and 27. The parameters of the PWM block are tabu-lated in Table V.

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ADC OverviewThe ADC of the ADMC(F)341 is based upon the single slopeconversion technique. This approach offers an inherently mono-tonic conversion process within the noise and stability of itscomponents, and there will be no missing codes.

The single slope technique has been adopted on theADMC(F)341 for four channels that are simultaneously con-verted. Refer to Figure 11 for the functional schematic of theADC. The main inputs (ISENSE1 to ISENSE3) are connected to theADC converter through three front end blocks. Figure 15 showsthe block diagram of a single front end block. Each front endblock has a bipolar current amplifier (Gain = –2.5) designed toacquire the voltage on a current-sensing resistor whose voltagecan be either positive or negative with respect to the powersupply ground rail.

The fourth channel has been configured with a serially con-nected 4-to-1 multiplexer. Table VI shows the multiplexer inputselection codes. One of these auxiliary multiplexed channels isused to acquire the internal voltage reference (VREF) for calibra-tion purposes.

Table VI. ADC Auxiliary Channel Selection

MODECTRL (1) MODECTRL (0)Select ADCMUX1 ADCMUX0

VAUX0 0 0VAUX1 0 1VAUX2 1 0Calibration (VREF) 1 1

ADC1ADC2ADC3

ADCAUX

COMPISENSE1

ISENSE2

ISENSE3

VAUX0VAUX1VAUX2

VREF

ICONST

CURRENT

VOLTAGECHANNEL1

CURRENT

VOLTAGECHANNEL2

CURRENT

VOLTAGECHANNEL3

4-1MULTIPLEXER

VAUX0 (V)VAUX1 (V)VAUX2 (V)VAUX3 (V)

MODECTRL REG

COMP

COMP

COMP

ICONST

FILTER

12-B

IT A

DC

TIM

ER

BL

OC

K

V1L

V2L

V3L

VAUXL

PWMSYNC (CONVST)

MODECTRLREG

CLK

MODECTRL REG

ICONST_TRIMREG

CAPACITOR RESET

Figure 11. ADC Overview

Single Slope ADC OperationsThe ADC conversion process is done by comparing each ADCinput to a reference ramp voltage and timing the comparison ofthe two signals. The actual conversion point is the time-pointintersection of the input voltage and the ramp voltage (VC), asshown in Figure 12. This time is converted to counts by the12-bit ADC timer block and is stored in the ADC registers.The ramp voltage used to perform the conversion is generatedby driving a fixed current into an off-chip capacitor, where thecapacitor voltage is:

V I C tC = ×( )

Table V. Fundamental Characteristics of PWM Generation Unit of ADMC(F)341

Parameter Min Typ Max Unit

16-BIT PWM TIMERCounter Resolution 16 BitsEdge Resolution (Single Update Mode) 100 nsEdge Resolution (Double Update Mode) 50 nsProgrammable Dead Time Range 0 102 µsProgrammable Dead Time Increments 100 nsProgrammable Pulse Deletion Range 0 51 µsProgrammable Pulse Deletion Increments 50 nsPWM Frequency Range 1531 78,4312 HzPWMSYNC Pulsewidth (TCRST) 2.0 12.8 µsGate Drive Chop Frequency Range 0.02 5 MHz

NOTES1153 Hz is calculated based on 16-bit resolution.278,431 Hz is calculated based on 8-bit resolution.

REV. A–18–

ADMC(F)341Following reset, VC = 0 at t = 0. This reset and the start of theconversion process are initiated by the PWMSYNC pulse, asshown in Figure 12. The width of the PWMSYNC pulse iscontrolled by the PWMSYNCWT register and should be pro-grammed according to Figure 13 to ensure complete resetting.

To compensate for IC process manufacturing tolerances (and toadjust for capacitor tolerances), the current source of theADMC(F)341 is software-programmable. Using software to setthe magnitude of the ICONST current generator is accom-plished by selecting one of eight steps over approximately 20%current range.

VC

V1

PWMSYNC

COMPARATOROUTPUT

VCMAX

TVIL

TPWM – TCRST

TCRST

Figure 12. Analog Input Block Operation

The ADC system consists of four comparators and a singletimer that may be clocked at either the DSP rate or half theDSP rate, depending on the setting of the ADCCNT bit (Bit 7)of the MODECTRL register. When this bit is cleared, the timercounts at a slower rate of CLKIN. When this bit is set, it countsat CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,and ADCAUX are the registers that capture the conversion times,which are the timer values when the associated comparator trips.

200

150

100

50

00 2 4 6 8 10

DE

CIM

AL

CO

UN

TS

CHARGING CAPACITOR – nF

Figure 13. PWMSYNCWT Program Value

ADC ResolutionThe ADC is intrinsically linked to the PWM block through thePWMSYNC pulse’s control of the ADC conversion process.Because of this link, the effective resolution of the ADC is afunction of both the PWM switching frequency and the rate atwhich the ADC counter timer is clocked. For a CLKOUTperiod of tCK and a PWM period of TPWM, the maximum countof the ADC is given by:

Max Count T T t

for MODECTRL Bit

Max Count T T t

for MODECTRL Bit

PWM CRST CK

PWM CRST CK

= −=

= −=

min

min

( , ( )/ )

( , ( )/ )

4095 2

7 0

4095

7 1

where TPWM is equal to the PWM period if operating in singleupdate mode to half that period if operating in double updatemode. For an assumed CLKOUT frequency of 20 MHz andPWMSYNC pulsewidth of 2.0 µs, the effective resolution ofthe ADC block is tabulated for various PWM switching fre-quencies in Table VII.

Table VII. ADC Resolution Examples

PWM MODECTRL[7] = 0 MODECTRL[7] = 1Frequency Max Effective Max Effective(kHz) Count Resolution Count Resolution

2.4 4095 12 4095 124 2480 >11 4095 128 1230 >10 2460 >1118 535 >9 1070 >1025 380 >8 760 >9

Programmable Current SourceThe ADMC(F)341 has an internal current source that is usedto charge an external capacitor, generating the voltage rampused for conversion. The magnitude of the output of the currentsource circuit is subject to manufacturing variations and canvary from one device to the next. Therefore, the ADMC(F)341includes a programmable current source whose output canalways be tuned to within 5% of the target 100 µA. A 3-bitregister, ICONST_TRIM, allows the user to make this adjust-ment. The output current is proportional to the value written tothe register: 0x0 produces the minimum output and 0x7 producesthe maximum output. The default value of ICONST_TRIM afterreset is 0x0.

Charging Capacitor SelectionThe charging capacitor value is selected based on the sample(PWM) frequency desired. A too-small capacitor value will reducethe available resolution of the ADC by having the ramp voltage riserapidly and convert too quickly, not utilizing all possible countsavailable in the PWM cycle. A too-large capacitor may not convertin the available PWM cycle returning 0x000.

To select a charging capacitor use Figure 14. Select the sam-pling frequency desired, determine if the current source is to betuned to a nominal 100 µA or left in the default (0x0 code) trimstate, then determine the proper charge capacitor off the appro-priate curve.

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100

10

11 10 100

CN

OM

– n

F

TUNED ICONST

DEFAULT ICONST

Figure 14. Timing Capacitor Selection

Analog Front EndThe main analog inputs of the ADMC(F)341 (ISENSE1 toISENSE3) are connected to the ADC converter through threefront end blocks. Figure 15 shows the block diagram of a singleanalog front end.

SHA TIMERREGISTER

SHASTATE

MACHINE

MU

X

OVERCURRENTCOMPARATOR

SHA TIMERCOUNTER

VOLTAGE (THIS IS NOT AVAILABLE EXTERNALLY ON THE ADMC(F)341)

CURRENT

PWMSYNC

CLOCKOUT

MODECTRL REGISTERCHANNEL SELECTION (ISENSE/V)

ADC CONVERSIONSTATUS BIT

(ADC REGISTER)

SHA–2.5

VxL(TO ADC)

TRIP(TO PWMTRIP FILTER)

TRIP REF HIGH

TRIP REF LOW

Figure 15. Analog Front End Block Diagram

N–1 N N+1 N+2 N+3 N+4 N+5

1 2 3 4 5 6 7 8 9 10 11 12

CYCLE

PWMSYNC

VC

SHA TIMERCOUNTER

SHA STATUS

ISENSE INPUT

ADC REGISTER

X T H T H H T H

DATA READYSAMPLED ON

CYCLE N–2

INVALIDLSB = 1


CYCLE N

INVALIDLSB = 1


CYCLE N+2


CYCLE N+4

S S SS

TSAMPLE

TSAMPLE TSAMPLE

TSAMPLE

TRACK

Figure 16. ADC Conversion Sequence of a Current Input

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ADMC(F)341

Each analog front end has two analog inputs: voltage and cur-rent. A 2-to-1 multiplexer selects which input will be converted;the multiplexer selection is determined by the MODECTRLregister. Note that in the ADMC(F)341, only the current inputs(ISENSE) are externally available.

The current input (ISENSE) is amplified through a bipolar ampli-fier (Gain –2.5). There is an output offset that matches theamplifier output signal range to the input signal range of theA/D converter. The amplifier has built-in overcurrent and open-circuit protection. The overcurrent protection shuts the PWMBlock when the voltage at any of the ISENSE pins exceeds the tripthreshold (high or low). The open-circuit detection shuts thePWM block when any of the ISENSE inputs is in high impedance(for example, the current sense resistor or transducer is discon-nected). The shutdown signals generated by the amplifiers arethen OR-ed and filtered to avoid a spurious trip caused by theswitching of the power devices. The amplifier is followed by asample-and-hold amplifier (SHA). The SHA time is user-pro-grammable through the SHA timer register. The sampling timeis set as a delay from the rising edge of the PWMSYNC signaland is calculated as:

T SHA CNT tSAMPLE CK= + ×( _ )2

The SHA timer counter has a minimum reload value of 0x0003,which ensures a minimum settling time of the SHA output incase the user is programming the SHA timer register to a valuesmaller than 0x0003. This means that the sampling time isprogrammable from 5 tCK to 65,535 tCK (corresponding to 250 nsto 3.28 ms for a CLKOUT rate of 20 MHz). The sampling timeis limited, however, to the rising edge of the following PWMSYNCcycle. Each channel has an independent amplifier, SHA, andSHA timing unit/state machine. Figure 16 shows a conversionsequence of a single channel.

At the beginning of the cycle N [rising edge of PWMSYNCsignal (1)], the timer counter is loaded with the value containedin the SHA_CNT register. After the timer counter has beenreloaded, it starts counting down at the CLKOUT rate. In thisphase, the SHA state-machine forces the SHA in TRACK(sample) status.

When the counter reaches the value of 0x0000 (after the timeTSAMPLE from the rising edge of PWMSYNC), the SHA state-machine forces the SHA in HOLD status.

The conversion of the sampled value is then taking place in thecycle N + 1 [from (4) to (5)] in Figure 16. The result of theconversion is available on the ADC register at the cycle N + 2[rising edge of PWMSYNC (5)].

On cycle N + 2, the reload value of the timer counter exceedsthe period of the PWMSYNC signal. In this case, the SHAstate-machine forces the SHA in HOLD status at the rising edgeof PWMSYNC of the next cycle (7). The conversion then takesplace on cycle N + 3, and the conversion result is available on theADC register at the cycle N + 4 [rising edge of PWMSYNC (9)].

During the acquire phase (the PWMSYNC cycle during thesampling of the input value), the conversion takes place. How-ever, the value on the ADC registers is not considered valid.This condition is signaled by the ADC by setting the LSB of theADC register to high.

On cycle N + 4, at the rising edge of the PWMSYNC signal (9),the timer counter is reloaded with a value smaller than thePWMSYNC pulsewidth. In this case, the SHA samples withinthe PWMSYNC pulsewidth and the conversion take place inthe same PWMSYNC cycle [from (10) to (11)].

AUXILIARY PWM TIMERSOverviewThe ADMC(F)341 provides two variable frequency, variableduty cycle, 16-bit, auxiliary PWM outputs that, when enabled,are available at the AUX1 and AUX0 pins. These auxiliaryPWM outputs can be used to provide switching signals toother circuits in typical motor control systems, such as powerfactor corrected front end converters or other switching powerconverters. Alternatively, by adding a suitable filter network, theauxiliary PWM output signals can be used as simple single-bitdigital-to-analog converters as shown in Figure 17. The auxiliaryPWM system of the ADMC(F)341 can operate in two differentmodes: independent mode and offset mode. The operatingmode of the auxiliary PWM system is controlled by Bit 8 of theMODECTRL register. Setting Bit 8 of the MODECTRL regis-ter places the auxiliary PWM system in the independent mode.In this mode, the two auxiliary PWM generators are completelyindependent and separate switching frequencies and duty cyclesmay be programmed for each auxiliary PWM output. In thismode, the 16-bit AUXTM0 register sets the switching frequencyof the signal at the AUX0 output pin. Similarly, the 16-bitAUXTM1 register sets the switching frequency of the signal atthe AUX1 pin. The fundamental time increment for the auxiliaryPWM outputs is twice the DSP instruction rate (or 2 tCK) andthe corresponding switching periods are given by:

T AUXTM t

T AUXTM tAUX CK

AUX CK

0

1

2 0 1

2 1 1

= × + ×= × + ×

( )

( )

Since the values in both AUXTM0 and AUXTM1 can rangefrom 0 to 0xFFFF, the achievable switching frequency of theauxiliary PWM signals may range from 152.59 Hz to 10 MHzfor a CLKOUT frequency of 20 MHz. The on-time of the twoauxiliary PWM signals is programmed by the two 16-bit AUXCH0and AUXCH1 registers, according to:

T AUX AUXCH t

T AUX AUXCH tON CK

ON CK

, ( )

, ( )

0 2 0

1 2 1

= × ×= × ×

so that output duty cycles from 0% to 100% are possible. Dutycycles of 100% are produced if the on-time value exceeds theperiod value. Typical auxiliary PWM waveforms in independentmode are shown in Figure 18a. When Bit 8 of the MODECTRLregister is cleared, the auxiliary PWM channels are placed

Table VIII. Fundamental Characteristics of Auxiliary PWM Timers

Parameter Test Conditions Min Typ Max Unit

Resolution 16 BitsPWM Frequency 10 MHz CLKIN 0.152 MHz

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in offset mode. In offset mode, the switching frequencies of thetwo signals on the AUX0 and AUX1 pins are identical andcontrolled by AUXTM0 in a manner similar to that previouslydescribed for independent mode. In addition, the on-times ofboth the AUX0 and AUX1 signals are controlled by the AUXCH0and AUXCH1 registers as before.

In this mode, however, the AUXTM1 register defines the offsettime from the rising edge of the signal on the AUX0 pin to thaton the AUX1 pin according to:

T AUXTM tOFFSET CK= × + ×2 1( )1

For correct operation in this mode, the value written to theAUXTM1 register must be less than the value written to theAUXTM0 register. Typical auxiliary PWM waveforms in offsetmode are shown in Figure 18b. Again, duty cycles from 0% to100% are possible in this mode.

In both operating modes, the resolution of the auxiliary PWMsystem is 16 bits only at the minimum switching frequency(AUXTM0 = AUXTM1 = 65,535 in independent mode,AUXTM0 = 65,535 in offset mode). Obviously, as the switchingfrequency is increased, the resolution is reduced.

Values can be written to the auxiliary PWM registers at anytime. However, new duty cycle values written to the AUXCH0and AUXCH1 registers only become effective at the start ofthe next cycle. Writing to the AUXTM0 or AUXTM1registers causes the internal timers to be reset to 0 and newPWM cycles to begin. By default following a reset, Bit 8 ofthe MODECTRL register is cleared, thus enabling offset mode.In addition, the registers AUXTM0 and AUXTM1 default to0xFFFF, corresponding to the minimum switching frequencyand zero offset. The on-time registers AUXCH0 and AUXCH1default to 0x0000.

AUXPWMR1 R2

C1 C2

R1 = R2 = 13k�C1 = C2 = 10nF

Figure 17. Auxiliary PWM Output Filter

Auxiliary PWM Interface, Registers, and PinsThe registers of the auxiliary PWM system are summarized inFigure 27.

AUX0

AUX1

2 � (AUXTM0 + 1)

2 � (AUXTM1 + 1)

2 � AUXCH1

2 � AUXCH1

2 � AUXCH0

Figure 18a. Typical Auxiliary PWM Signals(All Times in Increments of tCK), IndependentMode

AUX0

AUX1

2 � (AUXTM0 + 1)

2 � (AUXTM0 + 1)

2 � AUXCH1

2 � AUXCH0

2 � (AUXTM1 + 1)

Figure 18b. Typical Auxiliary PWM Signals(All Times in Increments of tCK), Offset Mode

WATCHDOG TIMERThe ADMC(F)341 incorporates a watchdog timer that canperform a full reset of the DSP and motor control peripheralsin the event of a software error. The watchdog timer is enabledby writing a timeout value to the 16-bit WDTIMER register.The timeout value represents the number of CLKIN cyclesrequired for the watchdog timer to count down to zero. When thewatchdog timer reaches zero, a full DSP core and motor controlperipheral reset is performed. In addition, Bit 1 of theSYSSTAT register is set so that after a watchdog reset, theADMC(F)341 can determine that the reset was due to thetimeout of the watchdog timer and was not an external reset.Following a watchdog reset, Bit 1 of the SYSSTAT register maybe cleared by writing zero to the WDTIMER register. Thisclears the status bit but does not enable the watchdog timer.

On reset, the watchdog timer is disabled and is enabled onlywhen the first timeout value is written to the WDTIMERregister. To prevent the watchdog timer from timing out, theuser must write to the WDTIMER register at regular intervals(shorter than the programmed WDTIMER period value). Onall but the first write to WDTIMER, the particular value writtento the register is unimportant, since writing to WDTIMERsimply reloads the first value written to this register.

PROGRAMMABLE DIGITAL INPUT/OUTPUTThe ADMC(F)341 has a 9-pin programmable digital input/output (PIO) port (PORTA). The nine pins (PORTA0 toPORTA8) are multiplexed with other on-chip peripheralfunctions, in accordance with Table IX. When configured as aPIO, each of these nine pins can act as an input or output, or aninterrupt source.

The operating mode (PIO or alternate function) of pins PORTA0to PORTA8 is controlled by the PORTA_SELECT register.This 9-bit register has a bit for each input so that the mode ofeach pin may be selected individually.

Bit 0 of PORTA_SELECT controls the operation of the PORTA0pin, Bit 1 controls the PORTA1 pin, and so on. Setting theappropriate bit in the PORTA_SELECT register causes thecorresponding pin to be configured for PIO functionality.Clearing the bit selects the alternate mode of the correspondingpin. Following power-on reset, all bits of PORTA_SELECTare set such that PIO functionality is selected. The second

REV. A–22–

ADMC(F)341

alternate function of PORTA7 is selected by Bit 14 of thePORTA_SELECT register. The second alternate function ofPORTA8 is selected by Bit 15 of the PORTA_SELECT register.

The second alternate function of the PORTA4 and PORTA5pins is selected by Bit 4 of MODECTRL Register (SPORT1mode: boot mode/UART mode).

Once PIO functionality has been selected for any or all of these ninepins, the direction may be set by the 9-bit PORTA_DIR register.Clearing any bit configures the corresponding PIO line as an input,while setting the bit configures it as an output. By default, followinga reset, all bits of PORTA_DIR are cleared, configuring the PIOlines as inputs. The data of the PORTA0 to PORTA8 lines is con-trolled by the PORTA_DATA register. These registers can be usedto read data from those PIO lines configured as inputs and write datato those configured as outputs. Any of the nine pins that have beenconfigured for PIO functionality can be made to act as an interruptsource by setting the appropriate bit of the PORTA_INTEN register.To act as an interrupt source, the pin must also be configured as aninput. An interrupt is generated upon a change of state (low-to-hightransition or high-to-low transition) on any input that has beenconfigured as an interrupt source. Following a change of state eventon any such input, the corresponding bit is set in thePORTA_FLAG, register and a common PIO interrupt is generated.

Reading the PORTA_FLAG register permits determiningthe interrupt source. Reading the PORTA_FLAG registerautomatically clears all bits of the registers. Following power-on or reset, all bits of PORTA_INTEN are cleared so that nointerrupts are enabled.

Each PIO line has an internal pull-down resistor so that followingpower-on or reset, all nine lines are configured as input PIOsand will be read as logic lows if left unconnected.

PIO RegistersThe configuration of all registers of the PIO system is shown inFigure 25.

INTERRUPT CONTROLThe ADMC(F)341 can respond to 18 different interrupt sourceswith minimal overhead. Seven of these interrupts are internalDSP core interrupts and 11 are from the on-chip peripherals.

The seven DSP core interrupts are SPORT0 receive andtransmit, SPORT1 receive (or IRQ0) and transmit (or IRQ1),the internal timer, and two software interrupts. The motorcontrol interrupts are the nine PORTA PIOs and two from thePWM block (PWMSYNC pulse and PWMTRIP). All the on-chipperipheral interrupts are multiplexed into the DSP core via theperipheral IRQ2 interrupt. They are also internally prioritizedand individually maskable. The start address in the interruptvector table for the ADMC(F)341 interrupt sources is shown inTable X. The interrupts are listed from highest to lowest prior-ity. The PWMSYNC interrupt is triggered by a low-to-hightransition on the PWMSYNC pulse. The PWMTRIP interruptis triggered on a high-to-low transition on the PWMTRIP pin.A PIO interrupt is detected on any change of state (high-to-lowor low-to-high) on the PIO lines.

The entire interrupt control system of the ADMC(F)341 isconfigured and controlled by the IFC, IMASK, and ICNTLregisters of the DSP core, the IRQFLAG register for thePWMSYNC and PWMTRIP interrupts, and PORTA_FLAGregister for the PIO interrupts.

Table X. Interrupt Vector Addresses

Interrupt Source Interrupt Vector Address

PWMTRIP 0x002C (Highest Priority)Peripheral Interrupt (IRQ2) 0x0004PWMSYNC 0x000CPIO 0x0008Software Interrupt 1 0x0018Software Interrupt 0 0x001CSPORT0 Transmit Interrupt 0x0010SPORT0 Receive Interrupt 0x0014SPORT1 Transmit Interrupt (or IRQ1) 0x0020SPORT1 Receive Interrupt (or IRQ0) 0x0024Timer 0x0028 (Lowest Priority)

Interrupt MaskingInterrupt masking (or disabling) is controlled by the IMASKregister of the DSP core. This register contains individual bitsthat must be set to enable the various interrupt sources. If anyperipheral interrupt is to be enabled, the IRQ2 interrupt enablebit (Bit 9) of the IMASK register must be set. The configurationof the IMASK register of the ADMC(F)341 is shown in Figure 30.

Table IX. Port A Multiplexing

PORTA Pin First Alternate Function (Peripheral) Second Alternate Function (Peripheral)

PORTA8 AUX0 (Auxiliary PWM Output) CLKOUT (System CLOCK)PORTA7 AUX1 (Auxiliary PWM Output) PWMSYNC (PWM)PORTA6 DR1 (Data Receive SPORT1) NonePORTA5 FL1 (Flag Out SPORT1) DT1 (Data Transmit SPORT1)PORTA4 SCLK1 (Serial Clock SPORT1) SCLK0 (Serial Clock SPORT0)PORTA3 TFS0 (Transmit Frame Sync SPORT0) NonePORTA2 RFS0 (Receive Frame Sync SPORT0) NonePORTA1 DT0 (Data Transmit SPORT0) NonePORTA0 DR0 (Data Receive SPORT0) None

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Interrupt ConfigurationThe IFC and ICNTL registers of the DSP core control andconfigure the interrupt controller of the DSP core. The IFCregister is a 16-bit register that may be used to force and/or clearany of the eight DSP interrupts. Bits 0 to 7 of the IFC registermay be used to clear the DSP interrupts while Bits 8 to 15 can beused to force a corresponding interrupt. Writing to Bits 11 and12 in IFC is the only way to create the two software interrupts.The ICNTL register is used to configure the sensitivity (edge orlevel) of the IRQ0, IRQ1, and IRQ2 interrupts and to enable/disable interrupt nesting. Setting Bit 0 of ICNTL configures theIRQ0 as edge-sensitive, while clearing the bit configures it aslevel-sensitive. Bit 1 is used to configure the IRQ1 interrupt, andBit 2 is used to configure the IRQ2 interrupt. It is recommendedthat the IRQ2 interrupt always be configured as level-sensi-tive, as this ensures that no peripheral interrupts are lost. SettingBit 4 of the ICNTL register enables interrupt nesting. The con-figuration of both IFC and ICNTL registers is shown in Figure 30.

INTERRUPT OPERATIONFollowing a reset, the ROM code on the ADMC(F)341 mustcopy a default interrupt vector table into program memoryRAM from address 0x0000 to address 0x002F. Since eachinterrupt source has a dedicated four-word space in this vectortable, it is possible to code short interrupt service routines (ISR)in place. Alternatively, it may be necessary to insert a JUMPinstruction to the appropriate start address of the ISR if the ISRrequires more memory. When an interrupt occurs, the programsequencer ensures that there is no latency (beyond synchronizationdelay) when processing unmasked interrupts. In the case of thetimer, SPOR

ADMC(F)341 DashDSP 28-Lead Flash and ROM Memory, Mixed … · 2019. 6. 5. · –2– REV. A...

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