Adaptive Circuit Techniques for Managing...
Transcript of Adaptive Circuit Techniques for Managing...
T.Sakurai
2004 Digital -- Advanced Solid State Circuits Forum:“Managing Variability in sub-100nm Designs”
Adaptive Circuit Techniques for Managing Variations
Takayasu SakuraiCenter for Collaborative Research,
University of TokyoE-mail: [email protected]://lowpower.iis.u-tokyo.ac.jp/
2004/2/19 San Francisco
T.Sakurai
Active leakage may ruin the Moore’s law Po
wer
per
chi
p [W
]
1980 1985 1990 1995 20000.01
0.1
1
10
100
1000
Year
MPU
x4 / 3
years
DSP
x1.4 / 3 years
Processors published in ISSCC
2005 2010 2015
x1.1 / 3 years
ITRS requirement
10000
Dynamic
Leakage1/100
T.Sakurai
Active leakage makes things more challenging
Year2002 ’04 ’06 ’08 ’10 ’12 ’14 ’160
0.2
0.4
0.6
0.8
1
1.2
0
20
40
60
80
100
120
Tech
nolo
gy n
ode[
nm]
Volta
ge [V
]
VTH
VDD
Technology node
2002 ’04 ’06 ’08 ’10 ’12 ’14 ’160
1
2
Year
PDYNAMIC
PLEAK
Pow
er [µ
W /
gate
]
Subthreshold leak(Active leakage)
T.Sakurai
Workload0 0.2 0.4 0.6 0.8 1
Norm
aliz
ed p
ower
P
ƒV2
0
0.2
0.4
0.6
0.8
1
Dynamic power reduction by compensating workload variability
Controller
Clock & VDD
Requiredspeed
Processor
Software
S. Lee et al, DAC, June 2000
HardwareSuper-linear
T.SakuraiCourtesy Hitachi Central Research Lab.
Power reduced to 1/3 by software ƒ-V control
1.5[V] 1.25[V]
Voltage
CurrentSleep Mode
0mA
250mA100mA
50mA
Multi-tasking:MPEG4 & MP3decoding
Application to cellular phones
T.Sakurai
Changing supply voltage is effective
0 0.5 10
0.5
1
Norm
aliz
ed p
ower
VDD [V]
PDYNAMIC
PSUBTHRESHOLD LEAK
PGATE LEAK
65nm tech. Node
VTH=0.15VDIBL coeff.=0.2
1
2
3
4
5
0No
rmal
ized
del
ay
Delay
T.Sakurai
Delay fluctuation gets worse in lower VDD
Fluc
tuat
ion
in d
elay
[%]
VTH=0.15V
0 0.5 1VDD [V]0
102030405060708090
100
)(
)(
)(
fast
Del
ayfa
stD
elay
slow
Del
ay VTH0.1V
VTH0.05V
T.Sakurai, “Panel on Reshaping EDA for Power,” DAC, 2003
Yield degradation
T.Sakurai
Delay fluctuation in logic
n1nfluctuatiodNormalize
n deviationstandarddelayPath
n averagedelayPath
nfluctuatioNormalized
deviationstandarddelayGate averagedelayGate
CMOS VLSI design, Baifukan, 1989. ISBN4-563-03450-9 C3055
Path delay
Gate
T.Sakurai
IOFF fluctuation due to VTH variation
VTH0 : averageVTH: standard deviation
• Within-die VTH variation is normal dist.
D. Frank, et al. Proceedings of the IEEE, 89 (2001) 259
sV10ln
0OFFOFF
TH
eII
VGS
log(IOFF)
IOFF0
VTHIOFF
VTH0 0
10-7
average
average: <IOFF>
Q.Liu, T.Sakurai, T.Hiramoto, “Optimum Device Consideration for Standby Power Reduction Scheme Using Drain-Induced Barrier Lowering,” JJAP. pp. 171 ・ 175, Apr. 2003.
T.Sakurai
Average and standard deviation of IOFF
2
VTH
2VTH
20THTHTH
s10ln
21
0OFF
TH2
VV
VTH
sV10ln
0OFFTHTHTHOFFOFF
eI
dVe2
1eIdVVf)V(II
s10ln
VTHIOFF
boundLower:0VVboundUpper:3VV
theory.distNormal:s210lnVV
0THTH
VTH0THTH
2VTH0THTH
Average
Standard deviation
Equivalent VTH shift
T.Sakurai
Leakage increase by intra-chip VTH variation
<IOFF> is much smaller than the worst case.
1.0
1.5
2.0
2.5
3.0
<IO
FF>/
I OFF
0
0 10 20 30 40 50-50
-40
-30
-20
-10
0Normal dist.
s (mV/dec) 60 80 100
VTH (mV)
<VTH
> - V
TH0 (
mV)0VV
boundLower
3VVboundUpper
s210lnVV
theory.distNormal
0THTH
VTH0THTH
2VTH0THTH
Normal dist.
Upper bound (3)
Upper bound (3)
Inter-chip VTH variability is important!
T.Sakurai
Coping with variability by adaptive circuitWhat to monitor
Leakage current, Speed, Logic thresholdTemperature
How to monitorReplica circuit, Actual circuit
What to controlFrequency , VDD, Body bias
How to controlAnalog, Digital, Software
Granularity of control Chip level , Block level, Transistor level
T.Sakurai
Self-Adjusting Threshold-voltage Scheme(SATS)
VBBN
Self- Sub- Bias
Circuit (SSB)
Leakage Sensor
leak
VGN1 Pwell
ON/OFF
low Vth large leakage SSB ON deepVBB high Vth
high Vth little leakage SSB OFF shallow VBB low Vth• control VTH to adjust leakage current• compensate VTH fluctuation
T. Kobayashi, and T. Sakurai, "Self-Adjusting Threshold-Voltage Scheme (SATS) for Low-Voltage High-Speed Operation," in Proc. IEEE 1994 CICC, pp.271-274, May 1994.
Leakage, Replica, Body bias, Analog, Chip level
T.Sakurai
VTCMOS (Variable Threshold CMOS)
Kobayashi, CICC‘94, pp.271-274. Kuroda, ISSCC’96, pp.166-167.
p-well
ILEAK,LCM
WLCM
Leakage Current Monitor (LCM)
"L"
chip
WCHIP
on / off
Self-Substrate Bias (SSB)
-3.0
-2.0
-1.0
0.0
V TH (
V)
V BB
(V)
0.2
0.3
0.4
0.5
0.6
- 0.2 - 0.1 0 0.1VTH (V)
0.2
VTH with control
VTH without control
VBB
ILEAK,CHIP
1
2
CHIP
LCM
CHIP,LEAK
LCM,LEAK
WW
WW
II
W2
W1
T.Sakurai
Body Bias Control to Minimize Fluctuation
16MbitDRAM
Speech Codec
Multiplexer
MPEG-4 VideoCodec
HostI/F
DRAM
I/F
PLLCamI/F
DisplayI/F
Pre-filter
VTVT
VT VT
T=27℃
-0.1 0 0.1 0.2 0.3 0.4 0.5(|VTH .p|+VTH.n )/2 as processed (V)
VTCMOS in active mode
VTCMOS in standby mode
Conv. CMOS
I DD.
leak
(A
)1E-6
1E-5
1E-4
1E-3
1E-2
1E-1
1E+0
Variable Threshold-voltage CMOSCourtesy of Toshiba Corp.
T.Sakurai
Measured benefit of VTCMOS
I DD
.leak
(A)
1E-6
1E-5
1E-4
1E-3
1E-2
1E-1
1E+0
-0.1 0 0.1 0.2 0.3 0.4 0.5
Tj=70C
(|VTH .p|+VTH.n )/2 as processed (V)
Tj=27C
-0.1 0 0.1 0.2 0.3 0.4 0.5(|VTH .p|+VTH.n )/2 as processed (V)
VTCMOS in active mode
VTCMOS in standby mode
Conv. CMOS w/o body bias control
I DD
.leak
(A)
1E-6
1E-5
1E-4
1E-3
1E-2
1E-1
1E+0
T.Sakurai
Power-on-Shunt Circuit
VT_p
VT_nLogicVT circuit
RD Q
RCounter
enableOSC.
Reset
C
R
VDD
GND
Controller
T.Sakurai
Layout of VTCMOS
Leaf cell w/oP/N-tap.(removed by MDP)
VDD
vnsu
b
vpsu
b
nwellpwell
Advantage no library re-design realized by MDP(Mask Data Processing) and
P&R possibly lower area penalty (minimum 4%)
Disadvantage P/N-taps are not close to transistors
VDD
VSS
VDD
VSS
T.Sakurai
Effect of substrate noise on
Kuroda, ISLPED’96, pp.309- 312.
8x8mm2, 188k gates 0.3 µm n-well, 2-layer metal VTCMOS
n+
n-welln-subp-sub
n+
n+
p+
p+
p+
(a) one substrate-contact
p-sub
n-welln-subp-sub
p-sub n-sub
p-sub n-sub
n-sub
(b) 400 substrate-contacts
T.Sakurai
Jitter measurement
(a) one substrate-contact with noise
(b) 400 substrate-contacts without noise
T.Sakurai
500µs
n-well
p-sub
Active Standby
2V
0V
-2V
4V
n-well
p-sub
2V
0V
4V
-2V
Standby Active0.5µs
Measured VBB waveform in VTCMOS
T.Sakurai
Power penalty of VTCMOS itself is smallIDD
impact ionization
ISUB ~ 0.1% IDD
IPUMP 2≒ ~ 3 Isub
PUMP
IPUMP ~ 0.2 ~ 0.3% IDD (at active)
ILCM ~ 1µA (always)ECV2 ~ 5µF x (3V)2 = 0.05µJ (active <-> standby) eg. MPU: ‘Idle’<->’On’ w/ timer interruption of every 25ms P ~ 2µW
LCM
ILCM
T.Sakurai
Speed-Adaptive Threshold-Voltage (SA-Vt) CMOS
Miyazaki, ISSCC’00, pp.420- 421. Miyazaki, ISLPED’98, pp.48- 53.
220MHz, 1.5-1.8V, 320-380mW, 30A, 4.3MTr
Speed, Replica, Body bias, Digital, Chip level
T.Sakurai
Digital control in adaptive body bias
Phase Detector & Counter
Resistor Network
Bias AmplifierCUT
Delay
Phase Detector & Counter
Resistor Network
Bias AmplifierCUT
Delay
21 sub-sites with separate body bias for each sub-site
J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, “Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage,” ISSCC, Paper 25.7, 2002.
5-bit counter
VREF
VCCA
+- VBP
fCritical path
Phase detector
Circuit block (CUT)
VCC
VSS
VBP,ext
VBN,ext
PD
Bias selector
2R 2R 2R 2R 2R 2R
R R R R
Rf
R
5-bit counter
VREF
VCCA
+- VBP
fCritical path
Phase detector
Circuit block (CUT)
VCC
VSS
VBP,ext
VBN,ext
PD
Bias selector
2R 2R 2R 2R 2R 2R
R R R R
Rf
R
Speed, Replica, Body bias, Digital, Block level
T.Sakurai
Software control of adaptive body bias
Conventional
VDD=0.5VVTHlow=0V94% f/2 operation
Norm
aliz
ed p
ower
VTH-hopping
K.Nose, M.Hirabayashi, H.Kawaguchi, S.Lee and T.Sakurai, "VTH-Hopping Scheme to Reduce Subthreshold Leakage for Low-Power Processors," JSSC, pp.413-419, Mar. 2002.
0
0.5
1PLEAK
PDYNAMIC
VTH is dynamically changed by means of back-gate bias.Workload, Actual, Body bias, Software, Chip level
T.Sakurai
Schematic of VTH-hopping
VTH controller
Freq. control
CONT
fCLK or fCLK/2
VBSP2
Target processor
VTH-hopping(VTHlow&VTHhigh)
Power control block
VBSP1
VBSN2
VBSN1
VTHlow_Enable
VTHhigh_Enable
VDD
GND
VBSN
VBSP
T.Sakurai
Multiple Threshold Voltage CMOS with Body Bias
Yamashita, ISSCC’00, pp.414- 415.
450MHz,1.8V, 8.3M logic gate +20M RAM Tr.
T.Sakurai
Drain leakage
-1 -0.5 0 0.510 -3
10 -2
10 -1
100
VBS [V]
Norm
aliz
ed I D
[A]
Body bias decreases subthreshold leakage
GIDL
VTH,MAX= x VBS,MAX
VBS,MAX
T.Sakurai
Performance increase with body-bias control
Perf
orm
ance
incr
ease
with
bod
y bi
as c
ontr
ol
VDD [V]Condition: keep leakage power at 100ºC with lowest VTH (VTH=0.15VDD) constant
0.5 0.6 0.7 0.8 0.9 1 1.1 1.21.0
1.2
1.4
1.6
1.8
2.0
VTH0.1V
VTH0.05V
T.Sakurai
Performance increase with body-bias control
Perf
orm
ance
incr
ease
with
bod
y bi
as c
ontr
ol
VDD [V]Condition: keep leakage power at 100ºC with lowest VTH (VTH=0.15VDD) constant
0.5 0.6 0.7 0.8 0.9 1 1.1 1.21.0
1.2
1.4
1.6
1.8
2.0
VTH,MAX0.1V
VTH,MAX0.05V
VTH,MAX0.15V
VTH,MAX0.2V
T.Sakurai
Why a group other than circuit solve the problem?Circuit side:
We are the most power-aware people who worked hard on this... without success though and worn out.
To System group:1) Most of software is power-negligent instead of power-aware although only system level can know performance-power tradeoff.2) Give us required performance-tag in protocols.
To Device group:1) First off, come up with non-leaking switch device anyway.2) High-k, low-k and high-µ are great weapon for lower power. 3) Device has not been optimized for power although device guys think it is.
D SC
T.Sakurai
Approaches for active leakage control
DS2GSBS0THGSTHGS
s/VVLEAK
VVVVVVV10I THGS
Source Drain
Main gate VGS
2nd gate VGS2
Body
Double gate transistor
Negative VGS Body bias
Double gate
DIBL
Subthreshold swing
T.Sakurai
The headache is not foreever
1 10 10010 -1
10 0
10 1
10 2
10 3Re
lativ
e le
akag
e po
wer
Scaling variable:
Per gate
Per chip with Tr. Count 1
Per chip with Tr. Count 2
90nmVDD=1V, VTH=0.15V
T.Sakurai
Let’s search for global optimumwith collaboration among levels
Local optima
Global optimumApproaches
log
(PO
WER
)