AD-R149 566 A CIRCUIT GRAMMAR FOR OPERATIONAL AMPLIFIER DESIGN(U) i/iCMASSACHUSETTS INST OF TECH LEXINGTON LINCOLN LAB

A L RESSLER JAN 84 RI-TR-807 N88814-88-C-0622UNCLASSIFIED F/G 9/2 NI

EMhhh~Eh

--ii- I - -0

2.0211111!.2 5 .4 11111.

MIR C P .LO UTO -IS . . -

rEXPEWf9!

a i'n

(a,{ Circuit Grammar'For Operationaln< Amplifier Design

Andrew Lewis Ressler

MIT Artificial Intelligence Laboratory

"-- DTIC-".. EECTKI

u bu m b owJN1

5 ~01 0S 047 S

S

UNCLASS I FI EDSECURITY CLA',SIFICATION OF THIS PAGE (07hen Data Entered)

REPORT DOCUMENTATION PAGE READ INSTRUCTIONS 0REPORTDOCUMENTATIONPAGE_ BEFORE COMPLETING FORM

I REPORT NuMBER 12 GOVT ACCESSION NO. I. RECIPIENT'S CATALOG NUMBER

AI-TR-8074. TITLE (and Subtitle) 5. TYPE OF REPORT & PERIOD.COVERED

A Circuit Grammar For Operational Amplifier Technical reportDesign S. PERFORMING ORG. REPORT NUMBER

7. AUTHOR(#) S. CONTRACT OR GRANT NUMBER(s)

Andrew Lewis Ressler N00014-80-C-0622

09 PERFORMING ORGANIZATION NAME AND ADDRESS 10. PROGRAM ELEMENT, PROJECT. TASK

Artificial Intelligence Laboratory AREA & WORK UNIT NUMBERS

545 Technology SquareCambridge, Massachusetts 02139

,,. CONTROLLING OFFICE NAME AND ADDRESS 12. REPORT DATEAdvanced Research Projects Agency January 1984 01400 Wilson Blvd 13. NUMBER OF PAGES

Arlington, Virginia 22209 9214 MONITORING AGENCY NAME & ADDRESS('ll different from Controlling Office) 15. SECURITY CLASS. (of thie report)

Office of Naval Research UNCLASSIFIEDInformation SystemsArlington, Virginia 22217 1Sa. OECLASSIFICATION/OOWNGRADING' SCHEDULE

16. DISTRIBUTION STATEMENT (of this Report)

Distribution of this document is unlimited.

0

17. DISTRIBUTION STATEMENT (of the abstract entered In Block 20, If different froi Report)

Distribution is unlimited

18. SUPPLEMENTARY NOTES

Artificial Intelligence CircuitNone

19 KEY WORDS (continuo on reverse eide if necessary nd Identify by block number)

Artificial Intelligence CircuitComputer-Aided Design DesignGrammar LanguageOperational Amplifier

20 ABSTRACT (Contlin, on reverse side If necesesry and identify by block number)

Electrical circuit designers seldom create really new topologies or use oldones in a novel way. Most designs are known combinations of common confi-gurations tailored for the particular problem at hand. In this thesis I showthat much of the behavior of a designer engaged in such ordinary design can bemcdeled bv a clearlv defined computational mechanism executing a set ofstvlized rules. Each of mv rules embodies a particular piece of the designer' ]k -oowledge. (OVER)

DD I FN ,3 1473 EDITION OF NOV6,5 IS DUSOLETE UNCLASSIFIEDS N ":f 2- '14- 6601 SECURITY CLASSIFICATION OF THIS PAGE (hen Date Entered)

0

Block 20 cont.

A circuit is represented as a hierarchy of abstract objects each of which is composed

of other objects. The leaves of this tree represent the physical devices from which

physical circuits are fabricated. By analogy with context-free languages, a class

of ciucuits is generated by a phrase-structure grammar, of which each rule describes

how one type of abstract object con be expanded into a combination of more concrete

parts.

Circuits are designed by first postulating an abstract object which meets the

particular design requirements. This object is then expanded into a concrete

circuit by successive refinement using rules of my grammar. There are in general -

many rules which can be used to expand a given abstract component. Analysis must

be done at each level of the expansion to constrain the search to a reasonable set. .,

Thus the rules of my circuit grammar provide constraints which allow the approximate

qualitative analysis of partially instantiated circuits. Later, more carefulanalysis in terms of more concrete components may lead to the rejection of a line

of expansion which at first looked promising. I provide special failure rules

to direct the repair in this case.

As part of this research I have developed a computer program CIROP, which implements

my theory in the domain of operational design.

* .2[*[r" " 1

, 0

77

A Circuit Grammar

For Operational Amplifier Design

by

Andrew Lewis Ressler

S.B.C.S. S.B.E.E. Massachusetts institute of Technology I Accession For* 9 NTIS GRAI!

S.M. Massachusetts institute orTechnology DI &1981 DTCTA

Submitted to the Department of Unannounced 0Electrical Enginecring and Computer ScienceJutri to

in Partial Fulfillment of theRequirements for the B

Degre ofDistribution/Avalability Codes

DocrOR OF PHIL-OSOPHY - vaiil djh&rDist Special

at the

MIASSACHUSETTS INSTITUTE OF TECHNOLOGY f0January 1984

@ Massachusetts Institute of Technology 1984/

0

Signature of Author ~IDepartment of Electrical Engineering and Computer Science

* certified by

Department of Electrical Engineeringand Computer Science

Acceptedv Chairman Arthur C SmithDepartment of Electrical Engineering,

and Computer Science

A Circuit GramminarI-or Opertionaul Amplifier Decsign

Anidre\% I c%& 1% Ressler

Stbmitmed it) the I )partment of IFlcctricail Fnineeriiw .andCoiptier Science on Jaiuiar\ x. 1984 in partial Ijiltillinent 0

of the reqtiriennS br tie I )eLgree of I )octor of P1hihosophi\ inElectrical Frngincering and Comptitcr Science.

Hlectrical circuit designers seldom create really newk topologies or usc old oneCs in a no\ cl way. Most designsarc known combinations of common configurations tailored for the particular problem at' hand. In thisthesis I show that much of the hcham ior of a designecrinaged in suich ordinary design can be modclcd by accirl defined computational mechanism executing a set of sty li/.cd rules. Fa~ch of my rules embodies aparuicutlir piece of the designer's knowledge.

A\ circii- repic scnicd as a hicrarch\ of abstract objects, each of which i% composed of other oibjects. M'ekca\& of Chi, ticc repreeNrt the physical de'ices from 1AhiCh ph'%iC.il Cir-CuitS ire fabricated. B\y analogyA ah context-free languages, a class of circuits is generated by a phrase-structure grammar. of wkhich eatch

rule describes how one type of abstract object can be expanded into a combination of more concrete parts.

CirCuit1. ire designed b) first postulating an abstract object which meets the particular design requirements.*I his object is then expanded into a concrete circuit by successive refinement using rules oif m) grammar.

['Ihcrc arc in general many roles which can be used to expand a gi~en abstract component. Analysis mustbe done at each level of the expansion to constrain the search to a reasonable set Thus the rules of mycircuit grammar provide constraints which allow the approximate qualitative analysis of partiallyinstantiated circuits. Latcr. more careful analysis in terms of more concrete components may lead to therejection of a line of expansion which at first looked promising. I provide special failure rules to direct therepair in this case.

As5 pat (if this research I hai~e developed a computer program. CIROP. which implements in)y theory in thedomain of operaitional amplifier design.

This thesis describes research done at the Artificial Intelligence Laboratory of the Massachusetts Institute ofTechnology. Support for the laboratory's artificial intelligence research is provided in part by the Adv~ancedResearch Projects Agency of the Departmient of lDcfense under Office of Naval Research contractNOOO I4-8O-C-0622.

*

0~~~1

S

* *1lo N1~ Morhcr and Father

0

IS

* S

9]4 0

4 5

* . __

~ ------

-. -- ~- -.... -

K-S

0

S

* 0

0

0

* ~0

* 0

* 0

0

~2k~ - - - -

I ould like ito ihank Gerr% Sussman fior stperh supenision. lie kept inc in the right track: While

%czicou, .,ing me to Ic.,rn more about ph).sics. astronomy. electrical enginecring and other areas outside of*

the realm of computer science.

I cannot hegin to expres.s my thanks and I.oe to my Aifc Linda and my daughter Julie for their

lmoral support and trying to makc mc a "normal" pcrsn.

I would like to thank Patrick Winston and James Robergc for promiding their expertise in artificial

intellip-encc and electrical engineering. respectively. 0

Thanks to Brian Williams and Mike Komichak for their thought provoking discussions after reading

many drafts of my thesis. Also, thanks to Elias Towe. Gerry Roylance. and Tom Knight for reading and

commenting on drafts of my thesis.

Thanks to my sister Janet for "learning me" some English while editing se'eral drafts of my thesis.

Thanks to Mike Kass for teaching me how to juggle and how to aoid becoming too serious.

k°'O

0' 0

".I .- -' _. .. ii ii -- _ :

*I Ni10 I 01 HAl[ Is 5

(CONTENTS -0

1. Introduction ............... ........... .................................................... ...... .... .................................................... 8

1.1 Key Ingredients .......................................................................................................... 81.2 Fornialifing the Do m ain ......................................................................................... II

1.3 C IRO P ....................................................................................................................... 131.4 Control Flow in C IRO P ...................................................................................... 131.5 *lhesis Roadm ap ................................................................................................... 15

2. O perational Am plifier Fxam ple ........................................................................................................... 16

2.1 Scenario ..................................................................................................................... 16

3. Phrase G ram m ar ................................................................................. ................................................ 23 0

3.1 G eneral Concept ................................................................................................ 233.2 Phrase G ram m ar Pattern ................................................................................... 243.3 N ew Parts .................................................................................................................. 253.4 Connections ........................................................................................................ 26 03.5 Fquations ............................................. 273.6 Interpreting Phrase G ram m ar R ules .................................................................. 293.7 Phrase G ram m ar R ule Exam ples ...................................................................... 30 "

4. Analyzing the Circuit ................................................................. ...................................................... 34

4.1 H ierarchical Fquations ...................................................................................... 344.2 O RACIt'- A n Increm ental Algebra System .................................................... 374.3 Proccdurc wscd in O RAC I.F system ................................................................. 414.4 C IR CO M .................................................................................................................. 42

5. Controlling the l)csign Process .................................................. ........................................................... 44

5.1 G uiding the Prototype ......................................................................................... 445.2 A nalysis and Testing .............................................................................................. 47

5.3 Failure R ules .......................................................................................................... 485.4 Backtracking with Failure Rules ............................................ 50

5.5 The Knowledge used to Develop Failure Rules . ......................................... . 50

* 0 I

* .0

r -°.- - - --. . - -. - .. .-- - -.. - -w --. - .- -, . - -,... ° -.. - -*- . . -- r-- . • -- t -- r.

I.\ ABI 01 (O\I\I\IS - •

b. l) taikd Q perational Am plifier Exam ple ................................................................................................ 56

6.1 Detailed Scenario ..................................................................................................... 56

7. Related \ ork .............................................................................................................................................. 60"

7.1 E1 ............................................................................................................................... 6( 1

7.2 SY N ........................................................................................................................... 617.3 A Sim ple M odel of C ircuit I )csign .................................................................... 63

7.4 Q ualitative Analysis ........................................................................................... 65L 7.5 A Refinem ent Paradigm .................................................................................... 65

7.6 M olgen ...................................................................................................................... 67

8. (onclusions ................................................................................................................................................. 69

8.1 limiuitions of a $trict Hierarchy .............................. 698.2 Transf rm ations ................................................................................................... 728.3 Algebra ...................................................................................................................... 738.4 )irecting the Search in C ircuit Space ............................................................... 74

4 8.5 Frequency Analysis .............................................................................................. 74

8.6 Sum m ary ............... .................................................................................................... 75

9. Bibliography .............................................................................................................................................. 76

Appendix 1. Phrase G ram m ar Rules .................................................................................. 78

1.1 Summary of Types of Operational Amplifiers ................................................... 781.2 Abstract O bjects in the Phrase G ram m ar .......................................................... 791.3 Prim itive O bjects in the Phrase G ram m ar ....................................................... 91

i \l0 I 01 [:16. R FS 7

FIGURES

Fig. 1. C om plex O perational Am plifier ......................................................................................................... 9Sig. 2. I lircc St ge O p rational Am plifier .................................................................................................. 10Il1. 3. )arling on Pair ................................................................................................................................... IIFig. 4. Sim ple Recursivc C ircuit G ram m ar ........................................................................................... 12Fig. 5. Flo% C hart of C IRO P ........................................................................................................................ ]4Fig. 6. I'artial T rcc of O pcrational Am plifier H ierarchy ...................................................................... 17Fig. ". Ahstr ct First S cagc ............................................................................................................................ 17I-ig. 8. Ahstract I)iffcrcntial Pair ................................................................................................................... 18Fig. 9. M atched Pair ....................................................................................................................................... 19F ig. 10. Protot.pe O perational Am plifier .............................................................................................. 20Fig. II. Amplifier SUges t be Improved ....................................... 21Fig. 12. Final O perational Am plifier ...................................................................................................... 22 0Fie. 13. Context Free Language G ram m ar Exam ple ............................................................................ 23Fic. 14. K C I. Assertions ............................................................................................................... 27Fie. 15. C urrent M irror ............................................................................................... ......................... 36Fig. 16. A lg ebra Exam ple ......................................................................................... ............................. 38Fig. 17. Algebra Exam ple ...................................................................................................... ...................... 39

i. 18. Tradeoff of Specifications .................................................................................. .................... 47Fig. 19. C urrent G ain in Com m on Em itter Transistor ......................................................................... 51Fig. 20. Input Bias Current Exam ple ...................................................................................................... 52Fig. 21. Super-beta D ifferential Pair ........................................................................................................ 53Fig. 22. D arlington D ifferential Pair ........................................................................................................ 54Fig. 23. Exam ple for El- and SYN ........................................................................................................... 61Fig. 24. T ransistor m odels used in SY N ................................................................................................. 62Fig. 25. Cascode C ircuit Synthesized by SY N ........................................................................................ 63Fig. 26. C urrent M irror .................................................................................................................................. 64

Fig. 27. C urrent C ancellation G oal ........................................................................................................ 69Fig. 28. D etails of C urrent Cancellation ................................................................................................ 71 0

Fig. 29. O utput Stage Protection by Transform ation ........................................................................... 72Fig. 30. Inductor Transform ation ............................................................................................................. 73

* +0

* 0

* 0 I

-* .•

E~ ~ 1\ Mo H0)I) II\

I. Inroduction

I leciric'11 circuit11 desu,1CINe "eldOi Cc.iic ic,ill'\ iie% topoloies or u-se old One', in a flo\c ci \ Most

'L"11,1n" .ne% knlo~ n1 eoiiuhini'tions of .ounn11ln conliivur.1tions 1.uilorcd for the pirticular piohleun it hiind.

\li of the bhh' bir of at designer engeaced in such ordinir% design can he mnodeled hi clearr1\ detine-d

computat0ional mechanism executing a set of st\ li/cd rule,,. [he inmplementation (it' this model. (Ill<OI. can

icsign opcrat onal amplifiers. such as the one in Figure 1. In this circit. se' era! comnmonl\ recogniiied

collections of objects are circled. a differcntial pair, aj current mirror, and the three main stlages oif the

orcevutional amnpliFivr. Such at collection of objects can be considered a complex abstract object. made of

f internal components, and can bc used as a component in a larger circuit. For example. Figure 2 shows t pica]

represenujtion of an operational amplifier as a circuit composed oif three parts: the First. second and third

Nte. ichi of these stages is a complex object composed of more primiti'e objects. A simill set of such

comiple\ abstraict objects can represent hierarchically a large number of \alid circuits.

01I%'I' does suprisingl\ %Aell at the taskA Of Circuit design. It designs circuits at the lekel of comrplexic\

* described in Solomion's cl,issic piper JI74J. [b us. CIROP demonstrates an upper hound (on the amount of

(k koA~ ledge needed to achie\ e this lev el of compoiance.

1.1 hei Ingredicnts

*Here are the key ingredients in the model of design that I present:

*Context- Free Hierarchical Expansion

*Failure D~ependent Redesign

4 * Circuit Kno~ ledge Forimalization

lDisiding a complex task into several smaller easier tasks is a well-known methodology for sol~ing a

problem [Simon]. D~esign begins A~ith an abstract concept describing the ultimate object to be synthesized.

4 The engineer proposes d method for building the object in terms of other known objects. This divides the

proiblem into se~cral smaller subproblems which arc modcled naturally in a hierarchical fashion. The

context-free assumption implies that the solution to each subproblem is independent of the othier

suhproblemrs. Fortunaitely, the electrical engineering world is particularN amenible to this hierarchical

prdudim of design. as exemplified hi the operaitional amplifier.. Its internal design can be characterized as a

1 ki KI I\k.t{ID1)1 \IS 9

vC0

Out

00

hierarchy of objects, and the operational amplifier, itself, is usually a small piece in a larger design. The

hicrarchy is implemented as a phrase grammar. which is a set of rules that describe a space of possible circuit itopologics. Any circuit generated by this grammar is ,alid. Tlhc grammar rulcs expand each abstract

topological fragment (a non-terminal of the grammar) into a more concrete topological fragment. By

SI (. I ,RI I)II\IS 10 -

First Recond ThirdStage Itdge Stage

V 1 Vto I --- I toV VtoV0

V2 Input Gain BufferV2-Gain

Fig. 2. Three Stage Operational AmplifierSimple Representation ofThrec Stage Operational Amplifier

applying a sequence of these rules, one begins %kith an abstract topolog) and expands it unil all the elements

in the topofog% correspond to ph.ysical objects and need not be expanded further.

A typical simple abstract object is the darlington pair in Figure 3 composed of two internal transistors

conncctcd as shown. 'he equation in the figure is a constraint describing an aspect of the object's behavior

and is used in the object's analysis.

There may be several ways to expand each abstract object in a hierarchy. Figure 4 describes two

different rules in a circuit grammar that together recursively define a filter. The simplest filter'is created by

expanding the abstract filter goal using Rule 1. The next more complex filter is created using Rule 2 first.

This expansion creates another goal of designing a filter which could be satisfied by using Rule 1. Tlhis

example also shows that hierarchical descriptions of circuits applies to ohjects besides operational amplifiers.

0 "-, .

I ki I\( RI I)!I.%l 1. IM

(collector)

(collector q1) 6

a a

:(base ql) ,

(base),

, (collector q2)(emitter ql), -.

I ~II

IIa I

(base q2) Q 1,2

(emitter q2)

(emitter)

0! d.arlingtn = P of Q1 *B of Q2ie,. 3. D.arlinglton Pair

A darlington pair is a virtual transistor that has higher than a single physical transistor.

1.2 Formalizing the Domain

The concepts that must be formalized for design are as follows:

. Primitive Objects

• Composition Knowledge

. Analysis Knowledge 0

. Strategic Knowledge

Eliminating Candidate Circuits

Guiding Redesign of Circuits

As the physical basis of circuits. primiliv'e objects are the vocabulary of the domain. Transistors.

U U - - J *4 ' .'' - J -'

I"

* I .,I 0 II (\ I I I I IO % I\I

Rule 1I- ;

Filter To DRule 2 L

Filter Filter

* •

Fig. 4. Simple Recursi'c ('ircuil Gr'antarhe top part of the figure rcprescrnt one Aa) to build a simple filter. "lc bottom of the figure shows another

way which is recursive.

resistors, and capacitors arc typical primitie objects. Composition knowledge describes how to create complex

abstract objects from the combination of other abstract and primiti~c objects. The composition knowledge is

explicit in the phr.-c grammar nile. iach rule describes one win to combine objects to create an abstract

object. Analvsis knowlcdgc erifies and tests the behaior of designed objects against the goals. Sira gic

knotedge controls the design process and includes the knowledge neccsary to make the control decisions.

Control is critical for both guiding the design towards a good proposal and guiding the redesign of an

4n

l S

* S

I tlH~l'13

un%.tisfxctor. circuit.

1.3 (IROP .6

CIR01' mhodies %ocahular% and composition kno- ledge in a hierarchical phrase gramma r that models

the hicrarchical struciure ofcircuits naturallb. tLch of its rules describes how to build a circuit object in terls

of more basic objects. Analysis knowledge is represented as a set of constraints asserted with each rule thai S

describes the bcha% ior of the object and passes constraints to its component parts. Using thc. constraints, the

circuit is anaIed and compared to the specifications givcn by the user. The constrains also represent

strategic kno) ledge that restricts the search space of possible circuits. Failure rules formalize the strategic

knowledge used by an engineer to correct the design of a circuit which fails to meet the specifications.I

)uring expansion, strategic knowledge guides The design. Each rule proposed fir expanding an object

is checked for strategic knowledge about its applicability. If the strategic knowledge determines that the rule S

is not applicable, another nile is chosen to expand the current object. CIROP searches the space of possible

circuits cfficicnt1. When strategic knowledge shows that a rule is not applicable. CIROP avoids that entire

region of the space. 0

Thc phrase grammar rules assert equations which describe constraints between the parts. These

equations are used to analyze a rule's applicability and to verify a completed circuit against the specifications.

If a specification is not met. CIROP determines which sections of the circuit do not meet specification. Then 0

one of these sections is redesigned to improve the specification. Failure rules embody knowledge used to

redesign circuits based on their failure. From the applicable failure rules. a rule is chosen. This failure rule

suggests an alternative method of designing a particular piece of the circuit based on the specification that

failed.

1.4 Control FloA in CIROP

The general procedure of CIROP is shown in Figure 5. The top level goal is a description of the

abstract object to build and a se" of specifications to meet. CIROP finds an appropriate rule to expand the

abstract object and then analyzes the resulting circuit. If the circuit is not complete, CIROP goes back to thefirst step to expand some abstract object. The circuit is complete when all the abstract objects have been

6

414 W \ I RolI ii OW 1\ CIROP 1

e~paiided it physicajl objechs. iek coinpkic circtiiI is compared with the original specificadis. It' thc

specificditiofls arc mat the circuit is inkhled. If riot. a stiggestiori is made lo improv'e die circuit. Suggkestions

deccrhhc a piece of Lhc circit it) replace and aii abstract ohject it replatce dhe had piece. If nio siqecstions irc -0

lou id C.1R01 cannot de'sigi the specified circuit.

CIROP

Top Level Goal

Expanion o

NoNorvmetoNpetFaile

No S1

I I II SI RO.\I) ..AP

1.5 i Icsdis Rdild.wp

Chapter 2 is a scenario of the design of a it pical operational amplifier. It denm mrIrs th,i an~0

lpe . tioitll amplifier c.in he dc-rihcd hicrrChiI.l1. mid tlh.it specilic.itions inIiucIm'I c h.' 1 Cr.,mon of the"

circuit. Uivpwr 1 descrihes (lROI\ pI h, g rammari rules ii Jet.mil. '(.hptel 4 dc c, the ,m.ehm,

inechan1l OR(I I' ites .ma/c die circus prduticd h\ ifs phras gr,mmmr rils. (i.'l ter 5 desuihes

CIIROP'cn tl mcch,miki for.guiding the design ,and idesi,-m of lhecircumu. Chpter 6 dCtaIls the &cntrio

hou it in mCh. pcr 2. Chapter 7 discusses hoA CIROP relates io othcr research in the arca of design. ChaIpter

8 sumnimri/cs thc work and discus es limitions orf this approach. Appendix I enumerates CIROP's phrasc

grammar rules. For gencral information on operational amplifiers, scc the book b\ Robcrgc 119751.

C-"0

* 0 1

; '0111' R \ I I0\-A1 A.\ll11 11IWR F1A \I'I 1: i,

2. Operational Aniplifier aniple

CIROP seenm, to do design in a human-like wA. becatsc huian desieners can .understand the

K:, * ,',1.,.ii ',,c,, and the decisions it makes. l he 1i1i inv ,cenari d,.non,,r.,es a t\pical design b\SII<OI'.

2.1 Scenario

Ihc initial goal is to build an operational amplifier with the following specifications.

gain 500000. "input-offset-current 10 tanoampsslew-ratc 0.2 volts per micro-sccondoutput-drie c-current 15 milliampsunit\ -gain-frequenc) 3 Megahertzoutput-load- resistance 2 kohimsinput-bias-current 0.2 mcroamps

Opeiational amplifiers haxe two \oltagc inputs and one voltage output. Ilie main goal of an amplifier is

to pro\ ide gain. The most common operational amplifier, shown in Figure 2. has three main stages. The first

stage conerts the differential input to single-ended and provides gain. The middle stage provides any

necessary gain that the first stage cannot supply. The third stage buffers the output.

In general. CIROP has several choices for implementing each stage of the operational amplifier. Figure

6 is a partial tree of the hierarchy showing some options. For instance, the first stage can be implemented as a

simple differential pair, a current cancellation differential pair. or a super beta differential pair. If the simple

differential pair is chosen, it has two internal parts: the load and the emitter coupled pair. The load can be

implemented as either a resistike load or a current mirror. In this design example. CIROP proposes the

simple differential pair, shown in Figure 7, for the first stage, which is the simplest choice. Before proceeding

with the design. the constraint between the gain and the input bias current is checked to see if the proposed

first stage will be sufficient. Assuming that the second stage can provide lots of gain (maybe it will be a 0darlington pair) the first stage will need a transconducance (gi) of at least .0004 mhos. The

* I

0

I~t 1 ARIO 1

OP AMP

Simple Three Stage Operational Amplifier

Differential Pair Current Super Beta .Resistive' Current Mirror Simple Pair Darlington

Fig. 6. I'artiaI ilrec orOper.itio'ial Ampliier IlicrarchyPartial ircc of tthc hicrarch), implemented For designing operatiornal amplificrs.

* Load Stage

Current Mirror

I Output

11 2

V Simple Diff Pair V2

Differential Pair

Fig. 7. Abstract First Stage* The first stage of in operational amplificr is usually composed of a diffcrcritial pair with a load.

Km

7 I, I \\R IO I.

tr, conductAncc of a diIlcrential pair is relted to he bia current as Ijllos:

01lbialsqf - l .

I otal gain =t:m I oading [lransreid inc

lherefore. the bias current A ill he at lc,ast 0.2 microanips. which nieets the h.ia, specifh.eation. The.

proposed first stage is adequate for now.

Figure 8 represents an abstract differential pair. It uses a matched pair of transistors for the

emitter-couwled pair. A matched pair is a pair of transistors with nearly equal physical charactoristics. Figure

1I I,1 2

Collector-1 Colector-2

V1 -- Base-1 Matched Pair Base.2 VEriitter-1 Emitter-2

Current 6Source

Fig. 8. .bstract )ilTffrential PairTh simplest differential pair uses a matched pair and a load.

I. The %ati.c of the constants 'c as follows:= 00? Volts

(40 for pnp transistors

Ib. ,1 j rr.'r L, a propun) that depends lare)C) on the dc~iccs ph) sical charactcnstic.

11 'I SU \\klh I --

S Ia ,inaliched pair.

0

Collector-i Collector-2I-

Base-i Base PNP BJT PNP BJT Base Base-2

Emitter Emitter

Emitter-1 Emitter-2

60

Hg. 9. Matched Pairlhc natched pair is composed of two identical physical transistors.

Mcanwhilc. the second stage can be a simple common emitter stage. although a darlington pair may be

nccessar) later. Continuing in this manner. the rest of the circuit is designed. The final circuit is similar to

Figure 10.

Howcver, a more careful analysis of the complete circuit reveals that the gain and the bias current

specification cannot be met simultaneously. The first stage. the first stage matched pair, and the second stage

transistor are the direct causes of the gain as shown in Figure 11.

To improve the gain CIROP must rebuild one of these options, CIROP's first choice is to replace the

second stage's single transistor with a darlington pair. The improved circuit as shown in Figure 12 is analyred

and mects the specifications.

1iS(I \\IO

+v V.in in

C outt-i I-

VEE-Fig. 10. Prototype Operational AmnplifierFirst Prototype for thc operational amplifier being designed.

This example demonstrates CIROP using many of thc types of dcsign knowledge uscd by a human

engineer. The vocabulary and composition knowledge arc used to construct a valid circuit. Strategic

knowledge is uised to determine which parts are used to build the operationail amplifier and how to rebuild an

liiItnarfctor) Prototypc operational amplifier. Analysis knowledge is used it) determine the pcrformancc of

tie circuit.

I*kI

(P Load Stage

V1 Simple Diff Pair V2

Fi.11. Amnplifier Srtages to he IrnproiedThe stazes that might be redesigned to impro e t~he gain arc circled.

I1 S( I\VNHIO

vcc

in vin

c ~Vout

U -VEEI- [mu1.Fia Operational Arnplifier

\11 ipif-wr designed by CIROP that required baicktracking to imprnnc the circuit by replacing a simplcsecond SLIPC idl a darlington pair transistor.

211

3. Phrase (oranimar

( 3.1 (,,encral Concept 0

\ circuit phrae grammar is a set or r-ules specifying a circuit language h iectirsiIc cxpansion. The

rulcs sho hoA a (non-tenninal) symbol fe'a\ he expanded into a combinAtion of* , rnhuls. This expan,,ion

process is rcpeited until no non-terminals arc left (oh. jeci, i hich could he expanded). I fhe termimal elements 0

in the grammar are ph. ,ical ohjec. and die r sultng topolog. is a legal sentence of the grammar. I'he

gr.immar dcscribes a set of topologies that perform useful functions. The grammar is extensible since new jniles can be added at any time. S

In contrast to a language grammar. a circuit grammar specifies how to combine components to make

cunipoUnd structure.,. In language grammars. the onl method of combining parts in surface language is

juxtaposition, whereas in circuits one must specify the resulting topology. Figure 13 is an example of a simple

11l.tge- grammar.

Grammar Rule

S::aSIa

Example derivations of sentences of above grammar where S is the top level object:

S =>a

S =>aS =>aa

Fig. 13. Context Free l.anguage Grammar Example

CIROP's phrase grammar rules have two main parts: the pattern and the body. The pattern describes

the main characteristics of the abstract object that it builds and determines if the rule is applicable whcn

building an object. The body is a list of assertions describing how the object is built and analyzed. There are

three types of assertions used. The new-part assertions describe internal components. The connection

1. I or more information on languape grammars .sec Aho(1979].

• • . - . .,.

--RV 7 .t -7 7 V.*~

1 t.1 \I:R.\I CO)\ 1'1 24 f . iI

assNcrtlons create the iol oloc\ b\ comnccig the internal components to each other and to the abstract object.

The consirdirit-cquation assertions creite constraints bei\mcen the conponents and the ,btrlct object.

CIROP's rules include the rclations betceen dhe intcrnal objects. that can bc used to simplif. anihlsis of thc

resulng circuit.

lypical structure of a phrase grammar rule.(Lo-make-a name

pattern

new-partsconnectionsconstraint-equations)

3.2 Phrase Graimmar Pallern

Every phrase grammar rule includes a pattern that is used to determine if the rule can create the

currentl proposed ohject. The pattern includes the following three components: the ijpe property. the has

properties, and the spccificafion tradeoffs. The pattern for the simple differential pair is as follows:

(where (type amplifier)(has (input differential))(has (input voltage))(has (output single-ended))(has (Output current))(has (sign ?sign))(has (simplest 1))(with-specs(= transconductance (S bias-current beta q/kT))( offset-voltage simple-offset-voltage)))

The ilye property says that the differential pair is an amplifier. The has properties list a variety of properties

that a differential pair will have. The simplest property of I means that this is the simplest method of building 0

this type of object. The with-specs denotes a list of specification tradeoffs. In this example, the

transconductance is equal to the product of the bias-current and the constants beta and q/kT. This is the

tradeoff used in the example in Chapter 2 to check if the rule was applicable.

A pattern may include variables which arc denoted with a "?" as is the ?sign variable in the example.When the pattern is matched, the ari,ihlc will match anything in the corresponding position in the matching

pattern. This binds the value of the variable so that an), place in the rule that uses the variable will have that 0

Nalue. In the example pattern the ?sign variable is used to pass the type of transistor to use inside the

-S

• . . .-. ° .. -. . , -, .. - - .. .

diftrential pair.

3.3 Ntei Parts .

M -I' \RI is the assertion that specifies a component of tile nile currcn.h being expanded. lhc

,tsertion's tllree .irguments are the name. pattern. and use. The part name allo~s equacion assertions in the

i rule hod\ to reference properties of the object. The pattern is used to match rules applicable to creating it. "

When matching a rtllcs pattern. the ipc propcrt\ must match exactl. and cecr\ ha.s propert) in the

NF\-PART pattern must be in the niles pattern. Has properties in the rule's pattern are not required to bc

E in the NM\-PARrs patem. Each NEW-PART may also ha\c a usw propcrt\. which is examined in the

aa,1.sis phase of CIROP. Following is an example of a NEW-PART assertion used in the rule for a

three-stagc amplifier to spccify a differential stage for its first stage. This NE\\-PART assertion matches the

example used to describe rule patterns in section 3.2. In this example the sign property is pop, so that the

atuc of the ?sign variable in the rule pattern from section 3.2 %ill be pnp.

(new-part first-stage((type amplifier)(has (input differential))(has (input voltage))

(has (output single-ended) S(has (output current))(has (sign pnp)))(use ((gain gm) (slew-rate gm))))

The process of finding a rule to expand a NEW-PART is more than simple pattern matching. It is a

negotiation between the NEW-PART's pattern, which is an advertisement for a part. and a set of rules which 0

are the applicants for filling the job of that part. CIROP mediates between the applicants. First. CIROP

considers only the applicants of the right type. CIROP eliminates any that do not have the specialties (the has

* properties) required for the particular part so that de remaining candidates hase the right properties. So far _

all CIROP has done is simple pattern matching. Now it must determine the best candidate. Assuming that

the simplest is best. CIROP sorts the candidates. simplest to most complex. Finally. it asks each candidate,

starting with the simplest, if it thinks it can do the job. The first candidate that replies "yes" is chosen for the

job. A candidate answers "no" if its specification tradeoffs cannot possibly meet the specifications. Since

,- .-- i , .T . . . . . , , . 4 . ' . . -~ . ---o . -. ,.--',. -, -- ,, ".. -. ;.- ,

- ~4 COW\ I "10\S ,•

I lIR ' can h.ackt rmick. it is Alt I ahlc Iir the candidate to repl% ") c" x cin if'.it the end it is not still'ici-t.

3.4 ( onnclions

* ennin off bjects are connected using one of the assertions ('ONNI(I. or RkIl.-(ONNF(T.

lliese assertions are the gluC that pro% ides the topological stncturc to the circuit. I he ('ONNI"'I assertion

states that a group of objcct's terminals are conneccd together. This assertion aumoniatical]N generates an

assertion corresponding to Kirchoffs Current I.a- (KCI ). A hich states that the suin of the currents flowing

into the mentioned terminals equals zero.

The current's direction is positive for current flowing into an object's terminal. If a connection includes

terminals from an abstract object to one of its component terminals, it negates the current flow from the

abstraict terminal when creating the KCI.1 assertion. This is shown in Figure 14.

The ] .Mx.-CONNECI" assertion stites that the mentioned terminals are connected to either the power

or ground bus of the circuit- No KCL assertions arc generated from the RAIL-CONNECT assertions since it

would violate the hierarchy for one rule to connect all the bus terminals together. S

I 1hc cxamplcs in thi. thcs, do no( cxplicil) mcntion KircholTs Voltage taw (KVL). which states that the sum of the %oltages arounda closed loop is /cro bi, is not indicatic of a limitation in the Jhcon. hut that the particular camples did not need it for their analysis.Must of the internal opcrt ion of an operational amplifier can be anal% /ed in tcrrns of curcni flois with littlc reference to %oltac loops

P0

[5 i -.-----•- - .- '- - |i 1- 4 t \\I'IIONS 7

A

D E

(Connect D E)

0 = (Current D) +e (Current E)

* (Connect A B C)

o =-(Current A) + tCurrent B) *(Current C)

Fig. 14. ..C. AssertionsrdCIROP ceates KCL assertions from the CONNECT assertions as shown. Thc currn from terminal A is

neeated since it is from the surrounding abstract objeck

3.5 Equations

The knomA ledge used for analysis is contained in the cqUiltion assertions. A hich assert relations between

- properties of the parts. or propap~te constraints from an abstract objecct to its inicrnal part-,. 'I10 prescr~c the

creation rules hierarchical namure. the eqlutions must refer onl\ to the abstract object's properties or an\

part's ad'ertiscd properties. An advertised property is a property of a part included in all methods for

building that part. For instance. if a virtual transistor is part of a circuit, the object requiring the virtual

transistor does not know whether the virtual transistor will be implemented as a single transistor or as a

darlington pair. Therefore, the object cannot refer to a parameter such as the P of the first transistor in a

darlington pair imtplementation of the virtual transistor, but only to the P~ of the combination.

When CIROP solves these equations. an equation might nced to know which variables to leave as

*-]

r-

3 I QL I IONS

unknowns. and which %ariahles to tsoe for. immeditel%. For instmic s1I ing lor the fl of'a transistor. in

tcns of the gmi and tie collector current, is u,,clcs, since ft is .a phy,,ical constant. lo sohxe this problem.

Cl lROl' uses "% ariable priorit.' ' 1 [ hat is. in sol ing an equation. the s\stcm examines the priorit. of each -

,1.1hl c that it could -ohc for. and then soies or the highest priorii% ariahle. When \ariable hasc the

,,me priorit. CIROP can choosc any one. In general. a priorla depends on ie le\el of abstraction of the

associated object. An abstract object's \ariahle has higher priority than .i ICss, ahtraci objec(s %ariahle.

Sometimes. CIROP should sohe for a specific %ariablc. regidc,,,, of priorities. In ,,uch a situation. the

rule specifiCs which \ariahle should he solved. A typical example is is follos. %here the \ariahle

(tranresistane. second-stage) has the highest prionty. 0

(equation-with-variable-priority(- (transresistance second-stage)

( (current-gain second-stage)(input-resistance third-stage)))

(transresistance second-stage))

The equations used in the phrase grammar rules are similar to ones human designers use. It is natural to

express such equations in the form V = fRA, II, C). where V is an abstract variable, and A. B, and C arc more

concrete variables.2 It is natural to solxe equations in terms of the 'ariable associated with most abstract

object. For instance, the P3 of a darlington pair is the product of the fis of the individual transistors. The

equation 81 = l1 P2 %here ,8 is the darlington's P8 and #I] and /32 are individual transistors' fis is natural:

the equation fl, = 2 2 is not. Empirical results show that using variable priority improves the

performance of the algebra system. Without variable priority the following problem often appears. The 0

algebra system cannot factor the numerator of the following expression and cannot reduce it to "c + d.

ac + ad + bc + hda+b

I A simple form of variable pnonio i used in CTRCOM. a sstem developed for teaching ecctrical circuits in a computational contextb\ Gcr. Sus, man.2 1 he mo(t concruc anablcs are parameters amociaicd wih physical objects. The most abstract variables are spcdfications asociated

vAth the top icvcl absiract object in a design

-Si

0 29

3.6 lutrprting 'hraus Grammar Rules

The creation of i circuit starts with a queuc of one NFW-PART assertion. which descrihes the0

h i~h-Icel hrabstr.ict ohjct to he designed. The procedure for expanding the rules is:

Repeat the follo% ing steps until the queue is empty.

I. Takc the next assertion off the queuc of NFW-'PA'r assertions.

2. Find the niles that match the type in the pattern of the new part. This is doneby simple lookup since the rules are indexed by the lype property.

3. Of the rules found in step 2. eliminate those without the required has properties

mentioned in the NEW-PAR's pattern.

4. From the remaining rules, find the simplest rule that meets the specifications.

5. Expand the rule. Each assertion in the rule-body is sequentially asserted, anddepending on the assertion type, an appropriate action is taken. AnyNEW-PART assertions in the rule's body are added to the end of the queue;this causes the design space to be searched in breadth first order.

For example. when expanding a NEW-PART assertion for a virtual-bjt-transistor "two rules are found

in step 2: one for a single-transistor-bjt and one for a double-darlingon-transistor-bjL The rule names and

their associated patterns are as follows:

Single- trans istor-bjt(where (type virtual-bjt-translstor)

(has (sign ?sign))

(has (simplest 1)))

Double-darlington-transistor-bjt(where (type virtual-bjt-transistor)

(has (sign ?sign))(has (simplest 2)))

In step 3. neither of the rules can be eliminated since they have the same sign has property. In step 4,

the single-transistor-bjt is chosen since it has a lower simplest number. Then in step 5, the chosen rule is 0

expandcd. In this example, the virtual transistor creates a single real transistor.

1 A 1UT Ls a bipolar junction transiaor.

I

34.7 VhIra~v (raiiar Rule FKmpkes

I[le Fodlo" inps ubsections descrihesomne ofClI<OPs 1% pical grammar rules.]

.1.7.1 Ilh.%NiLal I ralniktor Rule

A phi%sicail transistor is at terminal node in tie phrase %truciturc grammar. It corresponds to at real

transistor and hi.i-s properties, such its I.that depend oin the transisior's physical characteristics. 'Ilic tranlsistor

is thc main component in an integrated operational amplifier, since it can bc used for applications othcr than

die nornal transitor application. such ats that of at diodc or resistor. Here is dic grammar rule that describes

.in npn BYI. The rulc includes equations used to model the standard iu.

(to-make-a simple-npn-bjtPattern to match:

I (where (type bjt)(sign npn)

2 (has (simplest 1)))?(equation-withi-variable-pr iority

(~(current (collector)) (* (beta) (current (base))))(current (collector)))(~(beta) npn-beta)

4 ( gm) (0 q/kl (current (collector))))(~(rpi)(/ (beta) (* qtki (curren~t (coilealtor)))))

5 (equation-with-variable-priority(~(ro)(/ 200. (current (collector))))

(ro))6 (- 0 (+ (current (collector)) (current (base)) (current (em-*.tter)))))

.',m!ip-unpn-bII is the rule's name. Line I starts the pattcrn describing the type of object that the rule will

synthesize. Line 2 says that this rule will create the simplest npn BIT. Lines 3 and 5 are examples of a

%ariahlc simplest assertion wrapped around an equation. Line 4 is the familiar relation between the gyn and

the transistor's collector current. Line 6 states the KCI. relation for the transistor's terminals. This rule

includes no NI V-1PAR1'or CONNKTX assertions since it is a primiti% e circuit element.

I I or readahilait. thc notation or the rule%. is modificcd slighti) from the actual rorm used by CIROP. Appendix I contains the correctrorns for allI rules used in CIROP

IN II \ 11 \ I SIO R1I

A\ irttual trmistor i.in~ circuit that .ipprox imaits a pli.\%ical tran~isbor'- hAl' ior. T his ohject 1% 0

"111m111 ml \p.Indcd lilt()ii~I plhN.d~ci ti1~1imo. tile %m11ple~rt~ cv irilt.in-ostor \ Wii a hiplhcr /

I" c0.1Iffed thanl can be pioiiiced b\ a .Nngle na, %isIor imnplemnta~tion. the designer imo choo-,e it) Ilse a

* diIin1-ito paIi \k Inch .,~ another % irttiail tr.inskoi. I his I., compv~ed of t~o ph~sical tranistorN connected I,

Ni'i"' III I iwire 3. The rule Ilimt creates thle darlingion I\:

(to make-a doubile-darlingtofl-transistor-bjt*. Pattern to Match:(where (type virtual-bjt-transistor)

It I (has (sign ?sign)))*New Parts

2 (new-part q1 '(type bjt)(has (sign ?sign))))3 (new-part q2 ((type bjt)(has (sign ?sign))))

Connections4(connect (base)(base q1))(connect (collector)(coliector ql)(Collector q2))(connect (einitter)(ernitter q2))

* (connect (emititer q1) (base q2))Equations governing analysis

(~(rpi) (* 2 (beta q1) (fpi q2)))((ro) (ro q2))

, (beta) ( (et-a q1) (beta q2)))(9mgi) ((/12) (gin q2))))

Lines 2 and 3 assert thc twt) transistors that are used to build thc darlington. Line 4 is an example (if the

(ONA ECI assertion, which connlcts the base of thc darlington to the hase of thc internal transi- Lor q I. ine

5 is tic familiar relation %,here the of a darlingcon pair is thc pro~duct of the internal transistors'pfs.

In Line 1, the symbol ?sign is a variable with thc name sign. Whcn matching the rule's pattcrn against

the asscntions pattern, a value of either npn or pnp should be matched against this variable. Since the body

of the rule is expanded within the environmntt of the pattern match, the value found for ?sign is used

0 throti1chout the rule. I'llus die sign of the darlington is passed to the physical transistors created in lines?2 and -

3.7.3 Three Stage Operational Amnplifier Rule

The following rule is the top level rule used in CIROP to describe the simplest standard way to build an

operational amplifier. It creates the three main stages and the feedback stage for thc operational amplifier.

* The constraint equations pass the input specifications down to these stages.

III1111I IM j*I ON AI*.iIO\A I AMV11 II fR RU I 11-

(to-make-a threei stage-operational-amplifierPattern to match:

jwier:, ( typt! iiiip I ir iv,)(has (input voltage)( input differential)( (output voltage)(output S iigle-ended)(simplest 1)))

Parts are:I ( Now-p artI first-stage

((type amp]lif ier)(has (input differential)(output single-ended)

(inputt vottage)(output current)(sign pnp)fl(use ((gaiin (Im) (slew-rate gim)))

r(new'-part feedliack ((type capacitor)))(new-part second-stage

((type~ amplifier)(has (input single-ended)(output single-ended)

(input current)(output voltage)(sign npn))))(new-part third-stage

((type buffer)(has (input voltage)(output voltage))))Connections to outside are:(2 (connect (t+) (t+ first-stage))(connect (t-) (t- first-stage))(connect (ot) (ot third-.stage))

Internal connections are:3(connect (ot first-stage)(it second-stage)(tl feedback))I(connect (ot second-stage)(it third-stage)(t2 feedback))Propagating specifications to parts:((power-consumption)

((power-consumption first-stage)(power-consumption second-stage)(power-colsiimption third-stage)))

4 (~(slew-rate)(// (max (current (ot first-stage)))(capacitance feedback)))(~(cutoff-frequency)(// (transconductance first-stage)(capacitance feedback)))(~(offset-current) (offset-current first-stage))

5 (~(input-bias-current) (input-bias-current first-stage))(~(input-offset-voltage) (input-offset-voltage first-stage))(~(drive-current)(maximun (current (ot third-stagefll(~(gain) (- (transconductance firSt-stage)(loadiig second-first-stage)

(equation-with-variable-priority(~(transresistance second-stage)

((current-gain second-stage)(input-resistance third-stage)))(transresistance second-stage))

(equation-with-variable-priority6 (~(loading second-first-stage)0

(1(output-resistance first-stage)(+ (output-resistance first-stage)(input-resistance second-stage))))

(loading second-stage first-stage))(equation-with-variable-priority

(-- (load-resistance second-stage)(input-rPsistance third-stage))(load-resistance second-stage))(~(distortion) (distortion third-stage))((voltage-gain third-stage) 1))

Line I s thc NEW-PART assertion for creating the first-stage which will bc a pnip differential pair with

a load. Thc use properties show that the stge has a major affect on the gain and thC slew-ratc. If the resulting

circuit fails and the tradcoff involves one of these specifications. then this part will be a candidate for

replacement Atith an appropriate failurc-c~mtrol-ruic. Line 2 connects the t+ input terminal of the

opcrattonal atmplifter to the t+ input terminal of the first stage differential pair. Line 3 connects the output

icrmtnil of the firs-stagec to the input terminal of the second stage and tI terminal of the feedback stage. Line

Ilk1" I SIi \0~, 0ii1 K \110R \ \I \\t1' 11 11 1i R I I

.4 .xsertN thia the Nic" -r~ac Ii. die quotient of the iainuni current flo~k ing ow of' die firsi-si.ige and Lhc

01 n co die feeCdhac k StIeeU ThIN .INW17ti1 I, k dpen1dent On Ne' er.il im1plicit A'SNUmptions. 1irt dith

r ~-j- IN~ limited h\ dih ciriucn of die Icedhack Nlta-ce\ catcii r h% tlw cuIrrent i.1l.ible hom the first

Ni:' ScLOnd. it IN *xuuIcmd 11h1at1 ),llo the current IloA Ing hiorn the firmr sia~x ia iamLih1C tok li~irgc die

tim10. I ime 5 m~Nia fhc aissumption that thc input hi.vN curren ix dircctl\ depenident on the firt stage. so

(11c .Osllxall IN paxscd (oi111.111'd WI 111C first S1.12C. Linc he ' II~ .iti o t01h. Io)'idip on1 [lhe outlput

cx'O.II c I IN Mh llt t~ id the input reNt.IILCe Of the Seconid SLigC. I he Itladini I,, a I es comnponent -

Of LIhe g.1in relation of die operational amnplifier sincc it acts is ai current di~ ider and decreases thc a'ailablc

gain.

* 4. XAiu/ig hIw Cuit

I 'IcLi1 Iile lr OCict ill: .111 objc~t aS,,CflS c411d11tINs thai re useL'~d it) /k.I -, tile ohe i Ie'.e CqiI.1oIt iNi

st.itc cons.traii hei~eco in ternlil parlinicicr, and extern'l pairameters. I ii t NI ilte rid Ic r huildmL, J

pit\ sical transi,,tor ini.LIt des tihe de\ ice lay~ that relates thle L:Il of thle transistor to tie CuIrrent flim i ILI in t ill th

collector tenifinal. ie hc quations as"sociated with phl Njcal de\ ices represent conimonl\ used I t k)t of nvmork

theor\ Such as K\TI. KCL. and de' ice laws. '11C term "H ierairchicalI Fquations" is used because ihstraci

obhjects can ailso ha\ c cq uations to represent thec bcha\ ior and anialy sis of die object. 1 hus, at hierarchy of

equations exists constraining things from the highest lecic object to the lowest level object. 'Me given

,rcItfical Ions inflUcniceCciit design since they are referencedl in the cquations of thc highest lcNel object.

Iii2h le\el equations grcatly aid the analysis proccss. For C~arrnple. the top le~el rule oif a typical

k~l): IA1t11 'inl aplitict ha,\' the 1011loking list fqaindecbngLamiirsgi.

gain =(transconductance first-sage) dsrhn h mlfe~ an0 (lodingsecond-f irst)0 (ranresstacesecond-stage)

(transresistance second-stage) =(current-gain second-stage.)(input-resistance third-stage)

(loadin' second-first)(Output-rPesance first-stage)

4 (output-resistance firs t-stage *(nput-resistance second-stage)

The variable gain is the name of the specification variable for the operational amplifier's gain. The

equations state that the gain is dependent on the following variables:

(transconductance first-stage)(current-gain second-stage)(output-resistance first-stage)(input-resistance second-stage)(input-resistance third-stage)

High-lexel equations can ignore details that are irrelevant to a variable's solution, if including them

,A uld complicate matters unnecssarily. Note that the operational amplifier's gain is not dependent on the

third sutgces g.aii. %khich is usually close to one and thus affects the overall gain very little. By ignoring the

third paC5g~in. the cailculation ofithe oxerall gain can ignore possibly tedliouscalculations for the gain of the

11111d 01 [t i c he1th'd N(AVC OIC1 hen uincd to he a holIkr siaee \%h L:a n of .ppios ic.IiI\

C\iiolhcr id\.intx~k, oir.tichic.l cquaitions i,, tie Ahilht to V p. IJIltntooI 1OOIiipIeX tO ',01%c bV

1I s\oM\ 1 sOHC (I 11C CqkLJJ1ti11\ of fI\II IIh\1fatonms IROO lIKCe5 DJ C\ IcC1 suIcI .g tif\1LN1 If1i\C

Ii fpi\ equiis noh ing e cyoncntials" to describe tlieii complete bchia'ior. 'ilhe current Mirror depicted

III I LLie relies on s~ rinctr\ to perf'Oni tik. goal opim idi- iiearl\ equa cuirrents n he L1C lice torN. hull

L.afl1Oi0 he 111i11l d "4101 Ithoi P die expoieti Al relotionship (f thle emitter cuirrentit) the base-eitter

ol Luge. I-11.111C\ LIrtu1tel usin ancquatiOn as part or the abstract current mirrors grammar~i rule. ieccuicuont in

the emitters canl be stated to be identical. which pros ides dlie required cons;traint "ile h~passinig the

e.\ponentials.

Hierarchical equations pro\ ide other adiantapes. Analysis rcsults are more easil\ understood sincc the

hih1CC Ci quations pr\iestructurc to Lhanswers. mfnhi ceoe at onlh the KV\I .ind KCL le~ ci.

It olid he difficult to track doA n the reason hehlind a1 particl1r residt.

SI III K k R , III( \ 1 l o tl \ 1 ll0 NS q•

out ' reference

V V1 0

Goal: I = 1out dcerence

Conmplex equations:

qVbe ,

Presoked Result used in Analysis:1 -- 12

Fig. 15. Current Mirror

[he current mirror's behavior is determined b. a complex relationship involving exponentials. HierarchicalcqLllions alloA CIROP to hpass calculations involving exponcntials by using results that have beenprecomputed b. the riter of the rules. 0

4.2 OM 11" %it - ncretiiiial %Igdira Sistein

1 lic M1<AU F- incrementail .ilpehroi s.%stein is, used to NoIl e thle eq uations in tile an.il %si of the LitrcmiIis.

ViiIiti i prese.nted it, tlchucl~hr.i s imone of the tinkiio~t. it .iiahieNI iite etiuation is, sok'ed for

it Ihol ic, ill~. I II \j.Iiuc iind iihtmiiitiou Ahotti the equatlions it depenids on .iie retmiiicd in the ORA('I

'Ii~hae lhe equatioifs asserion retains the naine ttt ihe %.iriahte that ~ s ol'ed I hc ()RACI F is

ner'icnicntial becauise it Is, Pi sn equ.itions, onie at ai time ind sohc s itie equitituu hAsed onb tiu the restilts

sto)red III a database of prec iotisl .ol~cd '\alues.

The algebra sv stemn is at "Iruth Minicilane Systcm 11 )oylel for the sot' ing of algebraic equations. The

algebra .vstcm can selcctively undo the cffccvs of equiations that arc nlo longer considered true while retaining

informattion deri'ed from the equations that are still considered truc. Blecause of this when rebuilding a

-- circuit part. CIROP onEN needs to re-analy,.e the affected equations. The ORACLF- is similar to other

St, stems, suIch as 1:1 ISt~illm-anl & Suissman that uisc propagation of constraints to sot\ e algebra and Use truth

imiten.inicc to retract assertions. It's major dmlnrencc is tat it separaites thc il-gehra and die trUth

maintenance from the system that tises it. T[his pro\ ides a clean interfaice so that implementation issues of

CIROP are not affected by the implementation of the algebra sof~ing ilechanism.

4.2.1 Samnple

hefollowing example demonstrates the capabilities of the ORACLE to solve equations and undo the effects

of equations scc~~l.Te following set of equations are presented to the ORACLE in the order shown.

1. C =A + B12. E =B + 0

*3.G 1)+ F4. H =C + D5.M =D- K

Solve equation 1 for the result' that TC = A + B." Solve equation 2: however, instead of solving the

0 equation "B + C = E", substitute the known value of C from equation 1 so that equation 2 becomes "A +

2B1 = F." The solution of this equation is "B = (E - A)/2." Here is a table of results so far.

* t To demonstrate how ORACLE works. it doc-, not matter which variable vi solved ror. When analyzing circuits, thc variahtc%.otscd for0depend% on thc %3rnahtcs pnontu} In this 021amPle thic %ariablc thai us soh)cd for i underlined.

4 !' \\1II I

I quatiin I:qUaliOn SoIcd \ drldhk-\:lluc

- (: A+ (Ii CA4 I'

" I - II I A - 21 B: (I - A}/2"

I 11 tems 6n the colimin Ltheled (./hmi, ,arc thc original cquhlations. The items in the colunn Libcled

/ ,/.,U: ,,,.ied.re (li cqtheeqtions afiLer suibstituting de \altes of known \ariabl . Ihe iteniw in die I sWhh1 /¢ e

w ,.11u0n aire dic solutions of the equations. The compicic u.hic is as follos:

I k uanit I I-qualsn 'Ai ed \ anabk,- \ ia -'

I C -A I C= A + H C'A + It

2 I = It C != A + 2B 11:11:-A)/21q G = 1)+I = + F G D:1)+ 1:

4 II= C + 1) I + E)/2 + D A:211-2D -EM =D-K M=D-K D:K+ M

Whcne\cr dc ORACLF is asked for a variablcs WLuc. it rcturns an expression that contains no

\driihles \ith a known valuc. Since equation 5 has solcd for the variable I). if one asked for thc \dluc of G.

thC result \ ould be "G : F + K + M." F-ig'e 16 slmo s a1 dcpcndenc\ netw ork ofthe cquations contained in

the aho c table. Thc arrows point from kno" n results to cquations dependent on those results.

J

1 C A + B C:A +B

4//2 E B +C - E =A +2B B B(E -A)/2

3 G D+F - G:D +F

4/44 H C,+D- H (A E)/2 +D - A:2H -2D -E

5 M= D-K - D:K *M

Fig. 16. Algebra ExampleIhis shows the dependencics of the equations sohed.

y ."

6 4.' 1 S\MfI' I 4'1 -

I lie i nereIi l |.'' Coi e %kll. h,11.1 e cqi,1.1ion is, retirawcd. S'uppose that eqtn~ion 2 i i conequIcnLc olfa

mh.d de.",lni l.'.io and is rcil.'d. 0h1\ loul. .th,,t iflect% tle %aL ca..ulated for the \arihvhlc It since

'qdi,, 2 a1is ,Olhed for the.' \ariahl I. It also affect, the \aile of ,,rinhle A CIculated in CquaLntn 4. 0

heh,& Cqitlon 4 ,rs ,ol' cd it ,a, trin,,r1icd ti, ..hs,,it ,iilo that depended in tile restil ot equation

I. %l'tr reti.'tuing equation " \%c pet the t111i inL

I quation IquaiuOn .%Socd \ arahlh- \ aluc I quation-l ruth \ aium- I rulh

I , A + IB ( = A 4 1 C A + H Iruv I rue

2 I2 = 1 + ( I = A 4 211 H" (1 -A)/2 I'a Is Ias3 G = I) .+ I V= I) * G "1) + I Iruc True4 II = C + 1) II = .- I/2 + I) A 211- 21)- L Irue Falke5 M = )- K \ = I)- K ) :K + Miruc True

he ncA column :quatim-Trudi is the truth ahue of the equation. Since eqttion 2 was retracted, its

truth k aluc is false %khilc the other cquations are still true. The ncr column Truth- I'alue is the truth \alue of

the \,tlue solked for with the equation. The value resulting from equation 2 is false: therefore the \aluc 0

!. '1I4iiu..1 from equation 4 is false also. ,lthouih equation 4 is still true. Figure 17 shores the .me equations as

die Figurc 1. with the false information marked %k id large crosses.

1 C A + B C:A B

2 E C E X 2B B-~ B(E - /2

3 G= D +F - G:D + F

4 H C+-D -H-(A X 2 -D A: 2(D.E

5 M= D-K D:-:K +M

Fig. 17. Algebra Fxample-xample showing what ORACLE does when equation 2 is retracted.

* 5..

1440 4' IS\\11i 11 ,1

IquI.il)I1 4 can he rc-solcd for i neA ,alid restilt. [Me ordering in the I-lh, ing i.ihl renLI [tle' Iiklc"

that equttion 5 has .lread. been . I\Ad I hen equation 4 is rc-. s ed.

I ,wL.1,14-1 I qujm in .Sohed 1.r-1,-~ d I !': -hl I it~th \111% 11 111

4 k *II - \ (It I I rut: ruc

I It C I - A + I It 11 -Al/2 I .'w kIa-l

4, - I) - I I = I1) + I ( I1) I liu IruC

\ )k N = )i K f \ Irit Iruc4 II l - I) II t * - k M Ai i ll-t 'K-I Ia I nic

Note thc substitution for It is not made and It is not considered to hae a kno i n ,tue.

4.2.2 Equation Solving

Thc heart of the ORACI.s IS a data-basc which keeps track of the analysis results. Fach entr\ in the

ORACLE da|a-basc is a collection of four properties associated %kith the solution of a \ariablc's value and 0

indexed hb\ the xariahle', nAmc. The four properties are the ('LIRR[NI-\ \ILUE. TRUll!-V\I.1F.

REASONS. and ('ONSFQUEN(TS. The (URRINI-\ \ILI is the last \aluc calculated for this variabhle.

he TRUJiJ-\ ,\LJUY is IN if tie current \Aiue is \alid, and OUT if the %ariahlc's value has been retractcd

since it was last solked for. REASONS is the list of equations used to calculate the \ariablc's value. The first

reason in tie list is the name of the assertion that directly caused this variable to be sohed for. The other

reasons represent the dependency of the current ,alue on other variables solhed before this variable.

('ONSFQUENCES is a list of assertions that used the current \alue of the variable when solving their

equation.

CIROP maintains its own dau-base of assertions which includes the equation assertions. Properties of

in equation assertion are equation and the name of the sohcd variable. The assertions used in the

pre\ ious example are as follows:

ASSERTIONI : c =a+bASSERTION2: e = b + cASSERTION3: g = d + fASSERTION4: h = c + dASSFRTION5: m = d- k

After solving these equ.itions the data base is as follows:

4 itI \il\S)I \Vj 41 0

ii.hk \J)L"%211w .|lui. I rulth Rin'.'l:, ( OIINqi4. 'q,*,. .

( t IN (SSFRI ION I) (\SSI KI IO\4 RI H I I0\)"

I I1/2- A/ I\ t\SSIR I ION2 ASSI.R I ION I) (ASSI'R I IO\4

G 1) - I IN t\SSIFR ION 3) None .

."-?) I IN \SSI II\4 \SSIR I IO\ XSI RI 1OI None

II h - \ I\ .\SSIR I 10\ S None

The most interesting onrs is the second cntrr. lhienlr% reprcenis he ,olutiton of the equation

% ith ASSFRTION2 A hich %,as solhed for tie \,r.ihll II. Ihc aiLic fouind wr,, (12 - A/ 2). lhie

,sohILit10 depended on ASS'RTION1 and ASSFRTION2. '1ic solution of tie equauion associ.tied %kith

ASSI.R 110\4 dcpcnded on this valuc (if B. After equation 2 is retracted and equation 4 is rc-solhcd the

daLa-base looks like this:

xn.abl-\anc \aluc 1 ruth Reasons Conscqucnces

C A + It IN (%SSPRIIONiI (ASS!FRIION4 ASSFRI.HON2)

II I2 - A/2 OLT (ASSI:R'I ION2 ASSIRIIONID (ASSFRUION4I

G I) + I IN (ASSIRIION None•1 It - K - \1 IN ,\SSI.RIIO\4 ASSFR 0IIO\V .SSFR IONl None

I) K -M .I IN (ASSI-RIIONS) (ASSI:RIION4)

4.3 Procedure used in ORACLE system

The general procedure of the algebra system is as follows:

Gi'en a queue of assertions representing equations and a data-base of known variables, repeat the following

steps until the queue is empty.

I. lake the first assertion off the queue and call it A. If the truth alue of assertionA is IN. get the F'QUATION propcrt of assertion A to be used in thefollowing steps. If the truth value of assenion A is OUT. ignore steps 2 and 3.

2. Until every variable in the equation is unknown, substitute the value of the firstvariable with a known value. For each substituted variable, remember thename of assertion A on the consequence list of that variable. Also, get the •name of the first reason associated with each substituted variable.

3. Solve the resulting equation in terms of one of the unknown variables V. Enterthis solution into the ORACI.E database as the value of the variable V. Set thetruth value of the entry in the ORACILE data-base to IN. Add the name of the 0

assertion A to the front of the list of reasons collected in the last step and enter

.0

4 I'Ml I it I tM R I l)lD \ MACII SISI I. 4? •

Ih,itI new list its the iso Ill pioprt% Iir \aariahlc I in Ile OIR..CI.I- daiha-bas.Remember the iame oI* the \ariable N as the Soh cd- arialhlv propei-t% tin theassertion A.

4.4 (IR(OI1

Ic hcart of the algebra system is ia simple equation soter. w ritten h G. 'Sussman i% parl of his

C IRONI system. diat does simple substitution and simplification. To solae eqlalions. it choo'ses a ariblc

to solac for. and then tries to isolate that \ariablc. Fxpressions are reduced to a rational forni which is a ratio

of tAo rMlaticl% prime multiariatc polh nomials. The mathematical operators used are the basic arithmetic

operators: add, subtract. multiply. and di\ ide. The rational form is complete in that any two expressions that

arc equal hac the same rational form.

,4.4.1 Retracting Equations

1o use the ORACI.: ,Igebra systcm in a non-detemlinistic s\stem. it must be able to undo the affects of

in\alidted Cquations. The system keeps track of the consequences for each \ariable. Here is the procedure

for retracting an equation.

'1o retract equation F with associated assertion A. do the following.

1. If this is the original assertion to be retracted. set the truth value of the assertionto OUT: otherwise, add the assertion to a queue to be re-solved after thisprocedure is finished.

2. Get the name of the \ariable V that was solhed for when the equation was 0originally solved. This is the Sohed-\ ariable property on the assertion A.

3. Find the entry associated with the variable V in the ORACLE. Set the truthvalue of this entry to OUT.

4. Get the list of consequences in the entry. This is a list of assertions representing

other equations which depend on the now obsolete value of variable V.

A

* 0

* 0 ,-"

* .J4 I1 kII IN AI \CAI-QL,%I\S 4j

.5. I-or cach assertionl on this li exco~~qLc~ L%. cik the eimi c pitkedtllc

from die ,wr 1. *1 his procev, e ccntuajll' terrmia.es snce ill pf~h eriinle xiksome wiihl A ith no conlsequncelCs. U~Cosquenfces can onh point to

PC cquion m'i~ %e~~re so1hed Atfer dicmsc1hes. thcirc can he no ciicuhir pahs.

W\hen thmk pi-mcdure is finishced. it produces a queuec of' %alid equations that must he imc-sohe d. li h

110o1111 altuatm iii k ing pr K~cdirc is in% oked oil thi% queuec.

i t t)\ I Rol I IVJ 111 I 14 ,\ PISXX':5

L. 5. Controlling (lie Design Process

.n engincer use strategic knowledge to control the design process. CIROP minics the hum.in

%imuinecr h\ tsine stralcnc knoledgc in im v pliases of tile design proce%N. Stategic klno ledge gpides tie

design of the initial prototy pe. If the prototypC fails to meet its spectilications. strategic knowledge suggests

alternaiti\e ,tys to impro\c the circuit.

5.1 Guiding the Prototype

The experienced engineer uses learned heuristics to guide the prototype design of a circuit. Usuall

more than one rule exists that can be used to expand an abstract object. 1he learned heuristics are used to

select an appropriate rule from the possibilities to expand the object. The primary heuristic is to keep the

design as simple as possible. In some situations the simplest design may be obviousl. inadequate. The

reasons for preferring one sutge over others are usually based on tradeoffs due to the given specifications. 0

5.1.1 Sintplst First

The writer of the rules can include a subjective measure of the rules complexity. This measure is

distilled to a number by the writer, where a lower number represents a simpler object. When expanding an

object the applicable rules are sorted based on this measure. simplest ones first. In practice, this measure can

be used to state a preference for using one rule over another regardless of their relative complexities.

5.1.2 Tradeoffs

No design exists for an all-purpose operational amplifier. Man different operational amplifiers exist to

ser\c varying requirements. t- ,ch operational amplifier is thus designed with finite values for the important

specifications appropriate to the need for the amplifier. The differences between operational amplifiers are

based on tradeoffs between specifications. For instance, if input bias current is a high priority while the

slew-rate is not. that amplifier's design differs from an amplifier requiring a high slew-rate. This tradeoff 0

between the input bias current and the slew-rate of an operational amplifier results in different operational

amplifiers, each depending on their requirements.

TradcofTs can sometimes he expressed as simple equations. "l'hcsc equations arc approximate models of

tlw' heha\ ior of the I\ pe of object that one is buiilding aid cain he traced t) the more dctailed equiat tnN thai

descrihe die circuit accuratcl\. For instance. a front-end differential pair has i importaint tradcoft hetI en

0.111 '1nd the inpuLt bias Current. lDetiled anahsis shims a direct tradcotT bet\%ccn die gain and input bias 0

.urrcilt. because the gain depends on thle gin oif die transistors. Allich depends oin the collector current. 'Ahich

depends onl die base cuirrent. \%hich is the input bias current.

Ibhis I\ pe ol dependence is \.dlid for all] norimal x'arietics of differential pairs thait uise bipolir transistors.0

except Ibr the current cancellation stagc. 1 'I'lis one can dc'cbop a feel for this tradeoff which dictermnices

'%hich object in it set of front cnd stageS Might he appropriate. Tlhese tradeoffs can he uised whcn using a

differential pair to decide immcdiately whether it is worthwhile before expanding it. If the tradeoff is not0

met. the work of expanding an obv'iously inadequate circuit has been saved.

One should realize that these constraints are only heuristics, and an applicable constraint may not exist

ao t each lcecl. For instance, the -second stage of an operational amplifier will have little direct effect on the 0

inputI biIs Current in a Aell-desigriccl amplifier. lIbcrcfore. the second stage mould not use a heuristic to

constrain itsclf on the First pass of thc design process.

0Another problem is that of breaking down constraints. The gain of the entire operational amplifier

depends on the product of the gain of the first and second stages. Since one does not know the gain of either

stage. it seems hard to pass along a reasonable constraint to the lower stage. A constraint could be passed to

the first stage that contained the second stage's contribution o the gain symbolically. Then the first stage0

would further constrain the second stage gain. When the second stage is created it checks to see if the gain is

reasonable. At thispoint. it is unclear which stage should be replaced. How does CIROP know which stage is

0 at fault if the gain is not met?

Another method notices that the gain will be shared between the first and second stage nearly equally.

An approximate constraint can be passed to each stage, which is the square root of the total gain. Then the

first stage has real numbers for gain and bias current. Using this, CIROP can check to see if the first stage is

reasonable. If the first stage is not reasonable, CIROP goes to the next appropriate rule for building the first

1 The current canccitluon sayc purposcl breaks thc direct connection betAween thc gain and the input bias current.

I Di)I Of lIS

n, nul S.i uut Occurs hefore the circuit is coinpletel. desi,.gned na, be fault\ since it is hased on

.t\,,ltllf~ ~l'ti l \, o hat the undesignled p.,rt, ' ill do. It i, reasonable it) asIIni, that die allals. . A hile possih

folt., is nc,irl correct. Nt thi, phais oI the design it is Important tiat no po sible solutions hc eliminated

hCoc hnne gi\en a t'air chancc. I-ault% ,nalsis could eliminate good solutions. hile alloting bad solutinS

lo he tried. This na\ oc.'cur hecause certain heuristic constraints model the hehaMor too exactly. Ibis

problem is .ohed by ensuring that heuristic constraints alwa's, u.se optimistic models of the beha\ior. thus

erring on one side only. The heuristics may allow bad soluLtions to be tried. v ithout eliminating good

solutions. For instance. using the gain example. the first stage gain is checked, assuming the second stage can

pro\ ide an optimistic amount of gain. Any doubts about the second stage contributing enough gain are well

fo unded, since the first stage is assumed to provide as much gain as possible.

The affect of the specifications on the design is illustrated in Figure 18. As the gain/bias-current 0

tradcoff increases. it is more difficult to sditisf. for a gi.cn circuit. With a low tradeoff. any circuit, that

CIROP can synthesize will satisR the tradeoff. As the tradeoff increases, fewer circuits can satisfy the

tradeoff, undl no circuits can satisfy the tradeoff. Note: the number of possible circuits does not fall exactly to

one before hitting zero. B~en when the tradeoff is very difficult to mecL there are several options. For

instance, the biasing of the olitput stage will have little effect on the gain. Therefore. several operational

amplifiers can be built using different biasing on the output stage, although the) arc identical otherwise and

barely meet the tradeoff.

S

I I? ik\i)iOiiS 47

!

32NumberofPossibleCircuits

1 "0

Gain / Bias current Tradeoff increasingdifficulty

Fig. 18. Tradeoff of Specificationslhe number of possible circuits that CIROP might design decrease as a tradeofT becomes more difficult tosatisfy.

5.2 .%nal.sis and Testing

CIROP uses the ORACLE to solve the equation assertions made during the creation of the circuiL

During analysis, the ORACLE finds values for most of the variables. The top level specifications are

compared " ith the specifications of the proposed circuit. Since some of the specifications are interdependent.

thc cannot be checked individually. The ORACLE can be queried for the circuit's value of a specification.

If the \aluC is a number, it can be compared direct) with the goal specification. If the value is an arithmetic

expression, it depends on one or more of the other specifications. One by one. the other goat specifications

are asserted as necessary until the arithmetic expression becomes a number. The resulting temporary

asseruons are retracted as soon as a numeric value is found for the original specification. For example. after a

simple operational amplifier is created, the gain and bias current have the following values.

.S

"\ \1 Si \\1D [III1\6 48

GAIN = -2.99 1 128CI O I)-RI-SIS IANCF-('t IC RIN'I (H.\SI: (Q (IOS-Q (FIRSI -SI AGI- OP-AMP))))

lI \S-CL RRFN ( -1. (CLIRRIlN I (IMASI (Q (IWOS-Q (FIRS I -S I AG Ol-,\NI)))))))

I o check the gain specification. Ac must knoA the \alucs of the \ariables I OAI)-RESIS'IANCF and

(CL RRIFNI (HASE (Q (POS-Q (FIRST-S'IAGE OP-AMP))))). The \ariablc I.OAI)-RI-.SISiANCE is a "spcc:iication and the \ariable (CURRtNI A(\SI: (Q (POS-Q (tIRST-SIAGE OP-AMP))))) depends on the

hia current specification. The gain can be found by asserting \alues for the unknown specifications as

follows: 0

assert LOAD-RESISTANCE - 2000.assert (BIAS-CURRENT OP-AMP) - 2.0e-7

the new values.(CURRENT (BASE (0 (POS-Q (FIRST-STAGE OP-AMP))))) - 2.0e-7 0GAIN 11996.

lhe circuit gain has been reduced to a numeric 'alue and can be compared against the goal specification

tr the gain. Fach specification is checked in this manner.

5.3 F-ailure Rules

A designer's response to failure depends on his experience. An experienced designer has learned

characteristic ways that circuits fail, and methods for improving circuits which do not work for well defined

reasons. An inexperienced designer analyzes in detail, hoping to find the error. Paradoxically, it is easier to

mimic the experienced designer than the inexperienced. Detailed error analysis of a circuit requires complex

qaalitai c thinking. %hich is not formaliied well enough to use in a program. Een human designers find it S

difficult to anal)ze circuits in detail and often resort to approximate models.

CIROP's failure control rules embody the strategic knowledge used by experienced designers to

improve circuits. A failure control rule has a pattern of applicability that specifies which phrase rule failed,

and Ahich specifications were not satisfied. The body of the control rule directs the interpreter to try other

phrase rules based on the knowledge embedded in the control rule. The following example shows the

knowledge that indicates that if the gain and bias current cannot be met with a simple-differential-pair, the

EI \1 L l k

diltercit aI poir s1wuld he redesignecd iisa crct-aclnmapii

( in-case-of-failure-ofIs p nle-d irferent ia I-pa ir((gain gm)(bias-current gi))(try curret-cancel lat ioni-amplifier))

1 h lcrclr3osbhn hsrl r ilie nScin. .

;.4 Iacktrackin- i~iti l-ailure Rules

lidt.,ektrIei OccuLH s IChen.a specificat un Is not met. A list of equation &sN, rior., wkhich VAI L1Crc [ 0 o

(11' thNpe11fication's \~alue is contained in the OR ACIF. From these equation1S. Cl ROIP find, the

ohlcct, Lhat assertedl them. CIROP also finds thc supcriors of each object. Thecse objects represent the

* possible parts of the circuit that may, need redesigning. For each part. CIROP finds the applicable failure

control rules associated wAith the deficient spec ificat ions. [he use propert\ of the part is also compared \kith

the tailed specifications. From these a list of applicable failure rules is isolated. [his process oif finding

applicable failuire niles is repeated onl each parn that was found.

CIROP randomly chooses a failure ile from the applicable rules. The offending part.that thc failure

..ontvo! rule matched is rewokcd. and all the assertions dependent on that part are remo'ed. .Ank objects that

"ere -reated b' the offending part are also remov ed from the circuit. The phrase grammar rule suggested by

die fillUre rule is, used to rebuild the part. If the part is not a terminal object, its internals are built by the

orici, ITIA procedure for creating objects.

(7 5.5The Knois lcdge used to Deielop Failure Rules

[Ihe following subsections describe some of the kno~ edge that one must distill to create the failure

rules.

5.5.1 lmiproiing the Common Emitter's Current Gain

-1 lie second stage of an operational amplifier often uses a common emitter amplifier for cu~rrent gain.

lILH 19 ,hOA,, the difference bet~ken implementing a \irtual transistor as a single transistor and ats a

darlincton pair. The currenit gain for the single transistor is onl) ft. while the current gain for thecdarlington is

13 l.!sd on simplit\ the single transistor is preferable. ho~e' or. if it does not1 supply enough gain, it can

* he replaced \Ath a dlarlington pair. Therefore, one can derive the failure rule described in Section 5.3.

4 ~ 'M II(Ot\ I \u 1111 1 IW IRS I \(iI I I\\St O\IDt ('I A \(I

Load La

OUTi OUT2 0

1IN1 N

I 0

Single Transistor Darlington Pair

'outl /3 'l*ol27 2 lin2

Fig. 19. Current Gain in Common Emitter TransistorCurrent Gain in a Common Emitter Amplifier can be increased by increasing thc e

5.5.2 Improving the First Stage Transcondut]10nce

The transconductancc of an operational amplifier's first stage' 'is usually dcpe-dcnt on thc quiescent

j Collector current as shown in Figure 20.

The transconductancc can bc increased by increasing the collector current. Unfortunately, this also increases

dic inputL bias Current. To increase the collector current without increasing the input bias Curren the

cffeccu~e P3 can be increased. or thc topology can be changed to brcak the direct dcpendcnce of thc collector

current on the input bias current.2

* Following are some ways thc input bias current can be lowered.

I This discussion assumes that thc operational amplifier's firs szagc i% a bipolar difrcrcntia pair.2 '1 h,s is not meant to be an cxhaustse cIisting of methods to increase thc transeonduetance.

* 3 L nlc., sp9i~icai> stated. thc discussion of topologies assumes the first stage is a bipolar transistor emnitter coupled par (a differentialpair).

00

I\It R(o\ IM , I III IRS I S I A6 I fRA\S('O\I)t '( \\(I 5

vcc

C I C

c--- (--- O

Q QIbias Ibias

-VEE

Ic = ' biasq Ygin = kkT

Fig. 20. Input Bias Current ExampleSimplc l)iffcrcntial Pair for the first stage of an opcrational amplificr, showing relation between input biascurrent, the quiescent collector current and the transconductance.

Since the base current is directly proportional to the collector current by the factor 1/P of the transistor.

the input bias current is lowered most easily by lowering the quiescent collector current of the input

transistors. This mcthod A crks as long as the collector current is not too low for other specifications to be

met. For instance, a low collector current can lower the frequency response. The overall gain of an 0

operational amplifier has the gm of the first stage as a major contribution, but this is directly proportional to

the collector current in the first stage.

0Another method of lowering the input bias current is to increase the effective/f of the first stage input

0

11' I\tt)\ I f lilt I IRSI S AGI I H ,%S( ( 'l\)t (iA,(I 53 0

ti.m,,Nors. I his pe,,iits a lower base current for an equail'et * collector current. The ,3 can he incre.ised b.

,M' 'nLpcr-bct, trnsistors. A super-heta transistor has i \cr\ narroA hse region \Ahich impro\cs its base

H +,~ rt flictor and it,, emmer efficienc.\. 'Ibis increases te ,P b) as much a, a [actor often. The narro\ base -

ri. so .ko ctmue thc tr,nsistor to hJ\c a \cr\ Io\ brcakdoh n \ollage across this region. All the transistors in

the opcri.ionil implifier circuit cannot he super-beuts. because the circuit Aould not ',ithstand the required

operating \oltages. Ilierefore, the super-beta transistor must be used in a confiPturation that prc\ents it from

seeing large \0luiges across its terminals.

Vg+

0 out

V0g - - -a ou

Q - Q

Super-Beta Devices -•

)' 12 (Greaterthanll)

3 4

NS

V"Fig. 21. Sup'r-cta I)iffcntial PairSuper-beta transistors arc uscd in the diffrntial pair to increase the Pi of the first stage. This car decrease

the Input Bias Current while keeping the stage's gm constant.

* f.? I\II'RO~\( Jil [IRS] SIAGIRkA\S('O\I)L:CIANt[ 54 ]

Ini the detailed example of a super-beta circuit in Figure 21, the elements )1. 1)2. Q1 and Q3 form a

loop. llerefore. KVI. forces Ql's collector to emitter voltage to be approximatel the \oltage drop across one.

of the diode. Since this aerages six-tenths of a VolL the \olUig across the input transistor is kept at a small

L0lls.1ft1. Stipcr-hel.I transistor Q2 is protected in the same wa.. Also. two back-to-back parallel diodes

connect the tw4o inpuLs to protect the transistors from large input voltage differences.1

RC v Rc

_______Output

IC IC~

'bias Ibias

EE

Fig. 22. )arlington Differenti2' PairDarlington transistors can be used in the differential pair to increase the , similar to the super-betatransistors.

1 Ihe diodcs arc not shown to preserve clarity.

* S

I * .. | .-

0 0

I\II'RO\ I\ . III I I II Il i I K \\S(LO\I)L('IA\'CI.

Another wa\ of increasing die e ,ctke P ol dhe first st.,e input transistors is to use darlingion pairs

in,,ted of ,,inle tranoitors, as shown in liure 22. A d.irlington pfir consist,, of t least tk trn i sors

0c,'nil\, tcd so as 1o approximaiC J single transistor %kith a ,P approxirnatel.% the product Of the indk~idual ,P's.

I h'",. dArlinotons lha\c disad'antaes. [he hawc more circ uit components ini the signal path of th 11iNi

q,,c'-. ' hich Can increase the first stage's asymner. drilf. and noise.

*0

*0

a 0

* 0

S1)11I I~i \III) 0i OXPI lii MON \1\V 11 \A\1111 I 5

6. Detatiled Operational Amplifier Example

Illis chapter rc' kits thc design example of Chi I) er 2. detiI ing ClI ROP\'si~ decisions.

6.11 Detailed Sce~nario]

1[le iniii al is Io build an operationial amplifier A ith die following NFAV-IART assertion and0

spcC I heat it Ils.

(new-part op-amp((type op-amp amplifier)(has op-amp (input voltage))(has op-amp (output voltage))(has op-amp (inout dirfferential))(has op-amp (output single-ended))))

gain 500000.*input-offisct-currenit 10 nanoamps

*slew-ratc 0.2 volts per micro-secondotiplt-drk C-current 15 ilfliainpsuinit\ -2.Iii-frcqucncy 3 Mecgahertzoutpt-load-rcsistancc 2 kohms

(input-bias-curreni 0.2 microamps

The first actiorn is to find the nikes that match this NFW*PART assertion. [:or such a high lc~cl object.

different niles would probabl\ describe maiijor diflercnccs in thc strategy if designing the circuit. For instance.

*the nilc used might describe the most common operational amplifier strategy % ith three stages, while others

might dcscribc four stage opcrational amplifiers. The standard rule for crcating an operational amplifier is as

describcd in section 3.7.3. T'he following concepts arc implicit in thc rule definition: The first stage will

con\ crt thc diffcrential input to singlc-ended. 'Mc middle stage will provide an\ necessary gain that the first

staige cannot suppl\. The third stage will buffer the output. The feedback stage will be used to make the

operational amplifier stable aIt frequencies of interest.

The restult of the top le~el rule is to add, four NI W~-PART assertions to the queue. connect these new

parts to the abstract operational amplifier, and create several constraints between the objects. The original

NEW-PA WI assertion that created the top-level object has been removed from the queue.

The ne'% first assertion on die queueC is the assertion for the first stage of the operational amplifier as

h I I11 1 I.\ll I W I 1 \ARIO5

follosks:

(new-part first-stage[i ((type first-stage amplifier)(has (input differential))(has (output single-ended))

(has (input voltage))(has (output curret))

(has (sign pnp)))

((use . ((gain gm) (slew-rate gm)))(with-specs

(= (transconductance (first-stage))(sqrt (* 2 (gain)))))))

Shi, m.lch, the pattern of the follo~king niles: simple-differential-pair. current-cancellation-pair. and

super-beta-differential-pair.1 Since the simplest of these niles is the simple-differential-pair it is checked

first. '1 he ,implc-difTerential pair has a wiIh-spcc.' constraint that relates the transconductance to the gain.This constraint is temporarily asserted and the spccifications arc chcckcd to sec if thcy could be met with this

constraint. Since thc constraint is satisfied the proposed simple-differcntial-pair first stage is adequate for

no%.

The assertions in the ,,imple-differeitial-pair's body arc asserted. which adds more parts to the end of

the queue and more constraints arc created. The assertion used to create de first-stage is rcmo ed from the

queue.

The new first assertion on the queue is the top-level rule's NEW-PART assertion for the second stage as

follows:

(new-part second-stage

((type amplifier)(has (input single-ended))(has (output single-ended))(has (input current))(has (output voltage))(has (sign npn)))

((with-specs

(, (transresistance (second-stage ?op-amp))(sqrt (0 2 (gain ?op-amp)))))))

The onh rule that matches this is a common-emitter amplifier. The common-emitter amplifier is then

checked to see if it meets the specifications. The rest of the second stage and the third stage are designed in

similar ways. The next few paragraphs concentrate on the design of the first stage down to the level of

physical transistors.

After building some of the rest of the circuit, it will eventually get to the NEW-PART assertions that

1. The rule s for part% arc all in Appcndix I.

*'

I i I 11 I )Nt I V\RIO ,

\Aerc created h\ the simple-dilerencialI-pair nile. ' lie first such assertion is ie fidlo' ing:

(new-part matched((type matched-pair) S(has (sign ?sign))))

\ m.itched p,,ir is a pair ol tansistors that ha\e bec| carefully manufactured so tha thcir ph).sical properties

are nea rl\ identical. Using a matchcd pair for the two transistors in the emitter coupled portion of a

diflerencial pair impromes the s.mmetry of the slIge. lie implementation ofthc matched pair transistors is a

pair of pnp bipolar junction transistors.

The rest of the circuit is designed in the same manner. The complete probot)pe is analy/ed and

compared to the specifications. At this point in the design, the gain and input bias current are the following:

GAIN (S -2.9990628e7I OAI)-RI-SISTANCE(CURREN'I (BASE (Q (POS-Q (FI RSI-STAG E O1-A MP))))))

INPUT-IBIAS-CURIWNT =(* -I. (CURRENT (BASE (Q (POS-Q (FIRST-STAGE OP-AM P))))))

Gi\ :n the specified input-bias-current and load-resistance, the maximum gain will he 12000. This does

not meet the specification. CIROP must backtrack by redesigning some pan of the circuit. 0

The calculation of the circuit's gain is dependent on fort. -three of the total constraints asserted. The

parts that created these constraints arc found. Only three of these parts have a gain use property and also have

appropriate failure rules for improving the gain. These three parts are the first stage, the first stage matched

pair. and the second stage transistor. To improve the gain. one of these options must be rebuilt. The first

chOLC is to rcplace the second stige's single transistor with a darlington pair. Associated with the second

stac's transistor is the follo" ing failure rule: S

(in-case-of-failure-ofsingle-transistor-bjt

((gain beta))(try double-darlington-translstor-bjt))

The virtual transistor used in the second stage is removed from the circuiL This also removes the

ph)sicad npn transistor that was the only part of the virtual transistor. Removing the parts invalidates any

constraint equations that the. had asserted. As a result, only a few other equations must be re-sohed, those

that used the \alues doricd from the now imalidated equations. Alter this. the failure-rule is in.oked to

i "

6 I 1)1 \II 1)IS( I \IO)"

dcicimiii houk the %iriti,tI tanmi%tor -Al ie rebhuiit. In thk ctw. it A iII create at dai uiitoi paor insicad (if' i

oingle trin,%to(r. ieh impi m' d circuit is amnly/ed and noA mects the spcci tic.itio lis.Io re-.11\/ c tile

:ic~ uti. mflix tie neoi cowulntr~)I sseried h ie nok parts must he solsed.

- - .-. . t . .

I1 \11 I) \\ORk "9 0

7. IclalctLBork

( .1 El. S

'TI i rule-based ,,stem for compuITr-aided circuit anJ).sis IStllmin]. (iien a circuit description.

T dcetcrmines the suitc of the acti'c elements and the %alues of the %olhage potentials and currents at all

nodes and branches of the circuit. El. uses lrupagariiii of' consrainis and dcpewnAncj-direciclI b, wk rack ng to S

control the analysis. Since it is an analysis program, it does not need to understand the creation of topologies.

SIt is giien a fixed topology.

El- reprcscnts circuit specific knowledge as assertions in a rclational data base. ]'he general know,.ledge

about circuits is represented by "LAWS". which arc demons subject to pattcrn directed invocation. A new

assertion into the data base triggers matching demons. Triggered laws arc put onto a queue alone with

information that tells what part of the circuit they will operate on. The demons are executed when taken off S

the qtLcuc. [xecuting a demon has one of two useful actions: it either makes a nc assertion into the data

hase. %hich may restart the whole process by matching more dcmons. or it may discoxer a contradiction.

I. makes assumptions about the suites of the active devices. Since these assumptions are originally

geLiCsC. the. are frequently wrong. If an assumption is wrong a contradiction wkill arise, which is a set of

assertions Ahich can not all be true at the same time. When a contradiction is discovered. El. invokes a

method called dependcnc-directed backtracking. This automatic procedure removes one of the assumptions 0

associated with the contradiction. and tries another assumption. This leads to more effective control of

combinatorial search than undoing the last assumption which was made.

SFl. needs backr, -king since it makes guesses about the transistor's states. CIROP needs backtracking

since it makes guesses about how to refine abstract circuit objects. A combination of the use property and the

failure control rules are used to determine which assumption must be undone when CIROP finds a

contradiction (a failure to meet specifications). The failure rule also tells which option should replace the 0

faulty guess.

CIROP's ability to solve algebraic equations provides the same function as propagation of constraints.

Prpaguton of cotitraimts can be viewed as a system that solcs equations by al~ays solving the equations

Ith the feu'l Llnknowns. This im pose , i11n order on dhe eqtialtlons l 1o b.o\ ed. CI RO(OII in tIore 2eIle , l thtbn

Ut. incc it doe% not require the equatlions to bc solk ed in a particular order.

7.2 SIN

SYN [deKleer-3] shows that /Piglal ion of'con.trlails is usefil in s. nthesis. .s Acll is analysis of

electrical circuits. I'1 as sumes the componenlt alues are known and calculates the %Oltges and cmi-rlis of

inteiest. SY N shows that the calculations can go in the other direction: gi en CInOutgh constraints about

tluitges and currents, one can solbc fiar the component Nalues. Bk stating goals such is gain or particular

currents and Wolutgcs. SYN synthesies the circuit b finding the %alues for the components. For example, in

Figure 23, Ft. can solve for the current 11. gi'en the %oltage and the resistor %alues. SYN does that. plus

solhcs tor resistor %alues. Pi\en the desired currents and voltages.

+ R- 1 2

Fig. 23. FAample for H. and SYNft ~I n soix e for the url iiit,, laheled l1 ,rnd 12 gi en the 'attics of R1. R2. and V. SYN can also sohe for R 1

.ind R , gicn \alucs f(vr II[ I. and \.

To, mnidge the corplexitics of snthesizing a circuit, an engineer simplifies the problem by constructing

\.Far. Ic models of the circuit. kich model describes some aspect of the circuit's behavior. Each model is a

rie:, circult that can be more easily analfed then the original, although any one by itself does not model the

,mplctc behi ior of the circuit. SYN creates separate models similar to that used by a human engineer. For

in, tnce. each transistor can be modeled with a bias model or an incremental model as shown in Figure 24.

'IS) \ o2

4C

E-E E

Symbol Bias Model Hyprid Pi Model

Fig. 24. Transistor models used in SYNSYN simplifies analysis b using different models of devices for different regions of operation.

Although having different models simplifies the algebra required to s\nthcsi/c a ei\cn circuit. SYN is

still limited b) alg hra when thc circuit is large. The circuit in Figurc 25 is the largcst circuit SYN successfull

synthesized.

I SI

4 0 -

Vcc

Out

I N

Fig. 25. Cascode Circuit S.nthesized by SYNOne of the largest circuits sucecsfully synthesized by SYN. S

7.3 A Simple Model of Circuit Design

Rolancc's Mastcr's thesis [Roylancc80 is one of the first attempts to creatively design circuits. His

,vstmcr models fundamental rules about capacitors, resistors, operational amplifiers, feedback and network

Lmks. lhesc rules describe the dcv ice's causal bcha'ior. The causal behavior of devices suggests strategies for

using them in design. Starting with a goal, the rules are used to decide what components to use and how to

connect them. The system has no memorized circuit fragments (combinations of more than one primitive

device), because it builds them dynamically.

Since the system builds the circuit from basic components, it is not limited in the topologies it uses. It

has the potential of creating and designing new topologies to solve a problem. Unfortunately, it cannot take

adantage of topologies that are already known to solve specific problems. This approach may be limited in

the problems it can solhc until a large portion of general circuit knowledge is incorporated as rules. For

* ~ ~ "\ NIIPI I IOIl 1 01 IR( LII D)1 SRA ~4.

c \.imiple. ti ',.pp i .ich might 11,1\ [1Ii hC deNigninW .1 L0111plextirreni1irito!. ,\lihioih liIc 0iiriciti Mirrmr

1 20r 1", "liple to tndersiAnd. it is diIth'li o1 iiai.gic tite kntm~leduc needed to s\nithc',iie it the first

cv Lmmc. CI ROF c.iit u,,e the mirror ,mncc it ueed not kiiox. the oriciN~ od the cirCuit1 frdinent to use it effecti~el

id iccd no 1 nt h c~i/ it from pri I Li\ C elcmen is.

4/ reference l1 out

Fig. 26. Current MirrorCurrent Mirror that is hard to design from basic principles.

A go)od circuit design svstem will need the concepts dc~eloped in Roylances work as well as the

concepts used in CIRCE'. Using 0nl3 CIROP. onc could nc~cr design completely ncA circuits. but using only

Ro\ lince's svstem one must constantly re-invent the wheel. Often a new circuit may be a new twist to an old

circuit. CIROP could design the "old circuit" as a first approximation. A system similar to Roylane's that

could understand hoA the circuit worked and why it failed, Could provide the necessary "twist" to improve

the circuit to mcet the specifications. In this situation CIROP acts as a smart library of circuit fragments with

-- -- - -- -- -

I Ic k I Io% lcd2c to cornpose colIiip lCte C II cut rpotot% pes fron I the frigiiients.

7.4 ()ualiialitic kijl iis

Ihlc C\i ii.lS of cirCUiS 1, cr\ diffictill. 1101 de aCircui 1k Wint ifeCCI 111C SICCIt ILIoii it iu't h~e

a.11.1 rcd it) find thic Iniitiist. N Niiplc III,,\ ci ot' NO- to thc question of "IN die specifroaiion rnet"'' I,, not

.1140 u~ffiicl. I-or insIimiCt. ifi icraciron bhiv.CCII subpartS Of IIn ObjeCt L.111,d uniexpected bha iror it0

AOuLd1 ho: LINJU to UniderStAnd " lat \Ads %% rong. Qualitti~ e analysis of circits 1\ illiilsIldc Mecer] can

dcecribe in hiah-lcel~e terms ho~k a circuit operates. CIROP %ould not bc able Io take aid~antape of ,uch

qUalitati\C inalysis;. llo~xc~er, a s'lstern thait combined die ideas of Ro~ lancc and CIROP it' described in the

pre\ IOUS setion would understand hoow the circuit was supposcd to operate. 'he expected heha\ ior could be

com1paired \k ith the beha~i ior predicted b) qualiwti\ c anahs\ is. [ his could result in J SyS[Cm t.11t undcrstands

-- the k no" led~e that is thc basis for the falure rules used in CIROP.

7.5 \ Refinenictit Paradigmi

I [he rcFinernent paradigm Ilkirstow] is at technique that implements a high-le\ e program specification in

a 1o~k-decl langua1.e. Several similarities exist betwe en the paradigm'and CIROP. T[he paradigm starts % ith a

* highi-letad prograim specification. With coding and analysis rules. the specification is refined to a detiledl

ho\A-lc\ el program.

The coding rules are similar to CIROP's phrase grammar rules in that they cxpand a programming

concept into a more concrete procedure. For any particular concept there generally cxists more than one rule

pl iheto e\pind it. Simnilar to the circuit grammar. the coding rules describe at refinement tree, which is a

Npkoc of poNsible programs.

I hc a1n.ilvsis ruLes kio" Ibou1 cfficienc\ of implementations, and find tipper and looser bounds oinj

* .ltcrneimplementations of a givn concept. These results are used to choose the most efficient coding rule

for the gian goals. 'he analysis rules are similar to the with-spercs constraintLs used in CIROP's grammar nile

paltcrns. B~oth affecLt the decision of which rule is applicable to expind the current abstract object.

* The reFinerenL paradigm can be statied as follows:

-' 14 1\ N I I \ 1 Pl I \ 06\I) 1

1. Pick sonic node of the iclinent Irce it) expand. hbacd on cost estimatles for theactm e nodes (- ich- are non-tcmiinl le.i\ es).

2. Pick sonic prt of the program descrihed b\ that node to refine. hased on dhe .reliti\e import.,nce ot difttrent parts.

3. l-ind the coding rules thiat c.n hc usLd to refine that part.

4. Prune those rules that fail to satistN plausibility requirements. 0

5. EIxpand the tree b\ applying each of the remaining coding rules to Create newprogram description nodes.

6. Compute cost estimates for the new nodes by applying the analysis rules.

The refinement paradigm uses rules which produce "cost estimates" to decide which piece of the

proviaimi Nhould be refined next. CIROP does not use this type of strategic knowledge for control, although

hum.n engineers do. Some circuit designers like to work on the output stoge and then work their way back to

the input stcg. Other circuit designers choose to Aork on the input stage first. The philosophy is that one

,hmuld concentratc on the piece of the circuit that is the "most difficult" to build to meet the specifications.

' [he ad%,'ntge to0 using such knowledge is that it may direct the designer to a solution more directly. In other

vmords. the dcmoner ma\ ha\e to backtrack from bad solutions less often. CIROP does not use this type of

kinoledgc for two reasons. First it is \ery difficult to formalize in the circuit domain. Second, with the

failure control rules the amount of backtracking is small. CIROP expands its hierarchy in a left-right

breadth-first manner.

Barstow"s use of the refinement paradigm does not use ba~ktracking. Since each step of the refinement

uses correctness presecring transformations, each program in the refinement sequence will satisfy the

functionality specifications. The efficiency rules guide the refinement so that each program in the refinement

sequence is more efficient than the next. The only question would be "is it the best program?" The

question's answer can seldom be answered in a definite way. but if the answer is a fuzzy "yes", that is

probably good enough. In circuit design the answer is either "yes" or "no" because a circuit either meets the

specifications or it does not. Since one cannot verify the specifications exactly until a circuit is built in detail it

is possible for the question to be answkered "no" even though the next lcel abstract circuit seems to meet the

,cpecifications. If the answer is "no" then the systcm must be able to backtrack to find a good solution. The S

I "• \ I 1\ 1 \11 \ 1 IM \R \I) M\7 e

icline men paradigm assumes that using tie etlicienc\ rules will at least guarantee a ftLi/. "\es- or bettel

I hus,. it is not a, important that it he able to backtrack.

. ioll..n

,Molgen IStefi ki is a prog ram that implements a theor) of how to plan gene cloning eperiments b\

ic.l' ing abstract plans. Ilhe important issues in Molsen tit relate to CII OI' are its use of ( ,mlraint P'osiig

.tn1d .1ii-I/,1ninmg. Niolgen \ ic s ( onsir1n AimxIng it, three operations. Irst. constraint I rmulltlion is de

process of creating constraints. This occurs % hen abstract objects arc refined to more concrete objects. The

more concrete object may have constraints that must be meL For instance. whcn performing a

I RANSFORM operation. it is nccessary that the bacterium and vector, which are inputs to the

I R.\\SFORNI operator, be biological]) compatible. Therefore. refining an abstract MFRGE operation to .

I R \NSFORM operation places constraints on the %alues of the bacterium and vector so the TRANSFORM

ikI %kork proper]\. The equations in plfasc grammar rules in CIROP are constrints that are formulated

lihun die rule is c\pandcd. lhe cxpan,,ion ofa C IROP phrase grammar rule is similar to refining an object in

Mohcen.

Secoid. contraint passing propagates the constraint across operations to other objects. Subproblems

communicate h3 passing constraints. Ahich is necessar) since the subproblems ma\ intcract. The constraints

on objects are passed through operators. CIROP's objects correspond to the operators in Molgen. The

constraints in CIROP are passed when the equations arc solved.

Ihird. constraint satisfaction is the pro.ess of looking for concrete objects that will satisfy the constraints

placCd on an abstract object. If onl one ohject can bc found that satisfies die constraints, then Molgen can

rcline the abstract object to that particular concrete object. If no objects satisf3 the constraint, then the

abstract object has been o'erconstrained. CIROP also uses constraints to determine how an abstract circuit

object will be expanded. The fundamental difference is that Molgen is a least commilment planner. If

possible. it will not refine an object until the constraints are satisfied by only one concrete object. CIROP

doe, not try to constrain an object until only one rule is applicable. in circuits, there usually are many ways

of sati4ying a particular goal so it is not possible to create constraints that will eliminate all but one possibility.

Icta-planing controls the exolution of the plan. Three levels of control are used in to model

*A

6 7 6 \1I1 (I\ ", 0

hlicr.tilhical planningi ill Molgcn. The lowesi lc~el e ar L.ab steps. which arc the a~is opC.IItioh in thc

domain. ltik middle l\e l arc )csign steps. which select and execute ie I.ah steps. Thc lop le\el are strat e

,,c'\, 110h -,elect and cxccute the Design steps.

I lhe I iboratory space repreent, knov ledge ahout objects and operat ion, in a genetic lahorator.. This

lcxcl is not a control le\cl: it on1\ rcprccnts kno~ ledge about gcnetics. "Lb I.ahorator\ spaIcc also contains

abstract ohjects and operations.

"1he )esign space contains knowledge about designing plans. This defines a set of operators for

sketching plans abstractly and propagating constraints. Steps arc executed in design space to create and refine 0

the laboratory plan.

he Stratcg space contains simple knowledge about straLtegy for guiding the Design space. It

r -rcsents two major problem solving philosophies: heuristic and least-commitment. The intent is for S

MALogc¢1i to operate in the least-commitment mode whenever possible. If* no steps may be taken without

making a choice on an underconstrained operation. Molgen will operate as a heuristic planner.

0

SLO\( I t. Si()\Sfl

H. Conclusions

.1 I 1 initationsofa Strict I licrarchi 0

N hiiritrch% of' circuis c. descrihe an. circuit %Aih A kino n Iop log. oA c% er. nI does, ino)t ,Jlla s

Lcipure the kno% ledge in at naitural .For instLc, the .enerril P0.11 of a Current cancellmion t.tge for an

OpCr.tjioal i1plifier's first stage is to dramiticalI rcduce the input bias currint. It does Uiis, ith de clc\cr

ick sho)An i I. igme 27. Ihe to currc|t sources libeled 'bias sUppI. tIe current needed to bi.s die Input

irisisiors. V hicL theoreticall] reduces the inpit bias Current to /cro.

lihc implementation of this trick samples the current necessary to drive the input transistors and

Vcc

Ibias Rc R Ibias

T' EE

-VEE

Fig. 27. Current Cancellation Goal

h .co-rcii canccllhition difTerential pair breaks the direct link hctA ccn the Input lias Current and the stage's

I]is allo-s the dcsgner to decrease the Input I1,.i, Current substantially.

•

I Il\l11 \IO 1SO I \S Ik I 1l11 R\HtI\ 71

vcc

I Q3 Q4

B3B

Q QQ 0"

B31 2

* 0 'SE

* -V EE

Fig. 28. l)ctailk of Current CancellationIhe dcuiis of the current cancellation show how the current mirrors sample the collector currents of thedi fierential pairs. and use that to create currents approximately equal to the input transistors' base currents.

O

,*" S .

SI I \1 M O\V 01 \ S I~A R io 1 11 RR I IN 70

Mi1pplies it awjtonmaticill 'iai the current souirces. Biecause of this. the iniptib need rno i(upp)h an. ctirrent t0

diai\ the input1 transisors. In F~igure 28. QI is an input transistor, aind Q3's collCtor current is assumied to, be

*tpplo\Ima1-tel\ die sanme a1' QI s collector current. Assuiming the P3s (i QI and Q3 are tie sarnc. thc basc

kL [CU t', (I'Ql IAnd Q3 should also be the same. I ransistors QS and QOi are C0111tiC-Lil d i, i cuirrent mirror.

I[he% taike i1 reference Current. -Ahich is the collector current of Q5. and create A mnatching cuirrent aN the

- collector current of Q6~. fl1iis matchied currcn .ipproxirnately' eqLials Q3*s base current. '% hich ippioxini.itel%

equi.ils QI\s baise current. Ibis matched current suipplies Elhe base cuirren( necesr% for QI. [hle abo% C

technique issumes that the transistors' P's are large and nearly equal. which is a reasonable approximation for

( ain integrated bipolar circuit.

Unfortunately, this clever trick does not appear in the circuit grammar rcpresentation of the current

c~incellation swge. TVherefore, the entire circuit built around each different use of this trick must be

represented in detail in the grammar.

4 0

I k \\1%I OltMA I lo\s 7

8.2 Trantsformxatjins

\oi .ill ischul cir-cL~it, Can) he described casil b\ iheach\ of construction rules SUch aS CIRIOPS

phraise pr.immar ries. For instance. tie protection circuitr) uised in the out1put Stage of an operational

.inipli I Ir is not reall\ p)art of die circuit during normal operation. Figuire 29 sho%% it a tpical output stage

helorc ind after protection is added to the top transistor.

4 out out0

Vn Vn

Before Transformation After Transformation

Fig. 29. Output Stage Protection hi Transformation['he outpuit suseC of an operational amplifier is protected by transforming a fragment of thc circuit into a newfragment that sull achieves the original goals. but no"~ is protected.

Transformations are context-sensitive rules that can transform an existing part of the circuit into

something else. They can help simplify a circuit after it s designed. as shown in Figure 30. The top circuit is

the product of the phrase grammar manipulations. Thc bottom circuit is OpliMized because the t~o inductors

ha~e been combined into one.

Si? I R \\S I ORM \\IIO 7

,i"Li L2

I L2

H-,. 30. I nductor ransforinat ionI hc example circuits- ,ho\&s a simple optimi.ation ofcomhbinina tLo parts into one.

a08.3 Algcbra

Although circuit designers must seldom solve complex equations, it may still be neccssary to solve more

complex algebra than CIROP can. Its algebra system is limited bccause it does not understand inequalities

nor approximations. and cannot manipulate any mathematical operations, except the four basic arithmetic

operations. Inequilities are necessary since specifications are usually stated as inequalities. Since CIROP

Sircats mncqu. ilitie as equili nc, it mn.i conclude that it cannot find a solution for a set of specifications. because 0

it nirn be harder to mcet d ,pc. ,,uLaions cxact.. Human engincers use mans approximations in design.

For instance. the following equation mao seem complex:

C UB + 1)*A +D)fA+ D

In designing electronic circuits, the anahle fl often is at least 50-100. It is usually valid to assume that

(+ 1) approxim itel% equals ft. Therefore, the above equation can be simplified to the salue C. CIROP

* .0

i \I IRXA 74 0

+,i+ lit~iie ,u, ch Nipliflilng approxi1atilns. 'Aithout suLh approximations. a nore po cul Jlkwhra

,+,',tm is required.

I r,,nsistors and other componcnts cannot al a. s he de,;crihed and analy/ed is linear compolncnts. This

results in cquton; 1 ith exponentials. rcquirin,., complex algebraic manipulations. The human engincer can

usuUllv simplil\ equations using knok ledge that CIROI' does not hae.

lhe algebra system of the futre should he able to nmanipulate more complicated eqtations. make

.ipproximations %hen useful. and understand inequalities.

8.4 )irecting the Search in Circuit Space

I he engineer uses his experience to guide him through a design. His experience usually preents him

4 from going down incorrect paths. and instead leads him to a good solution in a seemingly direct manner.

CIROP has approximated this ability to avoid obviotsl errant paths with the specification tradeoffs

mechanism. howecer, this does not capture all of the intuiti~c knowledge that humans use. Humans also

categorize operational amplifiers into secral classes. High-speed. low-poer. high-powcr. and high accuracy

arc some categories appropriate for operational amplifiers. The differences in the classes are represented by

the tradeoffs in the specifications. Knowing the class of a proposed amplifier can direct the search by

eliminating options that are never found in amplifiers of that class. CIROP does not use this method.

although if the classification knowledge were formalized, it could be incorporated with the strategic

knoA ledge that determines the rules used in expansion.

8.5 Frequency Analysis

Anal\ss and reasoning about frequency response is so difficult that few human engineers do it well.

Resoning about frequency response requires the ability to analyze the circuit from other \iewpoints. Except

for slc% rate analysis, this area has been avoided in CIROP.

S

I hc L:i,,,i tClo t' been to deni d ui,,tI im i thc r.\ of ordiar. desian. CIROIP does suprisingl. AclI

' .In k ,I c"i dc\121 It dc )i'lN . 1ints ,11 thv I:col o Liuomplexit. dtlc-rihcd in Solni n's cls.ic paper

119"41 I hus,. CI ROtP demonstrates an upper bound on the amount of know ledge needed to ichic\e this lccl

ofcompetane.

A ne.k grammar descrihing sc\cral 'arieties ol'operational amplifiers ', as de'elopcd lor CIROP. The

phrase grammar's rules were dc\cloped to describe thc I)C characteristics of operational amplifiers. These

rulC, shoA that each of sce'cral common operational amplifiers can be modeled as a hierarch\ of abstract

objects. l1ie analysis of these circuits was accomplished with the hierarchical assertions of equations.

lie rcpresentation usCd in CIROP is general and extcnsible. New rules can be added that describe new

Sa) s of building existing abstract objects and defining new abstract objects. The hierarchical paradigm fits S

run,, ex.mples in the circuit domain. For instance. a raidio's tuner can be sho" n hierarchically as a collection

of three lower l'el objects: a con crier, an IF strip, and a detector.

There is no direct limitation on the type of equations. If more complex algebra is necessary, one could

interface it with a MACS) MA IMACSYMAI. The failure rules could have a more complex interpreter

implemented naturally with the rest of the system.

I he topolog and beha% ior of the dc\ices are the main ingredients in a circuit. The representation of

th , \h tiild hc expliciL which is accomplished b\ the phrase grammar rules. The equations that model the

. o -ft Ow ph1 I.d t h hlict, ore the s,mie equations used in models by engineers. The equations used in

:1- I. Je!' 1o ,umiilar to the cquations used b\ engineers and fit the domain naturall. Subject

:, : .,t: drsicd the reprcscntaUtior is complete and concise. The rules contain no extraneous

i:.:r". , U;,It ShOuld :Onfuse an engineer. CIROP accomplished its goal of demonstrating a theory for

• design. 0

* ,i

,lho Abo. Alfred V. and Ullmnan. Jcflrc\ I). Principles of Comipiler IDesign Addison & Wesle\.1979.

BarswI .irsto'~ . I0j\ id It. and Kant. IlIinL. " ''[b Refineii I'aradigm: The Interaction of Codinevand Efficiency Knoim ledge in Progrim S ihesis".

IBrokaw lrokdvh. A. Paul. Linear Synthesis for Moniolithic Circuits Analog D~e% ices. Inc.. 1978.

John Wile) & Sons. Nc% York, 1969.

tiraj P'. R. Gray. Paul R.. Meyer. Robert G.. Analisis and Design of Analog Integrated Circuits John4 Wile) & Sons 1977.

dec Kicer-I de Mecer. Johan. J. DlIe, C. Rich. G.Stecec. and G. Sussman, "AMORI): A l)eductjveProcedure System" Ml] Artificial Intelligence Lab.. AIM 485. September 1978.

tic A leer-?2 de Mecer. Johan, Causal and Tecleological Reasoning in Circuit Recognition MIT ArtificialIntellizence Lab.. AI-TR-529. September 1979.

ic Alcer-.? de Kleer. Johan. and SUSSMan. Gerald Jai, "Propagation of Constraints Applied to CircuitSynthesis" MIT Artificial Intelligence L~ab-. AIM 485. September 1978.

4Do v/c D~oyle, Jon Truth Maintenance System for Problem Sol% ing MIT Artificial Inrtelligence Lab..AI-TR-4 19. January 1978

AIACSIAIA ilie Mathlab Group MACSYMA. Reference Manual MlIT L~aboratory for ComputerScience.. January 1983.

AMcDermnoi Mcl~ermott, Drew Vincent. Flexibility and Efficiency, in a Computer Program for Dcsigning

Circuits MIT 'Artificial Intelligence L-ab.. Al-TR-402. June 1977.

. ICIoniald MlcIonaild. IDa~id D).. Natural Language Generation as a Computational Problem: an

Iiilroduction COINS I echnical Report 81-33 University of Massachusetts at AMhert.L

iluje's MaidiCIue. NModesto A.. SuLli\ an. D~ouglas R.. CTharacterization and Analysis or a NeA HighPerformance Operational Amplifier Family Transitron Electronic Corporation. WakefieldLMassachusetts.

Roberge Roberge. James K.. OPERATIONAL A.MPLIFIERS: Theory and Practice John Wiley &0Sons Inc. 1975.

R0.1lan1CC75 Roylancc. Gerald L., 'Anthropomorphic Circuit Analysis" MIT Bachelor T'hesis in EECS,June 1975.

1) Bwn IOUiR %III IY

R'ox huwccS( Rto lance, Gei Id I .. "A Sinmple Niodel of Circulit I )cigen" Nil I kasters, Thesis in I.FCS.14110.

Sbrobc Shrobe. Ht. Icpcidciic% I )ircctcd Reasoning for ( omplc\ l'rograiin I nderstanding NIArtificil Intellicence I -ab.. Al- I R 503, April 1979.

Simon, Herbert A.. The Sciences of the krtificial MITV Press 1969.

.Sohmiwi Solomon. James F., "'I he Monolithic Op Amp: A 'I'Luorial Stud\"' I EE JOn rnal Sol id-StateCirU~S. ol SC9.pp. 314-332. lOccemher 1974.

Suillinan. Richard Ni.. SLISSman. Geraild Ja\. "'orard Reasoning and IDepecdenc\lDirectcdllacktratckinu In i S~ stcmn for (iompffler-Aicd Circuit Analy'sis" MITr Artificial IntelligenceLab.. A111-3801. Sept. 1970.

XIcfihA Stefik. Mirk Jeff~re). "I'lannine %%ith Constraints" Stanford Computer Science Dept..SI -%-CS-fl-7S4. Jan. 1980

N Ufiiiau Sulli' an. I)(uglais R.. Madilqtie. Modesto A.. "Niatched IDesigPn - Key to i near ICs" El)N4Fehruair 15. 1971.0

SuLI\ aN11. Di )olL R. mnd Nlaidique. Miodesto A.. Characterization and .\pplication ofa acHigh Input Inipedanci' Monolithic AXmplifier 'I ransitron Electronic Corporation. WVakefield.Majsxhachetts.

C M'paw.-l Sussmajn. Geraild Jai\. A Computer Model of Skill Acquisition Elsevier Computer Science

Library. 1975.

U3911(711- 2 Sussman. Gerald Ja% and Steele. Gu) 1Lewis Jr.. "Constraints: A I annuage for Expressing

Almost-Hlierarchical lDescriptions" MIT Artificial Intelligence L-ib.. AIM-502A, August

* 1981.

Sussman-3 Sussman. Geraild Jay. "Slices: At the Boundlar\ Bermeen Anahsi s and Syn'zhesis" MITArtificial Intelligence Lab-. AIM-433. July 1977.

-4 1 fidia r Widlar. Robert J.. "D~esign I echniqucs. for Mionolithic Op ,r.ttional Amplifiers" IFEEJournal Solid-State Circuits. vol. SC-4. pp. 184-191. August 1909.

lHid/ar Widlar. Robert J.. "IC OP AMP Beats F I's in Input Current" EFE. lDecember 1969.

WH Xanis Williams. Brian C.. "Qualitafive Analysis of MOS Circuits" MIT NMasters Thesis FECSJanuary 1984

I I111 ISI (,R\M.\iR RLI FS 78 - -

Appendix I - Phrase (ramnmar Rules

1.1 Suinmar.% of Ii pc, of Ocra ional kniplifiers S

I he following kinds ofcircuits can he built with the gi\cn rles.

St,indard Three sLIgc operational amplifier with the following stages:

For thc first sLC:

Simple differenti;l pair with resisti c loadSimple differential pair % ith simple current mirror loadSimple differential pair with complex current mirror load 0l)arlington differenial pair A ith r isu'e load

I )arilinaton differential pair %ith simple current mirror loadI )arlinston differential pair % ith complex current mirror loadSuper Beta differential pair with loadCurrent Cancellation Pair with load

For the second stace:

Simple common emitter

l)arlington common emitter

For thc third stage:

Standard push-pull output stage with two diode drop biasingSLandard push-pull output stage with I + 1/2 diode drop biasing

With these possibilities 32 different operational amplifiers can be synthesized.

74J* 0

1.2 A hlrjc))hj.0. ,,, i nrase Grammar

1.2.1 I rce !itag Operational .\mplifier

Lll i die normal \jnill, flit\or op-.mip. differentidl front cnd simple amplifier for die gin stogc. and

huffer OItpnr Stage. ( to-make-an ?op-amp three-stage-operat ional -ampI ifier: Pattern of applicability:

where (type fop-amp amplifier)(has ?op-amp (input differential))(has ?op-amp (output single-ended))(has ?op-amp (input voltage))

(has ?op-amp (output voltage))

(has ?op-amp (priority 1))

(with-specs (gain-spec (voltage-gain Top-amp))

(slew-rate-spec (slew-rate ?op-amp))(input-offset-current-spec

(offset-current ?op-amp))(input-bias-spec (bias-current ?op-amp))

(input-offset-voltage-spec (offset-voltage ?op-amp))

(drive-spec (output-drive ?op-amp))

(power-spec (power-consumption ?op-amp))))

Topology is as follows:Parts are:

(new-part (first-stage Top-amp) S((type (first-stage fop-amp) amplifier)(has (first-stage ?op-amp) (input differential))

(has (first-stage ?op-amp) (output single-ended))(has (first-stage ?op-amp) (input voltage))

(has (first-stage ?op-amp) (output current))(has (first-stage ?op-amp) (sign pnp)))

((use . ((gain gm) (slew-rate gm)))

(with-specs(k ttransconductance (first-stage fop-amp))

(sqrt (0 2 (gain ?op-amp)))))))(new-part (second-stage ?op-amp)

((type (second-stage ?op-amp) amplifier)(has (second-stage Top-amp) (input single-ended))

(has (second-stage Top-amp) (output single-ended))

(has (second-stage ?op-amp) (input current))

(has (second-stage ?op-amp) (output voltage))(has (second-stage Top-amp) (sign npn)))((with-specs

(: (tran. esistance (second-stage ?op-amp))

(sqrt (0 2 (gain ?op-amp)))))))

(new-part (feedback ?op-amp)

((type (feedback ?op-amp) capacitor)))new-part (third-stage ?op-amp)

((type (third-stage fop-amp) buffer)(has (third-stage ?op-amp) (input voltage))

(has (third-stage Top-amp) (output voltage))))

Connections to outside are:

(connect (t+ Top-amp) (t+ (first-stage Top-amp)))0 (connect (t- ?op-amp) (t- (first-stage Top-amp))) 0

(connect (ot fop-amp) (ot (third-stage Top-amp)));; Internal connections are:

(connect (ot (first-stage Top-amp)) (it (second-stage ?op-amp))

(tl (feedback fop-amp)))

(connect (ot (second-stage ?op-amp)) (it (third-stage ?op-amp))

(t2 (feedback ?op-amp)))0* Propagating specifications to parts:

The gain of an op-amp is due to the product of the first two stages gain.

* S

I' III KII I )I'!RAIION\.\l \\11'1 1111K K 9

(: (gain ?op-amp)( (transconductance (first-stage ?op-amp))

(Ioddillg (secuIId-sLdge ?op-amp) (first-stage ?op-amp))(transresistance (second-stage ?op-amp))))

(equat ion-with-variable-priority(: (transresistance (second-stage ?op-amp))

( (current-gain (second-stage ?op-amp))(input-impedance (third-stage ?op-amp))))

(transresistance (second-stage fop-amp)))(equation-with-variable-prIority(: (loading (second-stage 7op-amp) (first-stage ?op-amp))

(// (output-resistasice (first-stage fop-amp))(+ (output-resistance (first-stage ?op-amp))

(input-resistance (second-stage ?op-amp)))))(loading (second-stage ?op-amp) (first-stage ?op-amp)))

(equation-with-variable-priority(= (load-resistance (second-stage ?op-amp))

(input-impedance (third-stage ?op-amp)))

(load-resistance (second-stage ?op-amp)))Power consumption is just the sum of the individual powers

(' (power-consumption ?op-amp) 0(+ (power-consumption (first-stage ?op-amp))

(power-consumption (second-stage ?op-amp))(power-consumption (third-stage ?op-amp))))

simple equation for determining the slew rate.(z (slew-rate ?op-amp)

(// (max (current (ot (first-stage ?op-amp))))(capacitance (feedback ?op-amp))))

(: (cutoff-frequency ?op-amp)(I/ (transconductance (first-stage ?op-amp))

.(capacitance (feedback ?op-amp)))). The input offset current is one of the main specs given by the user.(= (offset-current ?op-amp) (offset-current (first-stage ?op-amp)))

the input bias current is one of the main specs given by the user.( (bias-current ?op-amp) (0 -1 (bias-current (first-stage 'op-amp)))). Ihe input o'fset voltage is one of the main specs givenby the user. S

(: (offset-voltage ?op-amp) (offset-voltage (first-stage ?op-amp)))] The drive current is the amount of current that the amp can deliver to

;. a load of a specified size. probably 2K ohms.(= (drive-current ?op-amp)

(maximum (current (ot (third-stage ?op-amp)))))assumption is that most of the distortion comes from the third stage.

(- (distortion ?op-amp)(distortion (third-stage ?op-amp)))might as well say what the third stage voltage gain should be.

(= (voltage-gain (third-stage ?op-amp)) 1))

1.2.2 Simple I)iffrential Pair

(to-make-an ?dp simple-diff-pairPattern to match:

(where (type ?dp amplifier)(has ?dp (input differential)) (has ?dp (output single-ended))(has ?dp (input voltage)) (has ?dp (output current))(has ?dp (sign ?sign))

(has 7dp (priority I));; something about a the sign(with-specs(= (transconductance ?dp)

( (bias-current ?dp)(eval (if (eq (quote ?sign) 'NPN)

(get-algebra-value 'NPN-BETA)

., ' .

(get-algebra-value AINP-81t A)))

OI'irrelvulltaye ?,dp) siple-offset-voltage)))Parts are:

(iitw-parl (pos-q ?dp)

(type (pos-q ?dp) v irtual-bjt-transistor) -(lids p,,! q 'dp) (ign 7s ign))

((use' ((gali 9m)))I((type (neg-q ?dp) v irtual-bjt-transisLor)(has (neg-q ?dp) (sign ?sign'))((use ,((gain gmi)))

(new-part (load ?dp)

((type (load ?dp) differential-pair-load)))(new-part (source ?dp)

((type (source ?dp) current-source)))

Connections to outside are:(connect (t+ ?dp)(base (pos-q ?dp)))( (connect (t- ?dp)(base (neg-q ?dp)))(connect (emitter (pos-q ?dp))(emitter (neg-q ?dp))(tl (source ?dp)))(connect (ot ?dp)(collector (pos-q ?dp)) (t2 (load ?dp)))(rail-connect (1,2 (source ?dp))(rail (negative ?sign)))

Propagating specifications to parts:To1 calculate bias current, assume that we can cheat and assume thatthe bias current is basically one of the transistors input current.

(~(bias-current ?0p) (current (base (pos-q ?dp))))T he offset current can be done by getting a delta-current from theSthe load stage(offet-current 'dp)

(I(delta-curreil (load ?dp))(beta (pos-q ?dpf))

Th. e voltage offset for a given differential pair can be calculatedonce and then used as a constant.( (~ (offset-voltage ?dp) (offset-voltage (pos-q ?d)))The transconductance is the gain element in the diff pair.

*It's value depends on the type of load used.(~(transconductance ?dp)(* (gin (pos-q ?dp)) (transresistance-factor (load ?dp))))So that the slew rate can be calculated it must know this

(equation-with-variable-priority* (~(max (current (ot. ?dp)))

(1 -2 (current (collector (pos-q ?dp))))/)(max (current (ot, ?dp))))* : output resistance(equation-with-variable-priority

((output-resistance ?dp)(0! (ro (pos-cq ?dp)) (ro (t.2 (load ?dp))))

(+ (ro (pos-q ?dp)) (ro (t2 (load ?dp))))))(output-resistance ?dp))

1.2.3 Simple Common F.MittCr

4 (to-make-an ?amp simple-commion-emitter*Pattern to match:

(where (type ?amp amplifier)(has ?amp (input single-ended)) (has ?amp (output single-ended))(has ?amp (input current)) (has ?amp (output voltage))(has ?amp (sign ?sign))(has ?amp (priority 1))

* (with-specs ( transresistance-spec(transresistance ?amp))

(power-consumption ?Amp)))

*Parts are(now-part (q ?amp)

(( type~ q 7d-it, v i r tua I lij I L I dII!, is tot)(has (q '1alp) (sign ?sign)))

((use (ga in beta))Connect ions are:

(connec 1 ( it ?amp ) (base (q ?anip)))(connect (at ?amp) (col lector (q ? amp))

*somie connecti'on of emitter for biasing(connect (dc-bias ?amp) (emitter (q ?ainp)))

specifications(~(input-resistance ?amp) (rpi (q ?amp)))

(equation-with-variable-priority(= (max (current (at ?amp))) (current (collector (q ?amp))))(max (current (at ?amp))))(~(power-consumption ?amp)(0 voltage-range (current (collector (q ?amp)))))

(~(current-gain ?amp)(beta (q ?amp))))

1.2.4 Simple Commlon Collector

(to-make-an ?amp simple-commion-collector;: Pattern to match:(where (type ?amp coimmon-collector)

(has ?amp (input single-end~d)) (has ?amp (output single-ended))(has ?amp (input voltage)) (has ?amp (output voltage))(has ?amp (sign ?sign))(has ?amp (priority 1)))

*Parts are:(new-part (q ?amp)

((type (q ?amp) virtual-bjt-transistor)(has (q ?amnp) (sign ?sign))))0

*Connections are:(connect (it ?amp) (base %q ?amp)))(connect (at ?amp) (emitter (q ?amp))):: some connection of emiitter tar biasing(connect (dc-bias ?amp) (collector (q ?amp)))(= (current-gain ?amp) (beta (q ?amp))))

1.2.5 Simple Follower

(to-make-an 'toll simple-tollower:: Pattern to match:(where (type ?toll follower)

(has ?tol) (sign ?sign))(has ?foll (priority 1)))

*,Partz

(new-part (element ?toll)((type (element ?foll) comon-collector)(has (element ?foll) (sign ?sign))))

.Connections0

(connect (at ?toll) (at (element ?toll)))(connect (it ?toll) (it (element ?toll)))

(~(currant-gain ?foll) (current-gain (element ?foll))))

I' )11 I11<1 I I Nl l'\IRV \( I I O)AP

I.D.i lDiffhrcmiial Pair kcti~t Load

(c' iake- an ?load d ifferent ialI-pa ir-act ive- loadPattern to match-

e~~ (Iyp.e "load d ifferent iaI- pa ir- load)(has ? load ( sign ?s iqn) )(has ?load (priority 1))(with-specs (delta-current-spec (delta-current ?load))

(transresistance-factor-spectIransresistance-factor ?load))))

*Parts are;(new-part (cm ?load)

((Iype (cm 'load) current-mirror)))Connect ions are:

(connect (tI ?load) (reft (cm ?load)))(connect (tZ ?load) (outt (cmn ?load)))

((ro (t2 ?load)) (ro (outt (cm ?load))))(~(delta-current ?load) (delta-current (cm ?load)))(2 (transreristance-factor ?load)))

1.2.7 D~ifferential Pair Resisti~e L~oad

to-make-an 7load differential-pair-resistive-load(where (type ?load differential-pair-load)

(has ?load (sign ?sign))(has ?load resistive)(with-specs (transresistance-factor-spec

(transresistance-factor ?load))Partsare: (delta-current-spec (delta-current ?load))))

(nwPart are:la)(tp r ?od eitr)(niew-part (rI ?load) ((type (rI ?load) resistor)))

Connections:(connect (ti ?load)(t2 (rI ?load)))(connect (t2 ?load)(t2 (r2 ?load)))(rail-connect (rail ?sign)(tl (rI ?load)))

* (rail-connect (rail ?sign)(tl (r2 ?load)))specificationsthe delta current is dependent on how accurate we can make resistors

*for a simple load(~(delta-current ?load) (0 resistor-accuracy (current (t2 ?load))))(~(ro (t2 ?load)) (resistance krZ ?load)))p(ro (ti ?load)() (resistance (rl ?load)))

* ~ 1 (transresistance-factor ?load))

(~(resistance (rI ?load))(resistance (r2 ?load))))

1.2.8 Simple Current MirrorA

* (to-make-an 7cm simple-current-mirror;; Pattern to match:(where (type ?cm current-mirror)

(has ?cm (priority 1))

(has ?cm (sign ?sigjn))

(with-specs (delta-current-spec (delta-current ?cm)))) .* (new-part (diode ?cm)

((type (diode ?cm) virtual-bjt-translstor)(has (diode ?cm) (sign ?sign))))

* I ~ 'I\ll'l I (A RKII \IMIRROR *

(new-part. (output-trans. ?cm)((type (output -trans ?cm) v irtualI-bjt- trans is tor)(lids (output-ti-aw. ?LM) (sign ?sign))))

*Connect to output:Also make diode into a diode

(connec t ( rert ?cm) (collector (dilode ?cm)(base (diode ?cm) ) (base (Oulpst -trans ?cm) )

(connieCt (outt ?cm) (collector (output -Irans ?cm))Inlefnal connections:

(rail-coninect (emitter (diode ?cm)) (rail (negative ?signf)(rail-connect (emitter (output-trans ?cm)) (rail (negative ?sign)))

.Specifications(equationi-with-variable-priority

(ro (outt ?cm)))(~(delta-ctirrent ?cm) (// (current (collector (output-trans ?cm)))

(beta (output-trans ?cm))))(~(current (emitter (diode ?cu))) (current (emitter (output-trans ?cm)))))

1.2.9 W~ilson Current Mirror

Ito-make-an ?cm wilson-current-mirror:; Pattern to Match:(where (type ?cm current-mirror)

(has ?cm (sign ?sign)))N ~ew Parts:

(new-part (diode ?cm)((type (diode ?cm) virtual-bjt-transistor)(has (diode ?cm) (sign ?sign))))

*(new-part (output-trans ?cm)((type (output-trans ?cm) virtual-bjt-transistor)(has (output-trans 7cm) (sign ?sign))))

(new-part (q ?cm)((type (q ?cm) virtual-bjt-transistor)

(has (q ?cm) (sign ?slgn))))*Connections:*connect to output

(connect (reft ?cm) (c~llector (q ?cm)))4(connect (reft 'cm) (base (output-trans ?cm)))

(connect (outt ?cm) (collector (output-trans ?cm)))*in:ernal connectionsmake diode into a diode

(connect (base (diode ?cm))(base (q ?cm))(collector (diode ?cm)))(rail-connect (emitter (diode ?cm))(rail ?sign))(rail-connect (emitter (q ?cm))(rail ?sign))(connect (emitter (output-trans ?cm))(collector (diode ?cm)))

(~(delta-current ?cm) (// (current (collector (output-trans ?cm)))(beta (output-trans ?cm))))

(~(current (emitter (diode ?cm))) (current (emitter (output-trans ?cm)))))

1.2.101 NornyitIOp WmP Outpu( siage

to-make-an 7buffer normial -op-anip-output-stage*Pattern to match:

(where (type 7b buffer)(has 7b (input voltage))(has 7b (priority 1))(has ?b (output voltage))(with-specs (power-coiisumption-spec (power-consumption ?buffer))))

Parts are:(new-part (input-stage ?b1

((type (input-stage ?b)complemient-pair-input-voltage-drop-input-stage)))

(new-part (output-stage ?b)((type (output-stage ?b) complement-pair)(has (output-stage ?b) (sign npn))))

Connections are:(connect (it ?b) (it (input-stage ?b)) (it2 (output-stage ?b)))4 (connect (ot ?b) (ot (output-stage ?b)))(connect (topt (input-stage ?b)) (itl (output-stage ?b)))

(equation-with-variable-priority((maximum (current (ot ?b)))

(-1 (current-gain (output-stage ?b))(current (it ?b))))

(maximum (current (ot ?b))))(~(power-consumption ?b)(+ (power-consumption (input-stage ?b))

(power-consumption (output-stage ?b))))the distortion or this stage depends mostly on the type ofinput stage used to bias the voltage drop across the output drivers.

((distortion 7b) (distortion (input-stage ?b)))(~(input-impedance ?b)

l oad- res istance (current-gain jouitput-stae ?b))))-0

1.2.11 Comnplement Pair Input V'oltage D~rop Input Stage

4 (to-make-an ?cpvd complement-pair-input-voltage-drop-input-stagePattern to match:

(where (type ?cpvd complement-pair-input-voltage-drop-input-stage)(has ?cpvd (priority 1))(with-specs (power-consumption-spec (power-consumption ?cpvd))))

*New parts:* (new-part (dr6p ?cpvd)14 ((type (drop ?cpvd) complement-pair-input-voltage-drop)))

(new-part (load ?cpvd)((type (load ?cpvd) resistor)))

*Connections:

(connect (it ?cpvd) (it (drop ?cpv4)))(connect (ot ?cpvd) (ti (resistor ?cpvd)) (ot (drop ?cpvd)))(rail-connect (t2 (resistor ?cpvd)) (rail ?3ign))

(~(power-consumption ?cpvd)(0 voltage-range (current (load ?cpvd))))

((distortion ?cpvd) small-distortion)((bias-current (input-stage ft))

(current (ti (resistor ?cpvd)))))

I SIMPII O~l'l IMI\RNY PAIR K

*1.2.12 Sipl(om~plemntar3 Pi

(to-make-an ?cp simple-complementary-pair*Pattern to Match:

(where (type- 7cp complement-pair)(has cp (sign ?Sign))(has ?cp (priority 1))(with-specs (power-consuimption-spec (power-consumption ?cp))))

*Parts are:* (new-part (pull-up ?cp)

((type (pull-up ?cp) fallower)(has (pull-up ?cp) (sign ?sign))))

* (new-part (pull-down ?cp)((type (pull-down ?cp) follower)(has (pull-down ?cp) (sign (negative ?sign)))))

*Connections are:(connect (at ?cp) (at (pull-down ?cp)) (ot (pull-up ?cp).))(connect ( iu ?cp) (it (pull-up ?cp)))(connect ( id ?cp) (it (pull-down ?cp)))

(~(current-gain ?cp) (current-gain (pull-down ?cp)))(~(power-consumption ?cp)

(voltage-range (current (collector (pull-up ?cp))))))

1.2.13 Single Transistor ijt0

(to-make-an ?v-bjt Single-transistor-bjt.. Pattern to Match:(where (type ?v-bjt virtual-bjt-transistor)

(has ?v-bjt (sign ?sign))4 (has ?v-bjt (priority 1)))0(new-part (q ?v-bjt)

((type (q ?v-bjt) bjt)(has (q ?v-bjt) (sign ?sign))))

(connect (base ?v-bjt)(base (q ?v-bjt)))(connect (collector ?v-bjt)(collectar (q ?v-bjt)))(connect (emitter ?v-bjt)(emitter '4 ?v-bjt)))

4 (= (ro ?v-bjt) (ro (q ?v-bjt)))

* (~ (gin ?v-bjt) (gmn (q ?v-bjt)))(~(beta ?v-bjt) (beta (q ?v-bjl))))

1.2.14 D)ouble Darlington Trainsistor Bit

(to-make-an ?v-bjt double-dan ington-transistor-bjt*Pattern to Match:

(where (type ?v-bjt virtual-bjt-transistar)(has ?v-bjt (sign ?sign))(has ?v-tjt (priority 2)))

(new-part (ql ?v-bjt)((type (qI ?v-bjt) bit)(has (qI ?v-bjt) (sign ?sign))))

(new-part (q2 ?v-bjt)((type (q2 ?v-bjt) bit)(has (q2 ?v-bjt) (sign ?sign))))

(connect (base 7v-bjt)(base (qI ?v-bjt)))(connect (collector ?v-bjt)

(collector (qI ?v-bjt))(collector (q2 ?v-bjt)))

1 14 1 X)t Ill I I)ARI 1%( 110j\ IRA\SSIOR hI I K7

(connect (emitter ?v-bjt)(emitter (q2 7v-bjt)))(connect (emitter (qI ?v-bjt)) (bjase (q2 ?v-bjt)))

((rpi ?v-bjt) (r (2 (bjt)) ?-j))(p (i v-j))

(~(beta ?v-bjt) (* (Idea (qI ?v-bjt)) (beta (q2 ?V-bjt))))C (~(gin ?v-bjt)( I 1 2) (gin (q2 ?v-bjt))))) 0

1.2.1; Super Beta IDiffrriiaiI Pair

* (to-make-an ?dp super-beta-dift-pairPatterni to Match:

(where (type ?dp ampliftier)(has ?dp (input difterential))(has ?dp (output single-ended))-(has ?dp (input voltage))

(has ?dp (output current))(has ?dp (sign npn))(has ?dp (priority 3))(with-specs (input-bias-spec (bias-current ?dp))

(ottset-current-spec (oftset-current ?dp))(oftset-vol tage-spec (offset-vol tage ?dp))(gain-spec (transconductance ?dp))))

- . .State the components:*(new-part (pos-q ?dp)

((type (pos-q ?dp) super-beta-bjt-transistor)(has (pos-q ?dp) (sign ?sign))))

(new-part (neg-q ?dp)((type (neg-q ?dp) super-beta-bjt-transistor)(has (neg-q ?dp) (sign ?sign))))

(new-part (pos-q2 ?dp)((type (pos-q? ?dp) virtual-bjt-transistor)(has (pos-q2 ?dp) (sign ?sign))))

(new-part (neg-q2 ?dp)((type (neg-q? ?dp) virtual-bjt-transistor)(has (neg-q2 ?dp) (sign ?sign))))

(new-part (diodel ?dp)((type (diodel ?dp) diode)))

(new-part (diode? ?dp)* ((type (diode? ?dp) diode)))

*(new-part (diode3 ?dp)((type (diode3 ?dp) diode)))

(new-part (diode4 ?dp)((type (diode4 ?dp) diode)))

(new-part (sourqel ?dp)((type (sourcel ?dp) current-source)))

' new-part (source? ?dp) 1((type (source2 ?dp) current-source)))

Connect to outside terminals(connect (pos-it ?dp)(base (pos-q ?dp)))(connect (neg-it ?dp)(base (neg-q ?dp)))(connect (pos-ot ?dp)(collector (pos-q? ?dp)))(connect (neg-ot ?dp)(collector (neg-q2 ?dp)))(connect (pos-it ?dp)(tl (diode3 ?dp)))

*(connect (pos-it ?dp)(t2 (diode4 ?dp)))0(connect (neg-it ?dp)(t2 (diode3 ?dp)))(connect (neg-it ?dp)(tl (diode4 ?dp)));- now internal connections(connect (emitter (pos-q ?dp))(emltter (neg-q ?dp)))(connect (base (pos-q2 ?dp)) (base (neg-q2 ?dp))

(tl (diode! ?dp)) (t2 (source? ?dp)))*(connect (collector (pos-q ?dp))(eniitter (pos-q2 ?dp)))

(cunnect, (collector (neg-q ?dp))(emltter (neg-q2 ?dp)))(connect (t2 (diodel ?dp))(tt (diode? ?do)))

I' I st I'lIII-IAII IR IA II Al PAiR

(connect (,tl (sourcet ?dp)) (t.2 (diodeZ ?dp)) (emitter (pos-q ?dp)))(rail-connect (t.1 (Source2? dp))(rail ?sign))(rail-connect (t2 (sourcvl ?dp))(rail (negative ?sign)))

Propagating specifications to parts:(~(offset-voltage ?dp) simple-offset-voltage)

transconductance ?dp)(0 (gin (pos-q ?dp)) (transresistance-factor (load ?dp))))

(~(bias-current ?dp)(* 2 (current (base (pos-q ?dp)))))

(~(bias-current ?dp)(* 2 (current (base (neg-q ?dp))f))

L.' 16 Current Cancellationi Differential Pair

(to-mere-an ?dp current-cancellation-amp(where (type ?dp amplifier)

(has ?dp (input differential))((has ?dp (output single-ended))(has ?dp (input voltage))(has ?dp (output current))(has ?dp (sign ?sign))(has ?dp (priority 2))(with-specs (input-bias-spec (bias-current ?dp))

(offset-current-spec (offset-current ?dp))(offset-voltage-spec (offset-voltage ?dp))0(gain-spec (trangconductance ?dp))))

State the components:(new-part (pos-q Udp)

((type (pos-q ?dp) virtual-bjt-transistor)(has (pos-q ?dp) (sign ?sign))))

(new-part (neg-q ?dp)4 ((type (neg-q ?dp) virtual-bjt-transistor)(has (neg-q ?dp) (sign ?sign))))

(new-part (q3 ?dp)((type (q3 ?dp) virtual-bjt-transistor)(has (q3 ?dp)*(sign ?signf))

(new-part (q4 ?dp)((type (q4 ?dp) virtual-bjt-translstor)

4 (has (q4 ?dp) (sign ?sign))))(ne.-part (q5 ?dp)

((type (q5 ?dp) virtual-bjt-transistor)(has (q5 ?dp) (sign (negative ?sign)))))

(new-part (q6 ?dp)((type (q6 ?dp) virtual-bjt-transistor)(has (q6 ?dp) (sign (negative ?sign)))))

(new-part (q7 ?dp)((type (q7 'dp) virtual-bjt-transistor)(has (q7 ?dp) (sign (negative ?sign)))))

(new-part (q8 ?dp)((type (q8 ?dp) virtual-bjt-transistor)(has (q8 ?dp) (sign (negative ?sign)))))

(new-part (sourcel. ?dp)((type (source? ?dp) current-source)))

(new-part (source? ?dp)((type (source? ?dp) current-source)))

(new-part (bias-q ?dp)((type (bias-q ?dp) virtual-bjt-transistor)(has (bias-q ?dp) (negative ?sign))))

(new-part (dl ?do) ((type (dl ?dp) diode)))(new-part (d2 ?dp) ((type (d2 ?dp) diode)))(new-part (load ?dp)

((type (load ?dp) differential-pair--load)));(has (load ?dp) resistive)

*Now connect them to the outside(connect (pos- it 7dp)(base (pos-q 7dp)) (collector (q6 ?dp)))

* coinet ( flo- it ?dp i(tiae ( iey q, 'dp)) (collector ( q8 ?dp))* connect (ot 7dp)(collector (q3 ?dp(() (12 (load ?dp)))

(connect ( neg-Ot 7?dp)(collector ( q4 ?d~p)) (tI (load ?dpf))

nciw the inside connect ions on poi I i e s ide(CunneCt (collector (pos-q 7dp(*miiiter (Q3 ?dp)))(connect (emitter (pos-q ?dp)) (L1 (sourcel))

(emitter (neg-q ?dp)) (base (bias-q ?dp)))(connect (base (q3 ?dp)) (collector (q5 ?dp))

(base (q5 ?dp)) (base (q6 ?dp)))U(connect (emitter (q5 ?dp)) (emitter (q6 ?dp))

(emitter (q7 ?dp)) (emitter (q8 ?dp))(t2 (source? 7dp)) (tl (dl ?dp)))

*now the inside connections on neg side(connect (collector (neg-q ?dp))(emitter (q4 ?dp)))(connect (base (q4 ?dp() (collector (q7 ?dp))

(base (q7 7dp)) (base (q8 ?dp)))

*bias connections(,ail-connect (tI (source? ?dp))(rail ?sign))(ral,-connect (t2 (sourcel 'dp))(rail (negative ?sign)))(connect (t2 (dl 'dp(((tl (d2 ?dp)))(connect (t2 (d2 ?dp)((emitter (bias-q ?dp)))(rail-connect (collector (bias-j ?do))(rail (negative ?sign)))

Propagating specifications to parts-(current (emitter (q5, ?dp)) ( (current (emitter (q6 ?dp))))

(~(current (emitter (q7 ?dp)l( (current (emitter (q8 ?dp))))(~ offset-voltage 7dp) simple-offset-voltage)

transconductance ?dp)(* (gin (pos-q ?dp)) (transresistance-factor (load ?dp))))

(~(bias-current ?dp)(+ (current (base (pos-q ?dp))) (current (collector (q6 ?dp)))))

*The offset current can be done by getting a delta-current from the*the load stage(~(offset-current ?dp)

(/(delta-current (load ?dp))(beta (pos-q ?dp))))

so that the slew rate can be calculated It must know this* (equat ion-with-variable-priority

((max (current (ot ?dp)))(* -2 (currzent (collector (pos-q ?dp)))))

(max (current (ot ?dp))))**output resistance

(equation-with- variable-priority(~(output-resistance ?dp)

* k// (ro (pos-q ?dp)) (ro (1.2 (load ?dpf)))((ro (pos-q ?dp)) (ro (t? (load ?dp))))))

(output-resistance ?dp)))

1.2.1 7 (p N oltagc D~rop NN ib Diode

(to-make-an ?vd cp-voltage-drop-with-diode;; Pattern(where (type ?vd complement-pair- input-voltage-drop)

(has ?vd (priority 1))(has ?vd (sign ?sign)))

*Parts:* (new-part (dl ?vd)

((type (dl ?vd) diode)(has (dl.?vd) (sign ?sign))))

I I It I' \OI I \(I I)R)I 'IIII O) I 90

(new-part (d2 ?vd)((type (d2 ?vd) diode)

(has (d2 ?vd) (sygn ?Sign))))Connect ions:

connect (it ?vd) (it (dI ?vd)))(connect (ot ?vd) (ot (d2 ?vd))) Sconnect (o (dl ?vd)) (it (d2 ?vd))))

I.2.1 Nl'Ib Iraniktor I)iode

*((to-make-a., ?d npn-trans-dlode

Pattern(where (type ?d diode)

(has ?d (priority 1))(has ?d (sign npn)))

New parts:(new-part (q ?d) S

((type (q ?d) virtual-bjt-transistor)(has (q ?d) (sign npn))))

Connections:(connect (it ?d) (base (q ?d)) (collector (q ?d)))(connect (ot ?d) (emitter (q ?d))))

1.2.1Q 1"NI' I ransktor I)iode

(to-make-an ?d pnp-trans-diode.: Pattern(where (type ?d diode)

(has ?d (priority 1)) 0(has ?d (sign pnp)))

New parts:(new-part (q 7d)

((type (q ?d) virtual-bjt-transistor)(has (q ?d) (sign pnp))))

.. Connections:(connect (it ?d) (base (q ?d)) (collector (q ?d))) S(connect (ot ?d) (emitter (q ?d))))

* !

* .0 ,-

1.3 IPrinii i Objects In the PhIraws (.rammiar

1.3.1 Simplu NI'N 10 1

(to make-an ?bjt s imple-iipn-bjit.Pattern to match:

(where (type ?bjt bjt)(rias ?bjt (sign npn))(terminal-device ?bjt)(device-parameter (beta 'bjt))(device-paramieter (gin ?bjt))(has ?bjt (priority 1))three-terminai-dee ice (base ?bjt)(eniitter ?bjt )(col lector ?bjt)))

(equation-with-variable-priority(~(cuirrent (collector ?bjt))(* (beta ?bjt) (current (base ?bjt))))

4 (current (collector ?bjt)))S(beta ?bjt) npn-beta)

(Qlkt (Lurrent (collector ?bjt))))

(ri(eaj((qt(cret(olco ?bjt)))

(// (ret ?bjt) (* 200. (current (collector ?bjt)))))

(ro ?bj t )) 0(0 (+ (current (collector ?bjt)) (current (base ?bjt))

(current (emitter ?bjt))))

1.3.2 Sim~ple rNP H~r

to-make-an ?bjt simple-pnp-bjt.!

(hs?bjt (sign-pnp))

(terminal-device ?bjt)(device-parameter (beta ?bjt))(dev ice-parameter (gin ?bjt))(has ?bjt (priority 1))(three-terminal-device (base ?bjt)(emitter ?bjt)(collector ?bjt)))

(equation-with-variable-priority(~(current (collector ?bjt))(- (beta ?bjt) (current (base ?bjt))))

(current (collector 'bjt))((beta 'bjt) pnp-beta)

V gi ? bj t(q/k t Il (current (collector ?bjt))))

(rpi ?bjt((// (beta 7bjt) (I q/kt -1 (current (collector ?bjt)))))

1 equat ion-with-variable-priority((ro ?bjt) (// -80- (current (collector ?bjt)))) pnp-ro

* (ro ?bjt)0 (+ (current (collector ?bjt)) (current (base ?bjt)) -

(current (emitter ?bjt)))))

I I ISt P R lil I A \I'\ IUI_

1.3.3 Super Ita NI'N IkJF

(to-make-an ?v-bjt super-beta-npn-bjt, Pattern to Match.(where (type ?bjt npn-bjt)

(terminal-device ?bjt)(device-parameter (beta ?bjt))

(device-parameter (gm ?bjt))(has ?bjt (priority 1))(three-terminal-device (base ?bjt)(emitter ?bjt)(collector ?bjt)))

( (current (collector ?bjt)) (I (beta ?bjt) (current (base ?bjt))))= (beta

7bjt) super-npn-beta)

(gm ?bjt, (0 q/kt (current (collector ?bjt))))= (rpi ?bjt) (// (beta ?bjt) (* q/kt (current (collector ?bjt)))))= (ro ?bjt) super-npn-ro)( 0 (* (current (collector ?bjt)) (current (base ?bjt))

(current (emitter ?bjt)))))

1.3.4 Standard Resistor

(to-make-an ?r standard-resistor., Pattern to match:(where (type ?r resistor)

(terininal-device ?r)(device-parameter (resistance ?r))Ihas ?r (priority I))(two-terminal-device (tl ?r)(t2 ?r)))

(: (voltage ?r* (current (tl ?r)) (resistance ?r)))

(= 0 (+ (current (tl ?r)) (current (t2 ?r)))))

1.3.5 Capacitor

(to-make-an ?c capacitor; Pattern to match:

(where (type 7c capacitor)

(terminal-device ?c)(device-parameter (capacitance ?c))(has ?c (priority 1))(two-terminal-device (tI ?c)(t2 ?c)))

C (current (ti ?c)))( current (t2 ?c)))

S