Activation Records (Introduction) Mooly Sagiv html://msagiv/courses/wcc03.html Chapter 6.3.

Activation Records(Introduction)

Mooly Sagiv

html://www.math.tau.ac.il/~msagiv/courses/wcc03.html

Chapter 6.3

Outline

• What is the problem?

• A possible structure of the activation records

• A simple stack machine

• Example compilation

The problem

• The compiler needs to allocate memory for variables

• Consistent with program semantics– Scope– Duration– Recursion

• Efficient (moderate runtime cost)• Solution?

Typical Virtual Memory Content

Lower addresses

static area

Stack

area

Heap

area

A Typical Stack Frame

Basic Compiler Phases

void main() {printf(“%d\n”, fact(3));}int fact(int n){ if (n==0) return 1; else return n * fact(n-1) ;}

Example Program

void main() {printf(“%d\n”, fact(3));}

Activation Record for main(before fact)

Administrative part

3SP

FP


Activation Record for main(after fact)

Administrative part

3

6 SP

FP


Activation Record for main(before printf)

Administrative part

6

x87 SP

FP

x87 “%d\n”

Stack Instructions

Instruction Actions

Push_Const c stack[--SP]=c

Push_Local i stack[--SP]=stack[FP+i]

Store_Local i stack[FP+i]=stack[SP++]

Add_Top2 stack[SP+1]+=stack[SP++]

Sub_Top2 stack[SP+1]-=stack[SP++]

Mul_Top2 stack[SP+1]*=stack[SP++]

Branch L PC = L;

Branch_Eq L T1= stack[SP++]; T2 = stack[SP++];

if (T1==T2) PC =L

JSR L stack[--SP] = FP; stack[--SP] = PC; FP=SP-1;PC =L

RTS T= stack[SP++]; PC=stack[SP++]; FP=stack[SP++]; stack[--SP]=T

WPop Stack[SP+1] = Stack[SP]


.global _main

L1: Push_Const 3

Push_Const 0

JSR _fact

WPop

Push_Const L2

JSR _printf

.data

L2 : “%d\n”

.end

Code Generated for main

Activation Record for fact

Administrative part

SP

FP

int fact(int n){ if (n==0) return 1; else return n * fact(n-1) ;}

n 3ret

FP+5

0

Code generated for fact


L4: Push_Constant 1

RTS

.global _fact

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L5: Push_Local 5

Push_Local 5

Push_Const 1

Subtr_Top 2

Push_Const 0

JSR _fact

WPop

Mult_Top2

RTS

.end

Execution of fact

Administrative part FP

n 3ret

FP+5

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1

RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS

main

SP

0

Execution of fact


n 3ret

FP+5

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

SP3

0

Execution of fact


n 3ret

FP+5

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

SP

3

0

0

Execution of fact


n 3ret

FP+5

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

SP

0

Execution of fact


n 3ret

FP+5

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

SP3

0

Execution of fact


n 3ret

FP+5

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

3

SP3

0

Execution of fact


n 3ret

FP+5

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

3

3

SP1

0

Execution of fact


n 3ret

FP+5

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

3

2 SP

0

Execution of fact


n 3ret

FP+5

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

3

2

SP

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

SP

Administrative part

n

ret

3

3

Administrative part

n

ret

2

2

n

ret

1

0

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

SP

Administrative part

n

ret

3

3

Administrative part

n

ret

2

2

Administrative part

0

n

ret

1

1

0

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

SP

Administrative part

n

ret

3

3

Administrative part

n

ret

2

2

Administrative part

n

ret

1

1

Administrative part

n

ret

0

1

0

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

SP

Administrative part

n

ret

3

3

Administrative part

n

ret

2

2

Administrative part

0

1

n

ret

1

1

0

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1

RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 JSR _fact Push_Const 0 WPop Mult_Top2 RTS

main

Administrative part

n

ret

3

3

Administrative part

n

ret

2

2

Administrative part

1

n

ret

1

1

SP

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

Administrative part

n

ret

3

3

Administrative part

n

ret

2

2

Administrative part

n

ret

1

1 SP

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

Administrative part

n

ret

3

3

Administrative part

n

ret

2

2

n

ret

1

1 SP

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

Administrative part

n

ret

3

3

Administrative part

n

ret

2

2

n 1 SP

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

Administrative part

n

ret

3

3

Administrative part

n

ret

2

2 SP

0

0

FP

L3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

Administrative part

n

ret

3

3

n

ret

2

2 SP

0

FPL3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

Administrative part

n

ret

3

3

2 SP

0

FPL3: Push_Local 5

Push_Const 0

Branch_Eq L4

Branch L5

L4: Push_Constant 1


main

Administrative part

n

ret

3

6 SP

0

FPmain

n

ret

3

6 SP

L1: Push_Const 3

Push_Const 0

JSR _fact

WPop

Push_Const L2

JSR _printf

FPmain

6 SPL1: Push_Const 3

Push_Const 0

JSR _fact

WPop

Push_Const L2

JSR _printf

FPmain

6

SP

L1: Push_Const 3

Push_Const 0

JSR _fact

WPop

Push_Const L2

JSR _printf

x87

main

6_printf

x87

FPAdministrative part

SP

x87

Code For Register Machine

Register Instructions

Instruction Actions

Load_Const c, Ri Ri=c

Load_Local c(Ri), Rj Rj=*(Ri+c)

Store_Local Ri, c(Rj) *(Rj+c)=Ri

Add_Constant c, Ri Ri = Ri+c

Add_Reg Ri, Rj Rj = Rj+Ri

Sub_Constant Ri, c Ri = Ri - c

Sub_Reg Ri, Rj Rj =Rj-Ri

CMP Ri, Rj CC = Ri -Rj

CMP_Const C, Ri CC = Ri - C

Branch L PC = L;

Branch_EQ L if (CC==EQ) PC =L

JSR L *(--SP) = FP; *(--SP) = PC; FP=SP-1;PC =L

RTS PC=*(SP++); FP=*(SP++)


.global _main

Add_Constant -K1, SP

L1: Load_Const 3, R0

JSR _fact

Load_Reg R0, R1

Load_Const L2, R0

JSR _printf

Add_Constant K1, SP RTS

.data

L2 : “%d\n”

.end

Register Code Generated for main

Register Code generated for fact


L4: Load_Constant 1, R0 Goto L6

.global _fact

Add _Constant -K2, SP L3: Cmp_Constant R0, 0

Branch_Eq L4

Branch L5

L5: Store_Local R0, 5(FP)

Sub_Constant 1, R0

JSR _fact Load_Local 5(FP), R1

Mult_Reg R1, R0

Goto L6

L6: Add_Constant K2, SP

RTS

.end

Summary

• Activation records is a runtime data structure

• Updated by code generated by the compiler

• Support from machine instruction

Activation Records (Introduction) Mooly Sagiv html://msagiv/courses/wcc03.html Chapter 6.3.

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Transcript of Activation Records (Introduction) Mooly Sagiv html://msagiv/courses/wcc03.html Chapter 6.3.