References

[1] Anuruddh Sharma and Mukti Awad,July 2012 “8-Bit Risc Processor Using

Harvard Architecture” ISSN: 2278 – 1323 International Journal of Advanced

Research in Computer Engineering & Technology Volume 1, Issue 5, July 2012

[2] Vijay R. Wadhankar and Vaishali Tehre “ A FPGA Implementation of a

RISC Processor for Computer Architecture” National Conference on Innovative

Paradigms in Engineering & Technology (NCIPET-2012) Proceedings published

by International Journal of Computer Applications® (IJCA)

[3] Nidhi Maheshwari “A 16-Bit Fully Functional Single Cycle Processor”

International Journal of Engineering Science and Technology (IJEST)

[4] Samiappa Sakthikumaran,S.Salivahanan and V.S.Kaanchana Bhaaskaran ,

June 2011, “16-Bit RISC Processor Design For Convolution Application”,IEEE

International Conference on Recent Trends In Information Technology, pp.394-

397.

[5] Sivarama P.Dandamudi ,”A Guide To RISC Processor For Programmers And

Engineers”, Springer.

[6] Seung PyoJung, Jingzhe Xu, Donghoon Lee, Ju Sung Park, 2008, “Design

And Verification Of 16 Bit RISC Processor”, International SOC Design

Conference.

[7] Xiaoping Huang,Xiaoya Fan, Shengbing Zhang , 2008,“Design and

Performance Analysis of One 32-bit Dual Issue RISC Processor for Embedded

Application”.

[8] Luker, Jarrod D., Prasad, Vinod B., “RISC system design in an FPGA”,

MWSCAS 2001.

Acknowledgement

I offer my sincere thanks and gratitude towards my project (Dissertation seminar) guide

Prof. Mrs. S. V. Verma and H.O.D.(Elex. & comm.. Engg.) Dr. Sayyad Ajij D., Principal

Dr.P.H.Waghodekar for there valuable guidance throughout preparation of this seminar.

There valuable suggestions & advices helped me a lot while preparation of this seminar. I

thank for providing all necessary facilities needed in completion of this seminar.

I would also like to thank the college for providing the required magazines, books and

access to the Internet for collecting information related to the Seminar.

Last but not the least, I thank my friends and well-wishers, to whom I am indebted for

their constant help, encouragement and without whom this seminar would not have been

a success.

Dinesh B. Borude,M. E (Embedded System)

2nd year MIT, Aurangabad