Access IC Lab Overview & 103-2 Undergraduate...

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Access IC Lab Overview &

103-2 Undergraduate Projects

吳安宇教授

Date: 2015/01/20

URL: http://access.ee.ntu.edu.tw (slide 會放在網頁)

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

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Access Lab Profile/Overview

Location: EE building II (Rm. 232, 14坪)

Manpower: 6 Ph.D. students

14 MS students

Equipment:

3 Sun Blade 2000 Workstations

2 Sun Ultra 60 Workstations

24 PC and 6 Notebooks for students


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有關指導教授 2015 IEEE Fellow

99年度「中國電機工程學會傑出電機工程教授獎」 96年8月1日借調工研院系統晶片中心副主任 95年度台大共同教育委員會 - 「教學優良獎」 95年度第七屆旺宏金矽獎-半導體設計與應用大賽：「指導教授獎」(應用組、設計組)

94年8月1日升等教授 94年度國科會「吳大猷先生紀念獎」（微電子學門唯一提名） 94年度「國立臺灣大學傅斯年獎（肯定 SCI 學術期刊論文發表之學術貢獻）」 93年度「中國電機工程學會優秀青年電機工程師獎」 93年度「中國工程師學會工程論文獎」 93年度第四屆旺宏金矽獎-半導體設計與應用大賽：「最佳指導教授獎」 92年度「旺宏電子青年教授講座」 86、87、88、89年度國科會甲等研究獎勵共四次 88年度教育部「VLSI與系統設計」教育改進計畫佳作 (課程：可程式性信號處理器專題)

國科會「微電子學門」計畫複審委員教育部 SOC 聯盟「系統晶片設計實驗」總主持人第 15 屆 VLSI/CAD Symposium 議程主席我國 IA 旗鑑產品推行小組規格起草委員經濟部技術處「業界開發產業技術計畫」審查委員經濟部工業局「審核係屬科技事業暨產品或技術開發成功且具市場性意見書評估委員會」專案委員 Associate Editor：IEEE Transactions on VLSI Systems

Associate Editor：EURASIP Journal on Applied Signal Processing

Technical Program Committee Member of Major IEEE International Conferences: ICIP, SiPS, AP-ASIC, ISCAS, ISPACS, ICME, APCCAS, and ASIC/SOC.


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指導學生獲獎第一屆全國SOC系統晶片設計比賽

軟硬體發展平台組「優等獎」

SoC晶片組「優等獎」

94年度中國工程師學會全國大學部工程論文競賽

電資組「特優」

94年度台灣積體電路設計學會「博士論文獎」

94 & 95學年度電子所年度「最佳碩士論文獎」

2010, 2014 IEEE VLSI-DAT 「最佳會議論文獎」

100年度大專學生研究計畫研究創作獎

103年度數位電路組最佳論文獎

103年度IEEE Taipei Section 博士論文獎

旺宏金矽獎-半導體設計與應用大賽：

第四屆「優等獎」及「新手獎」

第五屆設計組-設計組「最佳創意獎」

第七屆設計組-應用組「銅牌獎」、設計組「優勝」、

設計組「銅牌獎」、設計組「最佳創意獎」

第八屆設計組「優勝獎」x2

第九屆設計組「金獎」、設計組「最佳創意獎」、設計

組「銅獎」

2004,2005,2007,2008,2009,2010 國家晶片系統設計

中心「優良晶片」設計

2007鳳凰盃IC設計競賽數位IC組「優等獎」

大學院校積體電路設計競賽：

94,95,96,98學年度研究所組標準單元設計「佳作」

99,100學年度研究所組標準單元設計「特優」「佳作」

101學年度研究所組標準單元設計「特優」「優等」

102學年度研究所組標準單元設計「優等」「完成」


P5

From 3C to ICS

Computer

Content/

ConsumerCommunication

3C

VLSI

DSPCommunication

& Networking

Access

lab.

3C Access IC Lab Focus

ICS: Integrated Circuits and Systems


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Topics

I. 5G行動通訊

(Key Enabling Technology for 5G Mobile Communications)

II. 具錯誤恢復機制之多核心系統設計

(Error-Resilient Multi-core System)


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5G Service Vision & Trend

Immersive

Experience

Ubiquitous

Connectivity

Intuitive

Remote AccessEverything on

Cloud

Desktop-like

experience on the go

Lifelike media

everywhere

An intelligent web of

connected things

Realtime remote

control of machines


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5G Key Performance Targets Providing Gigabit Experience to Users Anywhere

Capacity Increase More than 1000x over 4G.


P9

mmWave is the highest radio frequency band in practical

use today.

Candidates for large chunks of contiguous spectrum

Microwave Millimeter-Wave (mmWave)

mmWave Technology Enables 5G


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mmWave Advantage

How Can We Get There ?

Bandwidth & Throughput (B)

Densification (D)

Spectrum Efficiency (S)

Inherent Shorter Range &

Beamsteering Mitigate

Interference

mmWave Bands Support

Multi-Gbps Rates

Beamsteeing & MU-MIMO

Techniques Support PtP & PtMP

In Same Frequency Band

Capacity Increase = D x B x S > 1000


P11

mmWave Small Cell with Massive MIMO

vs. Modern LTE Femto Cell


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2014.10.14

Samsung Presents 5G Demo of 7.5Gbps with

mmWave Beamformer Technology

Both & Have

Greatly Focused on this Topic


P13

Topics : Advanced Hybrid Massive MIMO

Design for mmWave System


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5G行動通訊

適合對象:

對通訊系統有興趣的同學

願意投入研究的同學

條件:

對通訊(懂消息理論者佳) 、線性代數有基礎

懂得撰寫Matlab程式

內容:

Beamforming Alignment Protocol

Hybrid Beamforming Engine Design

Massive MIMO CSI Acquisition


P15

Topics

I. 5G行動通訊

(Key Enabling Technology for 5G Mobile Communications)

II. 具錯誤恢復機制之多核心系統設計

(Error-Resilient Multi-core System)


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Challenge of Reliable Green Computing

Circuits and Systems

Conventional Reliable System

DSP and ASIP

Good Performance on Single Integrated Chip

Reliable System Features• Redundancy for protection• Algorithmic noise tolerance• Built-in soft error resilience• Self-test/ failure prediction

Error Resilient System Architecture(Multi-core system and 3D-IC)

TechnologyAdvance

Challenge 1.

Voltage Scaling Variation

Challenge 3.Challenge 4:Faulty InterconnectionOverheat Problem

Challenge 2.Process Variation

[1]


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Why Error Resilient

Statistical Error Resiliency (2013, SIPS, Shanbhag) [2]

Robustness (1000x) Energy efficiency (3x-6x)

Logic level error resiliency (LLER): NMR, Cascaded NMR

Micro-architecture error resiliency (MLER): ERSA

System level error resiliency (SLER): ANT, Soft-NMR, SSNoC, LP

[2]

2009~ 2011~

NMR: N-modular redundancy

ERSA: Error-resilient system

architecture

ANT: algorithmic noise tolerance

SSNoC: stochastic sensor

network-on-chip

LP: likelihood processing


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Advantage of

System Level Error Resilient

No worst-case protection but error resiliency (2013, ICASSP, Shanbhag) [2]

Stochastic applications

Energy efficient

Inherent resiliency to errors (2012, ERSA) [1]

Iterative computation

Probabilistic representation

Input from the real world

Cognitive resilience

Recognition, mining, and synthesis (RMS) applications, media

processing, immersive computing [2]

Evaluation through BER, probability of detection, PSNR

Admit approximate error correct/compensation


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A1: Algorithmic Error Resilience for RMS

Applications (LDPC Decoder)

Goal: Identify algorithmic invariants for error detection

Sanity check for computational errors by algorithm-specific method

Provide a reduced overheads

and algorithm-aware method10

-1.5

10-1.4

10-1.3

10-1.2

10-1.1

10-6

10-5

10-4

10-3

10-2

10-1

100

Raw BER

Cod

ed B

ER

Soft error rate = 10-3

in both CNU and BNU


in both CNU and BNU

with protected BNU


in both CNU and BNU

with protected CNU


in both CNU and BNU

with protected BNU and CNU

Error-free


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A2: Algorithmic Error Resilience for RMS

Applications (Stereo Matching)

Goal: Identify algorithmic invariants for error detection

Sanity check for computational errors by algorithm-specific method

Data input

Data output

w/ hw error

Error correct


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B: Advanced Core Redundancy

A more general method to deal with more actual errors

Core-level error resilience

Exploit the inherent core redundancy for error-resilience design [3]

good

bad

Op

era

tin

g e

nviro

nm

en

t How to determine the number

of coupled cores and which

cores should be coupled

How to evaluate the

vulnerability of

different operation in

different environment


P22

B: Advanced Core Redundancy

Many-core Virtual Platform

Online Tracking of

System Reliability

E1 E2 E3 E4

T1 N11 N12

T2 N21

T3

T4

……

Task

Environment

Dynamic

Adjustment

E1 E2 E3 E4

T1 N11 N12

T2 N21

T3

T4

…Environment

Reliability-Aware

Task Allocation

…

Ta

sk C

lassific

ation


P23

Access CERES Project Topics

Error handling and error-resilient algorithms

Application-specific enhancements

Asymmetric reliability in multi-core architectures

Task allocation algorithm

Combination of Spatial and Temporal Redundancy

Error detection

for specific

application

Advanced

core

redundancy

Topic B

Topic A

Reliability-Aware

Task Allocation

How to detect and

control system

errors?


P24

Error-Resilient Multi-core System

適合對象:

對多核心系統有興趣的同學

未來想加入實驗室的同學

條件:

有想法、熱愛討論的同學

一顆充滿熱情的心

內容:

學習錯誤容忍系統設計

學習Task allocation algorithm

熟悉虛擬多核心平台模擬環境


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Contact Information

Feel free to contact with 吳安宇教授Office: 電機二館441室，Phone:(02) 3366-3641

Email: [email protected]

直接連絡 Access IC Lab 學長實驗室: 電機二館，Room 232 (EE2-232)

Phone: (02)3366-3700, ext.232

李懷霆: [email protected]

Lab Website http://access.ee.ntu.edu.tw/


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Access Lab 花東創意研究研討會

小蒙牛送舊迎新

ACCESS IC LAB

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