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Accelerating Precise Race Detection Using Commercially-Available Hardware Transactional Memory...
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Accelerating Precise Race Detection Using Commercially-Available Hardware
Transactional Memory Support
Serdar TasiranKoc University, Istanbul, TurkeyMicrosoft Research, Redmond
Hassan Salehe Matar, Ismail Kuru, Koc University, Istanbul, Turkey
Roman DementievIntel, Munich, Germany
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This Work• Races are bad
– Cause non-deterministic execution, sequential consistency violations– Symptomatic of higher-level programming errors– Difficult to catch and debug
• Precise, dynamic detection of races is good– Useful, timely debugging information– No false alarms
• But dynamic race detection is too expensive: 10X for Java, 100X for C/C++• Dynamic race detection slowdown
– Instrumentation: Detecting memory and synchronization accesses– Analyis: The race detection algorithm
• Computation: Update, compare vector clocks, locksets• Synchronization: Synchronize vector clocks, locksets• This work: Reduce this using Intel Hardware
Transactional Memory support
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What this talk is NOT about• This work is about
– using Intel hardware transactional memory support to make dynamic race detection in lock-based applications faster
• This work is not about– replacing lock-based synchronization in applications
with hardware transactional memory instead– race detection for applications that use transactional memory (and
maybe locks) – Using hardware transactional memory purely for
conflict detection/avoidance• Are there conflicting accesses to the same address by two different
threads “at the same time”?although our experimental results will give some indication of how successful these approaches might be
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This Work in Context• Goldilocks: PLDI ‘07, CACM ’10
– DataRaceException is a good idea for Java– Needs to be supported by continuous, precise run-time happens-
before race detection– Later work, by others: Hardware support for concurrency exceptions
• Why precise: Tools with too many false alarms do not get used• Why dynamic: A concrete error trace is very useful for debugging• Why online (vs post-mortem):
– To support accessing race information within the program• FastTrack: Faster than Goldilocks, state of the art
– But still too expensive: 10X for Java, 100X for C/C++
• Goal: Make precise race detection more practical using only mainstream hardware and software.
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This Work in Context• Our previous efforts:
– Parallelize race detection using the GPU• Faster than dynamic race detection on the CPU only• Checking lags behind application• Event buffer between CPU and GPU the bottleneck
– Parallelize race detection using software TM running on sibling threads• Not faster• Synchronization cost between application and sibling threads
offsets benefit of parallelization• This work:
– Had access to Intel TSX prototype before it was commercially available– Experimented with using hardware TM support to make analysis
synchronization faster• Result: Up to 40% faster compared to lock-based version of FastTrack
on C programs.
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Happens-before race detection
Lock(L) read X
write XUnlock(L)
Lock(L)write X
Unlock(L)
Lock(L)write X
Unlock(L)
Var X = 1;Thread 1 Thread 2
Prog
ram
-ord
erPr
ogra
m-o
rder Prog
ram
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Synchronizes-with
Happens-before
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Happens-before race detection
Lock(L) read X
write XUnlock(L)
write XUnlock(L)
Lock(L)write X
Unlock(L)
Var X = 1;Thread 1 Thread 2
xrace
Prog
ram
-ord
erPr
ogra
m-o
rder Prog
ram
-ord
er
Synchronizes-with
Happens-before
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Anatomy of Dynamic Race Detection
Memory access or synchronization operation
Dynamic instrumentation - detects access, - calls race-detection function: FastTrack_Process_Access(addr, thrd);
FastTrack_Process_Access(addr, thrd); - Read analysis state for addr - Determine if there is a race - Update analysis state
x = 3;PIN
FastTrack
Thread1
Thread2
Thread3
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The FastTrack Algorithm
Figure taken from “FastTrack: Efficient and Precise Dynamic Race Detection” Flanagan and Freund, PLDI ‘07
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The FastTrack Algorithm
Clock vectors
Figure taken from “FastTrack: Efficient and Precise Dynamic Race Detection” Flanagan and Freund, PLDI ‘07
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The FastTrack Algorithm
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Code snippet fromFastTrack implementationfor Java on GitHub
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Time Spent in Additional Analysis Synchronization
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IDEA• Intel TSX
– Hardware support for atomically-executed code regions– Optimistic concurrency– Available on mainstream processors
• Use Intel TSX to ensure atomicity of FastTrack code blocks– Instead of lock-protected regions
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Intel TSX instructions
• Hardware instructions to tell processor to start and transaction
• Processor hardware ensures transactional memory semantics
TSX_BEGIN;
Sequence ofinstructions
TSX_END;
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lock (L1) FastTrack_Process_Lock(L1) temp = acc TSX_BEGIN; FastTrack_Process_Read(acc) TSX_END;
temp = temp +100 acc = temp TSX_BEGIN; FastTrack_Process_Write (acc) TSX_END;
FastTrack_Process_Unlock(L1) Unlock (L1)
After instrumentation
lock (L1)
temp = acctemp = temp + 100acc = temp
Unlock (L1)
Before instrumentation
Instrumentation
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lock (L1) FastTrack_Process_Lock(L1)
TSX_BEGIN; temp = acc FastTrack_Process_Read(acc)
temp = temp +100 acc = temp FastTrack_Process_Write (acc) TSX_END;
FastTrack_Process_Unlock(L1) Unlock (L1)
After instrumentation
lock (L1)
temp = acctemp = temp + 100acc = temp
Unlock (L1)
Before instrumentation
Also Sound Instrumentation
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Lock-based vs TSX-based FastTrack (4 threads, 4 cores)
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Lock-based vs TSX-based FastTrack (8 threads, 4 cores)
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TSX Speedup vs # of Application Threads
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For fun: Comparison with single-global-lock-based FastTrack
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Speedup over fine-grain lock-based FastTrack vs TSX block size
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• TSX-based FastTrack up to 40% faster thanlock-based FastTrack for C benchmarks
• Future work– Integrate with PIN dynamic instrumentation– Randomize TSX block boundaries– Race avoidance in legacy x86 binaries
Conclusions, Future Work