ACADEMIC YEAR : COURSE : IV B.Tech., (II-Sem.,)- Section A ...
13
LESSON PLAN ACADEMIC YEAR : 2012-13 COURSE : IV B.Tech., (II-Sem.,)- Section A BRANCH : Electronics and Communication Engineering SUBJECT : Digital Design through Verilog (Code: L0422) FACULTY : Y.AMAR BABU UNIT S.No. Date-I Topic Date-II Remarks UNIT-I (Introduction to Verilog) 1. 19-11-12 Verilog as HDL, Levels of Design Description 2. 20-11-12 Concurrency, Simulation and Synthesis, Functional Verification 3. 22-11-12 Tasks, System Programming Language Interface (PLI) , Module 4. 23-11-12 Simulation and Synthesis Tools, Test Benches 5. 24-11-12 Tutorials1 6. 26-11-12 LANGUAGE CONSTRUCTS AND CONVENTIONS :Introduction, Keywords, Identifiers, White Space 7. 29-11-12 Data Types, Scalars and Vectors 8. 30-11-12 Parameters, Memory, Operators ,System Tasks 9. 3-12-12 Tutorials2 UNIT-II (Gate level Modeling) 10. 4-12-12 Introduction, AND Gate Primitive, Module Structure 11. 6-12-12 Other Gate Primitives, Illustrative Examples, Tri- State Gates 12. 7-12-12 Array of Instances of Primitives, Additional Examples 13. 8-12-12 Design of Flip flops with Gate Primitives 14. 10-12-12 Delays, Strengths and Contention Resolution 15. 11-12-12 Net Types, Design of Basic Circuits 16. 13-12-12 Tutorials3 UNIT-III (Behavioral Modeling) 17. 14-12-12 Introduction, Operations and Assignments, Functional Bifurcation 18. 15-12-12 Initial Construct, Always Construct, Multiple Always ,Examples 19. 17-12-12 Assignments with Delays, Wait construct 20. 18-12-12 Blocks, Designs at Behavioral Level 21. 20-12-12 Blocking and Non blocking Assignments 22. 21-12-12 The case statement, 23. 22-12-12 iƒ and iƒ-else constructs, assign-deassign construct, 24. 24-12-12 repeat construct, for loop, the disable construct 25. 26-12-12 While loop, forever loop, parallel blocks, force- release construct, Event 26. 27-12-12 Tutorials4 27. 28-12-12 Tutorials5 UNIT-IV (Data flow and Switch level Modeling) 28. 29-12-12 Introduction, Continuous Assignment Structures, Delays and 29. 31-12-12 Assignment to Vectors, Operators 30. 1 -1-13 Tutorials6 31. 3-1-13 Introduction, Basic Transistor Switches, CMOS Switch, Bi-directional Gates 32. 4-1-13 Time Delays with Switch Primitives 33. 5-1-13 Instantiations with Strengths and Delays 34. 7-1-13 Strength Contention with Trireg Nets, Exercises
Transcript of ACADEMIC YEAR : COURSE : IV B.Tech., (II-Sem.,)- Section A ...
LESSON PLAN
ACADEMIC YEAR : 2012-13 COURSE : IV B.Tech., (II-Sem.,)- Section A BRANCH : Electronics and Communication Engineering SUBJECT : Digital Design through Verilog (Code: L0422) FACULTY : Y.AMAR BABU
UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-I
(I
ntr
od
uct
ion
to
Ver
ilo
g)
1. 19-11-12 Verilog as HDL, Levels of Design Description
2. 20-11-12 Concurrency, Simulation and Synthesis, Functional
Verification
3. 22-11-12 Tasks, System Programming Language Interface
(PLI) , Module
4. 23-11-12 Simulation and Synthesis Tools, Test Benches
5. 24-11-12 Tutorials1
6. 26-11-12 LANGUAGE CONSTRUCTS AND CONVENTIONS
:Introduction, Keywords, Identifiers, White Space
Characters, Comments, Numbers, Strings, Logic
Values, Strengths
7. 29-11-12 Data Types, Scalars and Vectors
8. 30-11-12 Parameters, Memory, Operators ,System Tasks
9. 3-12-12 Tutorials2
UN
IT-I
I (G
ate
lev
el M
od
elin
g) 10. 4-12-12 Introduction, AND Gate Primitive, Module Structure
11. 6-12-12 Other Gate Primitives, Illustrative Examples, Tri-
State Gates
12. 7-12-12 Array of Instances of Primitives, Additional
Examples
13. 8-12-12 Design of Flip flops with Gate Primitives
14. 10-12-12 Delays, Strengths and Contention Resolution
15. 11-12-12 Net Types, Design of Basic Circuits
16. 13-12-12 Tutorials3
UN
IT-I
II
(Beh
avio
ral
Mo
del
ing
)
17. 14-12-12 Introduction, Operations and Assignments,
Functional Bifurcation
18. 15-12-12 Initial Construct, Always Construct, Multiple
Always ,Examples
19. 17-12-12 Assignments with Delays, Wait construct 20. 18-12-12 Blocks, Designs at Behavioral Level 21. 20-12-12 Blocking and Non blocking Assignments 22. 21-12-12 The case statement,
Simulation Flow
23. 22-12-12 iƒ and iƒ-else constructs, assign-deassign construct, 24. 24-12-12 repeat construct, for loop, the disable construct 25. 26-12-12 While loop, forever loop, parallel blocks, force-
release construct, Event
26. 27-12-12 Tutorials4 27. 28-12-12 Tutorials5
UN
IT-I
V
(Dat
a fl
ow
an
d
Sw
itch
lev
el
Mo
del
ing
)
28. 29-12-12 Introduction, Continuous Assignment Structures,
Delays and
Continuous Assignments
29. 31-12-12 Assignment to Vectors, Operators 30. 1 -1-13 Tutorials6 31. 3-1-13 Introduction, Basic Transistor Switches, CMOS
Switch, Bi-directional Gates
32. 4-1-13 Time Delays with Switch Primitives 33. 5-1-13 Instantiations with Strengths and Delays 34. 7-1-13 Strength Contention with Trireg Nets, Exercises
35. 8-1-13 Tutorials7 UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-V
(S
yst
em T
ask
, F
un
ctio
ns,
UD
Ps)
36. 10-1-13 Introduction, Parameters, Path Delays, Module
Parameters
37. 11-1-13 System Tasks and Functions
38. 17-1-13 File-Based Tasks and Functions
39. 18-1-13 Compiler Directives, Hierarchical Access, General
Observations, Exercises
40. 19-1-13 Tutorials8
41. 29-1-13 Introduction, Function, Tasks
42. 31-1-13 User- Defined Primitives (UDP)
43. 1-2-13 FSM Design (Moore and Mealy Machines)
44. 2-2-13 FSM Design (Moore and Mealy Machines)
45. 4-2-13 Tutorials9
UN
IT-V
I (D
igit
al D
esig
n w
ith
SM
Ch
arts
)
46. 5-2-13 State Machine Charts, Derivation of SM Charts
47. 7-2-13 State Machine Charts
48. 8-2-13 Realization of SM Charts
49. 11-2-13 Realization of SM Charts
50. 12-2-13 Implementation of the Dice Game
51. 14-2-13 Alternative realizations for SM Charts using
Microprogramming
52. 15-2-13 Microprogramming
53. 16-2-13 Linked State Machines
54. 18-2-13 Tutorials10
UN
IT-V
II
(Des
ign
ing
w
ith
FP
GA
s,
CP
LD
s)
55. 19-2-13 Xilinx 3000 Series FPGAs
56. 21-2-13 Designing with FPGAs
57. 22-2-13 Designing with FPGAs 58. 23-2-13 Using a One-Hot State Assignment 59. 25-2-13 Altera Complex Programmable Logic Devices
(CPLDs)
60. 26-2-13 Altera CPLDs 61. 28-2-13 Altera FLEX 10K Series CPLDs 62. 1-3-13 Altera FLEX 10K Series CPLDs 63. 2-3-13 Tutorials11
UN
IT-V
III
(Ver
ilo
g M
od
els)
64. 4-3-13 Static RAM Memory 65. 5-3-13 A simplified 486 Bus Model 66. 7-3-13 Interfacing Memory to a
Microprocessor Bus
67. 8-3-13 Interfacing Memory to a
Microprocessor Bus
68. 11-3-13 UART Design 69. 12-3-13 UART Design 70. 14-3-13 Design of Microcontroller CPU 71. 15-3-13 Design of Microcontroller CPU 72. 16-3-13 Tutorials12
Ad
van
ced
To
pic
s
73. 18-3-13 System Verilog 74. 19-3-13 Verilog A 75. 21-3-13 Verilog AMS 76. 22-3-13 Advanced FPGA Architectures 77. 23-3-13 Advanced FPGA Architectures
Total
Signature of Faculty Signature of HOD
LESSON PLAN
ACADEMIC YEAR : 2012-13 COURSE : IV B.Tech., (II-Sem.,)- Section B BRANCH : Electronics and Communication Engineering SUBJECT : Digital Design through Verilog (Code: L0422) FACULTY : Y.AMAR BABU
UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-I
(I
ntr
od
uct
ion
to
Ver
ilo
g)
1. 20-11-12 Verilog as HDL, Levels of Design Description
2. 21-11-12 Concurrency, Simulation and Synthesis, Functional
Verification
3. 22-11-12 Tasks, System Programming Language Interface
(PLI) , Module
4. 23-11-12 Simulation and Synthesis Tools, Test Benches
5. 24-11-12 Tutorials1
6. 28-11-12 LANGUAGE CONSTRUCTS AND CONVENTIONS
:Introduction, Keywords, Identifiers, White Space
Characters, Comments, Numbers, Strings, Logic
Values, Strengths
7. 29-11-12 Data Types, Scalars and Vectors
8. 30-11-12 Parameters, Memory, Operators ,System Tasks
9. 1-12-12 Tutorials2
UN
IT-I
I (G
ate
lev
el M
od
elin
g) 10. 4-12-12 Introduction, AND Gate Primitive, Module Structure
11. 5-12-12 Other Gate Primitives, Illustrative Examples, Tri-
State Gates
12. 6-12-12 Array of Instances of Primitives, Additional
Examples
13. 7-12-12 Design of Flip flops with Gate Primitives
14. 11-12-12 Delays, Strengths and Contention Resolution
15. 12-12-12 Net Types, Design of Basic Circuits
16. 13-12-12 Tutorials3
UN
IT-I
II
(Beh
avio
ral
Mo
del
ing
)
17. 14-12-12 Introduction, Operations and Assignments,
Functional Bifurcation
18. 15-12-12 Initial Construct, Always Construct, Multiple
Always ,Examples
19. 18-12-12 Assignments with Delays, Wait construct 20. 19-12-12 Blocks, Designs at Behavioral Level 21. 20-12-12 Blocking and Non blocking Assignments 22. 21-12-12 The case statement,
Simulation Flow
23. 22-12-12 iƒ and iƒ-else constructs, assign-deassign construct, 24. 26-12-12 repeat construct, for loop, the disable construct 25. 27-12-12 While loop, forever loop, parallel blocks, force-
release construct, Event
26. 28-12-12 Tutorials4 27. 29-12-12 Tutorials5
UN
IT-I
V
(Dat
a fl
ow
an
d
Sw
itch
lev
el
Mo
del
ing
)
28. 1-1-13 Introduction, Continuous Assignment Structures,
Delays and
Continuous Assignments
29. 2-1-13 Assignment to Vectors, Operators 30. 3 -1-13 Tutorials6 31. 4-1-13 Introduction, Basic Transistor Switches, CMOS
Switch, Bi-directional Gates
32. 5-1-13 Time Delays with Switch Primitives 33. 8-1-13 Instantiations with Strengths and Delays 34. 9-1-13 Strength Contention with Trireg Nets, Exercises
35. 10-1-13 Tutorials7 UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-V
(S
yst
em T
ask
, F
un
ctio
ns,
UD
Ps)
36. 11-1-13 Introduction, Parameters, Path Delays, Module
Parameters
37. 16-1-13 System Tasks and Functions
38. 17-1-13 File-Based Tasks and Functions
39. 18-1-13 Compiler Directives, Hierarchical Access, General
Observations, Exercises
40. 19-1-13 Tutorials8
41. 29-1-13 Introduction, Function, Tasks
42. 30-1-13 User- Defined Primitives (UDP)
43. 31-1-13 FSM Design (Moore and Mealy Machines)
44. 1-2-13 FSM Design (Moore and Mealy Machines)
45. 2-2-13 Tutorials9
UN
IT-V
I (D
igit
al D
esig
n w
ith
SM
Ch
arts
)
46. 5-2-13 State Machine Charts, Derivation of SM Charts
47. 6-2-13 State Machine Charts
48. 7-2-13 Realization of SM Charts
49. 8-2-13 Realization of SM Charts
50. 12-2-13 Implementation of the Dice Game
51. 13-2-13 Alternative realizations for SM Charts using
Microprogramming
52. 14-2-13 Microprogramming
53. 15-2-13 Linked State Machines
54. 16-2-13 Tutorials10
UN
IT-V
II
(Des
ign
ing
w
ith
FP
GA
s,
CP
LD
s)
55. 19-2-13 Xilinx 3000 Series FPGAs
56. 20-2-13 Designing with FPGAs
57. 21-2-13 Designing with FPGAs 58. 22-2-13 Using a One-Hot State Assignment 59. 23-2-13 Altera Complex Programmable Logic Devices
(CPLDs)
60. 26-2-13 Altera CPLDs 61. 27-2-13 Altera FLEX 10K Series CPLDs 62. 28-2-13 Altera FLEX 10K Series CPLDs 63. 1-3-13 Tutorials11
UN
IT-V
III
(Ver
ilo
g M
od
els)
64. 2-3-13 Static RAM Memory 65. 5-3-13 A simplified 486 Bus Model 66. 6-3-13 Interfacing Memory to a
Microprocessor Bus
67. 7-3-13 Interfacing Memory to a
Microprocessor Bus
68. 8-3-13 UART Design 69. 12-3-13 UART Design 70. 13-3-13 Design of Microcontroller CPU 71. 14-3-13 Design of Microcontroller CPU 72. 15-3-13 Tutorials12
Ad
van
ced
To
pic
s
73. 16-3-13 System Verilog 74. 19-3-13 Verilog A 75. 20-3-13 Verilog AMS 76. 21-3-13 Advanced FPGA Architectures 77. 22-3-13 Advanced FPGA Architectures
Total
Signature of Faculty Signature of HOD
LESSON PLAN
ACADEMIC YEAR : 2012-13 COURSE : IV B.Tech., (II-Sem.,)- Section A BRANCH : Electronics and Communication Engineering SUBJECT :optical communications FACULTY :G.Venkat rao
UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-I
&II
(o
ver
view
of
op
tica
l fib
er c
om
mu
nic
atio
n,s
ingl
emo
de
fib
ers
)
1. 19-11-12 Overview of optical fiber communication-historical
development.
2. 20-11-12 The General system, advantages of optical fiber communications
3. 21-11-12 Optical fiber wave guides-introduction, ray theory transmission
4. 22-11-12 Total internal reflection, acceptance angle, numerical
aperture.
5. 24-11-12 Skew rays, cylindrical fibers-modes, vnumber.
6. 26-11-12 Mode coupling,
7. 28-11-12 step index fibers, graded index fibers
8. 29-11-12 Tutorial class1
9. 30-11-12 Single mode fibers-cutoff wave length, mode field diameter,
10. 1-12-12 Effective refractive index, fiber materials-glass,halide
11. 3-12-12 active glass,chalgenide glass, plastic optical fibers.
12. 4-12-12 Signal distortion in optical fibers-attentuation,absorption
13. 5-12-12 Scattering&Bending losses, core and cladding losses
14. 6-12-12 Tutorial class2
15. 8-12-12 Information capacity determination, group delay.
16. 10-12-12 Types of distortion-material dispersion, waveguide
dispersion.
17. 11-12-12 Polarization mode dispersion
18. 12-12-12 intermodal dispersion
UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-I
II&
IV
(op
tica
lfib
er
con
nec
tors
,ligh
t
sou
rce
s) 19. 15-12-12
Pulse broadening, optical fiber connectors-connector types.
20. 13-12-12 Single mode fiber connectors 21. 14-12-12 connector return loss. 22. 17-12-12 Tutorial class3
23. 18-12-12 Fiber splicing-splicing techniques, splicing single mode fibers
24. 19-12-12 Fiber alignment and joint loss-multimode fiber joints,
25. 20-12-12 single mode fiber joints 26. 22-12-12 Optical sources-LEDS. 27. 24-12-12 LED Structures, materials. 28. 26-12-12 Quantum efficiency, power, modulation.
29. 27-12-12 Power bandwidth product, injection laser diodes.
30. 29-12-12 laser diodes-modes, threshold conditions
31. 31-12-12 External quantum efficiency, laser diode rate
equations.
UN
IT-V
&V
I (P
ow
er la
un
chin
g,o
pti
cal d
ete
cto
rs)
32. 1-1-13 Resonant frequencies, reliability of LED&ILD.
33. 2-1-13 Tutorial class4
34. 3-1-13 Source to fiber power launching-
35. 5-1-2013 output patterns
36. 7-1-2013 Power coupling, power launching
37. 8-1-2013 Equilibrium numerical aperture,
38. 9-1-2013 laser diode to fiber coupling.
39. 10-1-13 Tutorial class5
40. 16-1-13 Optical detectors-
41. 17-1-13 physical principles of PIN&APD.
42. 19-1-13 Detector response time
43. 28-1-13 temperature effect on avalanche gain
44. 29-1-13 Comparison of photo detectors
45. 30-1-13 Optical receiver operation-
46. 31-1-13 fundamental receiver operation.
UN
IT-V
II
(op
tica
lsys
tem
des
ign
)
47. 02-2-13 Digital signal transmission. 48. 4-2-13 error sources 49. 5-2-13 Receiver configuration. 50. 6-2-13 digital receiver performance. 51. 7-2-13 Probability of error. 52. 9-2-13 quantum limit, analog receivers. 53. 11-2-13 Tutorial class 6 54. 12-2-13 Optical system design-considerations 55. 13-2-13 Component choice, multiplexing.
56. 14-2-13 Point-to-point links, system considerations
UN
IT-V
III
(WD
M)
57. 16-2-13 link power budget with examples. 58. 18-2-13 Overall fiber dispersion in multimode fibers.
59. 19-2-13 Overall fiber dispersion in single mode fibers.
60. 20-2-13 Rise time budget with examples. 61. 21-2-13 Tutorial class 7 62. 23-2-13 Transmission distance, line coding in optical links. 63. 25-2-13 WDM-Necessity, principles 64. 26-2-13 Types of WDM
65. 27-2-13 Measurement of attenuation and dispersion, eye
pattern.
66. 28-2-13 Tutorial class 8
67. 2-3-13 to 8-3-13
Revision
A
DV
AN
CED
TO
PIC
S
68. 11-3-13 to 16-3-13
Revision
69. 18-3-13 Advanced Topic1 70. 19-3-13 Advanced Topic2 71. 20-3-13 Advanced Topic3 72. 21-3-13 Advanced Topic4 73. 22-3-13 Advanced Topic5
Total 23-3-13 Advanced Topic6 Signature of Faculty Signature of HOD
LESSON PLAN
ACADEMIC YEAR : 2012-13 COURSE : IV B.Tech., (II-Sem.,)- Section B BRANCH : Electronics and Communication Engineering SUBJECT :optical communications FACULTY :G.Venkat rao
UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-I
&II
(o
ver
view
of
op
tica
l fib
er
com
mu
nic
atio
n,s
ingl
em
o
de
fib
ers)
1. 19-11-12 Overview of optical fiber communication-historical
development.
2. 20-11-12 The General system, advantages of optical fiber communications
3. 21-11-12 Optical fiber wave guides-introduction, ray theory transmission
4. 22-11-12 Total internal reflection, acceptance angle, numerical
aperture.
5. 24-11-12 Skew rays, cylindrical fibers-modes, vnumber.
6. 26-11-12 Mode coupling,
7. 28-11-12 step index fibers, graded index fibers
8. 29-11-12 Tutorial class1
9. 30-11-12 Single mode fibers-cutoff wave length, mode field diameter,
10. 1-12-12 Effective refractive index, fiber materials-glass,halide
11. 3-12-12 active glass,chalgenide glass, plastic optical fibers.
12. 4-12-12 Signal distortion in optical fibers-attentuation,absorption
13. 5-12-12 Scattering&Bending losses, core and cladding losses
14. 6-12-12 Tutorial class2
15. 8-12-12 Information capacity determination, group delay.
16. 10-12-12 Types of distortion-material dispersion, waveguide
dispersion.
17. 11-12-12 Polarization mode dispersion
18. 12-12-12 intermodal dispersion
UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-I
II&
IV
(op
tica
lfib
er c
on
nec
tors
,ligh
t so
urc
es)
19. 15-12-12 Pulse broadening, optical fiber connectors-connector types.
20. 13-12-12 Single mode fiber connectors 21. 14-12-12 connector return loss. 22. 17-12-12 Tutorial class3
23. 18-12-12 Fiber splicing-splicing techniques, splicing single mode fibers
24. 19-12-12 Fiber alignment and joint loss-multimode fiber joints,
25. 20-12-12 single mode fiber joints 26. 22-12-12 Optical sources-LEDS. 27. 24-12-12 LED Structures, materials. 28. 26-12-12 Quantum efficiency, power, modulation.
29. 27-12-12 Power bandwidth product, injection laser diodes.
30. 29-12-12 laser diodes-modes, threshold conditions
31. 31-12-12 External quantum efficiency, laser diode rate
equations.
UN
IT-V
&V
I (P
ow
er la
un
chin
g,o
pti
cal d
ete
cto
rs) 32. 1-1-13 Resonant frequencies, reliability of LED&ILD.
33. 2-1-13 Tutorial class4
34. 3-1-13 Source to fiber power launching-
35. 5-1-2013 output patterns
36. 7-1-2013 Power coupling, power launching
37. 8-1-2013 Equilibrium numerical aperture,
38. 9-1-2013 laser diode to fiber coupling.
39. 10-1-13 Tutorial class5
40. 16-1-13 Optical detectors-
41. 17-1-13 physical principles of PIN&APD.
42. 19-1-13 Detector response time
43. 28-1-13 temperature effect on avalanche gain
44. 29-1-13 Comparison of photo detectors
45. 30-1-13 Optical receiver operation-
46. 31-1-13 fundamental receiver operation. U
NIT
-VII
(o
pti
cals
yste
md
esig
n)
47. 02-2-13 Digital signal transmission. 48. 4-2-13 error sources 49. 5-2-13 Receiver configuration. 50. 6-2-13 digital receiver performance. 51. 7-2-13 Probability of error. 52. 9-2-13 quantum limit, analog receivers. 53. 11-2-13 Tutorial class 6 54. 12-2-13 Optical system design-considerations 55. 13-2-13 Component choice, multiplexing.
56. 14-2-13 Point-to-point links, system considerations
UN
IT-V
III
(WD
M)
57. 16-2-13 link power budget with examples. 58. 18-2-13 Overall fiber dispersion in multimode fibers.
59. 19-2-13 Overall fiber dispersion in single mode fibers.
60. 20-2-13 Rise time budget with examples. 61. 21-2-13 Tutorial class 7 62. 23-2-13 Transmission distance, line coding in optical links. 63. 25-2-13 WDM-Necessity, principles 64. 26-2-13 Types of WDM
65. 27-2-13 Measurement of attenuation and dispersion, eye
pattern.
66. 28-2-13 Tutorial class 8
67. 2-3-13 to 8-3-13
Revision
AD
VA
NC
ED T
OP
ICS
68. 11-3-13 to 16-3-13
Revision
69. 18-3-13 Advanced Topic1 70. 19-3-13 Advanced Topic2 71. 20-3-13 Advanced Topic3 72. 21-3-13 Advanced Topic4 73. 22-3-13 Advanced Topic5
Total 23-3-13 Advanced Topic6 Signature of Faculty Signature of HOD
LESSON PLAN
ACADEMIC YEAR : 2012-13 COURSE : IV Year B.Tech. ECE.II-Sem, Section A BRANCH : Electronics and Communication Engineering SUBJECT : DSP PROCESSORS AND ARCHITECTURES FACULTY : V.V.RAMA KRISHNA
UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-I
(I
NT
OR
OD
UC
TIO
N T
O D
IGIT
AL
SIG
NA
L P
RO
CE
SIN
G)
78. 19-11-12 Introduction
79. 21-11-12 A Digital signal-processing system
80. 22-11-12 The sampling process, Discrete time sequences
81. 23-11-12 Discrete Fourier Transform (DFT)
82. 28-11-12 Fast Fourier Transform (FFT)
83. 29-11-12 Linear time-invariant systems
84. 30-11-12 IIR Filters
85. 01-12-12 FIR filters
86. 03-12-12 Decimation and interpolation
87. 05-12-12 Analysis and Design tool for DSP Systems MATLAB
88. 06-12-12 Tutorial-1
UN
IT-I
I C
OM
PU
TA
TIO
NA
L
AC
CU
RA
CY
IN
DS
P
IMP
LE
ME
NT
AT
ION
S 89. 07-12-12 Number formats for signals and coefficients in DSP
systems
90. 10-12-12 Dynamic Range and Precision 91. 12-12-12 Sources of error in DSP implementations 92. 13-12-12 A/D Conversion errors, DSP Computational errors 93. 14-12-12 D/A Conversion Errors 94. 15-12-12 Compensating filter 95. 17-12-12 Tutorial-II
UN
IT-I
II (A
RC
HIT
EC
TU
RE
S F
OR
PR
OG
RA
MM
AB
LE
DS
P
DE
VIC
ES
)
96. 19-12-12 Basic Architectural features 97. 20-12-12 DSP Computational Building Blocks 98. 21-12-12 Bus Architecture and Memory 99. 22-12-12 Data Addressing Capabilities 100. 24-12-12 Address Generation Unit 101. 26-12-12 Programmability and Program Execution 102. 27-12-12 Speed Issues 103. 28-12-12 Features for External interfacing 104. 29-12-12 Tutorial-III
UNIT
S.No.
Date-I
Topic
Date-II
Remarks
UN
IT-I
V
(EX
EC
UT
ION
CO
NT
RO
L A
ND
PIP
EL
ININ
G)
105. 31-12-12 Hardware looping, Interrupts 106. 02-01-13 Stacks, Relative Branch support 107. 03-01-13 Pipelining and Performance 108. 04-01-13 Pipeline Depth, 109. 05-01-13 Interlocking 110. 07-01-13 Branching effects
111. 09-01-13 Interrupt effects 112. 10-01-13 Pipeline Programming models 113. 11-01-13 Tutorial-IV
UN
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114. 12-01-13 Commercial Digital signal-processing Devices 115. 17-01-13 Data Addressing modes of TMS320C54XX DSPs 116. 18-01-13 Data Addressing modes of TMS320C54XX Processors 117. 28-01-13 Memory space of TMS320C54XX Processors 118. 30-01-13 Program Control 119. 31-01-13 TMS320C54XX instructions and Programming 120. 01-02-13 On-Chip Peripherals 121. 02-02-13 Interrupts of TMS320C54XX processors 122. 04-02-13 Pipeline Operation of TMS320C54XX Processors 123. 06-02-13 Tutorial-V
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124. 07-02-13 The Q-notation
125. 08-02-13 FIR Filters 126. 11-02-13 IIR Filters 127. 13-02-13 Interpolation Filters 128. 14-02-13 Decimation Filters
129. 15-02-13 PID Controller
130. 16-02-13 Tutorial-VI
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131. 18-02-13 Adaptive Filters 132. 20-02-13 2-D Signal Processing 133. 21-02-13 An FFT Algorithm for DFT Computation 134. 22-02-13 A Butterfly Computation 135. 23-02-13 Bit-Reversed index generation 136. 25-02-13 An 8-Point FFT implementation on the TMS320C54XX 137. 27-02-13 Computation of the signal spectrum 138. 28-02-13 Tutorial-VII
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139. 01-03-13 Memory space organization, External bus interfacing signals
140. 02-03-13 Memory interface, Parallel I/O interface 141. 04-03-13 Programmed I/O, Interrupts and I/O 142. 06-03-13 Direct memory access (DMA). 143. 07-03-13 A Multichannel buffered serial port 144. 08-03-13 McBSP Programming 145. 11-03-13 a CODEC interface circuit, CODEC programming 146. 13-03-13 A CODEC-DSP interface example 147. 14-03-13 Tutorial-VIII
148. 15-03-13 Revision of I Unit 149. 16-03-13 Revision of II Unit 150. 18-03-13 Revision of III Unit 151. 20-03-13 Revision of IV Unit 152. 21-03-13 Revision of V Unit 153. 22-03-13 Revision of VI Unit 154. 23-03-13 Revision of VII & VIII Units Total
Signature of Faculty Signature of HOD
LESSON PLAN ACADEMIC YEAR : 2012-13
COURSE : IV Year B.Tech. ECE.II-Sem, Section B BRANCH : Electronics and Communication Engineering SUBJECT : DSP PROCESSORS AND ARCHITECTURES FACULTY : V.V.RAMA KRISHNA
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1. 19-11-12 Introduction
2. 20-11-12 A Digital signal-processing system
3. 21-11-12 The sampling process, Discrete time sequences
4. 22-11-12 Discrete Fourier Transform (DFT)
5. 23-11-12 Fast Fourier Transform (FFT)
6. 28-11-12 Linear time-invariant systems
7. 29-11-12 IIR Filters
8. 01-12-12 FIR filters
9. 03-12-12 Decimation and interpolation
10. 05-12-12 Analysis and Design tool for DSP Systems MATLAB
11. 06-12-12 Tutorial-1
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13. 11-12-12 Dynamic Range and Precision 14. 12-12-12 Sources of error in DSP implementations 15. 13-12-12 A/D Conversion errors, DSP Computational errors 16. 15-12-12 D/A Conversion Errors 17. 17-12-12 Compensating filter 18. 18-12-12 Tutorial-II
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19. 19-12-12 Basic Architectural features 20. 20-12-12 DSP Computational Building Blocks 21. 22-12-12 Bus Architecture and Memory 22. 24-12-12 Data Addressing Capabilities 23. 26-12-12 Address Generation Unit 24. 27-12-12 Programmability and Program Execution 25. 29-12-12 Speed Issues 26. 01-01-13 Features for External interfacing 27. 02-01-13 Tutorial-III
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28. 03-01-13 Hardware looping, Interrupts 29. 05-01-13 Stacks, Relative Branch support 30. 07-01-13 Pipelining and Performance 31. 08-01-13 Pipeline Depth, 32. 09-01-13 Interlocking 33. 10-01-13 Branching effects 34. 09-01-13 Interrupt effects
35. 16-01-13 Pipeline Programming models 36. 17-01-13 Tutorial-IV
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37. 28-01-13 Commercial Digital signal-processing Devices 38. 29-01-13 Data Addressing modes of TMS320C54XX DSPs 39. 30-01-13 Data Addressing modes of TMS320C54XX Processors 40. 31-01-13 Memory space of TMS320C54XX Processors 41. 02-02-13 Program Control 42. 04-02-13 TMS320C54XX instructions and Programming 43. 05-02-13 On-Chip Peripherals 44. 06-02-13 Interrupts of TMS320C54XX processors 45. 07-02-13 Pipeline Operation of TMS320C54XX Processors 46. 11-02-13 Tutorial-V
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47. 12-02-13 The Q-notation
48. 13-02-13 FIR Filters 49. 14-02-13 IIR Filters 50. 16-02-13 Interpolation Filters 51. 18-02-13 Decimation Filters
52. 19-02-13 PID Controller
53. 20-02-13 Tutorial-VI
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54. 21-02-13 Adaptive Filters 55. 23-02-13 2-D Signal Processing 56. 25-02-13 An FFT Algorithm for DFT Computation 57. 26-02-13 A Butterfly Computation 58. 27-02-13 Bit-Reversed index generation 59. 28-02-13 An 8-Point FFT implementation on the TMS320C54XX 60. 02-03-13 Computation of the signal spectrum 61. 04-03-13 Tutorial-VII
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62. 05-03-13 Memory space organization, External bus interfacing signals
63. 06-03-13 Memory interface, Parallel I/O interface 64. 07-03-13 Programmed I/O, Interrupts and I/O 65. 08-03-13 Direct memory access (DMA). 66. 11-03-13 A Multichannel buffered serial port 67. 12-03-13 McBSP Programming 68. 13-03-13 a CODEC interface circuit, CODEC programming 69. 16-03-13 A CODEC-DSP interface example 70. 18-03-13 Tutorial-VIII
71. 19-03-13 Revision of I & II Unit 72. 20-03-13 Revision of III & IV Unit 73. 21-03-13 Revision of V & VI Unit 74. 23-03-13 Revision of VII & VIII Unit Total
Signature of Faculty Signature of HOD
