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� 15 years ago ISAs were driven by academia

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� How many of you will ever design an ISA?

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Register Add R4,R3 Regs[R4] ← Regs[R4]+Regs[R3]

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Direct or absolute Add R1,(1001) Regs[R1] ← Regs[R2]+Mem[1001]

Memory indirect or memory deferred

Add R1,@(R3) Regs[R1] ← Regs[R1]+Mem[Mem[Regs[R3]]]

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Accessing local variables.

Registerdeferred orindirect

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Accessing using a pointer or acomputed address.

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Used to index arrays. May beapplied to any indexedaddressing mode in somemachines.

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Arithmetical and logical Integer arithmetic and logical operations: add, and, subtract, or

Data transfer Loads/stores (move instructions on machines with memoryaddressing)

Control Branch, jump, procedure call and return

System Operating system call, virtual memory management instructions

Floating point Floating-point operations: add, multiply,...

Decimal Decimal add, decimal multiply, decimal-to-character conversions

String String move, string compare, string search


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� 8-bit branch displacements cover most cases

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Ins tructiontype

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Load LW R1,30(R2) Regs [R1] ←Mem[30+Regs[R2]]

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ALU ADD R1,R2,R3 Regs[R1] ← Regs[R2] +Regs[R3]

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28 November 2002


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Structural hazards: Simultaneous use of same resourceIf unified I+D$: LW will conflict with later I-fetch

Data hazards: Data dependencies between instructionsLW R1, 100(R2) /* result avail in 2 - 100 cycles */ADD R5, R1, R7

Control hazards: Change in program flowBNEQ R1, #OFFSETADD R5, R2, R3

Serialization of the execution by stalling the pipelineis one, although inefficient, way to avoid hazards


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Code sequence Opi A

Opi+1A

5$: �5HDG�$IWHU�:ULWH�

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WAR (Write-After-Read) Opi+1 modifies A before Opi reads A. Opi reads new A

WAW (Write-After-Write) Op i+1 modifies A before Opi. The value in A is the one written by Opi, i.e., an old A.

28 November 2002


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IF ID EX M WB

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pc

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Data$DTLB…L2$…Mem

Instr$ITLB…L2$…Mem


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Branch conditionand target addr. needed here

Branch conditionand target addr. available here

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28 November 2002


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IF ID EX M WB

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PC := PC + Imm


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Predict Branch not taken (a fairly rare case)zExecute successor instructions in sequence

z“Squash” instructions in pipeline if the branch is actually taken

zWorks well if state is updated late in the pipeline

z30%-38% of conditional branches are not taken on average

Predict Branch taken (a fairly common case)z62%-70% of conditional branches are taken on average

zDoes not make sense for the generic arch. but may do for other pipeline organizations

Delayed branch (schedule useful instr. in delay slot)zDefine branch to take place aftera following instruction

zCONS: this is visible to SW, i.e., forces compatibility between generations


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28 November 2002


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Pipeline speedup = #stages1 + Branch frequency x Branch penalty

S c h e d u lin gs c h e m e

B ra n c h p e n a lt y f o rin t e g . P g m

C P I S p e e d u p v s.U n p ip e l in e d

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Solution: Dynamic branch predictionto predict the outcome of conditional branches.

Benefits:PReduce time to determine branch conditionPReduce time to calculate the branch target address

28 November 2002

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Predict Not taken

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P Predicts branch target address in the IF stage

P Can be combined with 2-bit branch prediction

28 November 2002


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Ins tructionin buffe r

Pred ic tion Actualbranch

Penaltycyc les

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A solution:

1. Force a trap instruction into the pipeline

2. Turn off all writes for the faulting instruction

3. Save the PC for the faulting instruction- to be used in return from exception

- may need to save multiple PC values

28 November 2002


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Exceptions may be generated in another order than the instruction execution order

Pipeline stage Problem causing exception

IF Page fault on instruction fetch;misaligned memory access; memoryprotection violation

ID Undefined or illegal opcode

EX Arithmetic exception

MEM Page fault on data access;misaligned memory access; memoryprotection violation

WB none

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MU LTD F 2 ,F 4 ,F 6 IF ID M 1 M2 M3 M4 M5 M6 M7 ME M W B

AD D D F 8 ,F 1 0 ,F 1 2 IF ID A 1 A2 A3 A 4 ME M W B

S U B I R 2 ,R 3 ,# 8 IF ID E X ME M W B

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Example of a WAW hazard:DIVF F0,F2,F4 FP divide 24 cycles...SUBF F0,F8,F10 FP sub 3 cycles

SUB finishes before DIV ; out-of-order completion

WAW hazards are avoided by:zstalling the SUBF until DIVF reaches the MEM stage, or

zdisabling the write to register F0 for the DIVF instruction


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SUBF may generate a trap before DIVF has completed!!


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Two historical schemes used in “recent” machines:

Tomasuloin IBM 360/91 in 1967 (also in Power-2)

Scoreboarddates back to CDC 6600 in 1963

28 November 2002


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The scoreboard is updated when an instruction proceedsto a new stage


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Tomasulo’s algorithm addresses the last two limitations


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MULD tmp2 ,F10, tmp1 ;delayed a few cycles

28 November 2002


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x[i] = x[i] + 10;

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How about moving SD down?

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Can we do better by scheduling across iterations?

5 instruction + 4 bubbles = 9 cycles / iteration(~one cycle per iteration on a vector architecture)


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Can we do even better by scheduling across iterations?

5 instruction + 1 bubble = 6c / iteration


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Important steps:Push loads up

Push stores down

Note: the displacement of the last store must be changed

All penalties are eliminated. CPI=1

14 cycles / 4 iterations ==> 3.5 cycles / iteration

From 9c to 3.5c per iteration ==> speedup 2.6

Benefits of loop unrolling:Provides a larger seq. instr. window (larger basic block)

Simplifies for static and dynamic methods to extract ILP


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SoftwarePipelinedIteration 1 BNEQ SUB ST ADD LD

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Look at three iterations of the loop body:LD F0,0(R1) ; Iteration iADDD F4,F0,F2SD 0(R1),F4

LD F0,0(R1) ; Iteration i+1ADDD F4,F0,F2SD 0(R1),F4LD F0,0(R1) ; Iteration i+2ADDD F4,F0,F2

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z No data dependencies within a loop iteration

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z 5c / iteration, but only uses 2 FP regs (instead og 8)

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for (i = 1; i <= 100; i = i+1) {A[i] = B[i] + C[i];

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The absence of loop-carried dependencies increases the amount of exploitableparallelism


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A loop iteration is often dependent on results calculated in an earlier iteration.

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Y[i] = Y[i-5] + Y[i];

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Example:for (i = 1; i <= 100; i = i + 1)

X[2 * i + 3] = X[2 * i] * 5.0;

We have a=2, b=3, c=2 and d=0; GCD(2,2) = 2 which does not divide (0-3) = -3 =>

z There are no loop carried dependencies in this loop

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z HW finds independent instructions in “sequential” code

zPredominant: (PowerPC, SPARC, Alpha, HP-PA)

Very Long Instruction Words (VLIW):z Static scheduling used to form packages of independent instructions that can be issued together

zRelies on compiler to find independent instructions (IA-64)


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zData dependencies

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zDependencies are properties of the program

zCan lead to hazardswhich are properties of the implementation


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z Data and control dependencies are in general more costly in a superscalar processor than in a single-issue processor

Simple superscalar relying on compiler instead of HW complexity Î VLIW

Techniques to enlarge the instruction window to extract more ILPare important


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LD F 1 8 ,-3 2 (R 1 ) LD F 2 2 ,-4 0 (R 1 ) ADD D F 4 ,F 0 ,F 2 ADD D F 8 ,F 6 ,F 2 3

LD F 2 6 ,-4 8 (R 1 ) ADD D F 1 2 ,F 1 0 ,F 2 ADD D F 1 6 ,F 1 4 ,F 2 4

ADD D F 2 0 ,F 1 8 ,F 2 ADD D F 2 4 ,F 2 2 ,F 2 5

S D 0 (R 1 ), F 4 S D -8 (R 1 ), F 8 ADD D F 2 8 ,F 2 6 ,F 2 6

S D -1 6 (R 1 ), F 1 2 S D -2 4 (R 1 ), F 8 7

S D -3 2 (R 1 ),F 2 0 S D -4 0 (R 1 ),F 2 4 S UBI R 1 ,R 1 ,#4 8 8

S D 0 (R 1 ),F 2 8 BNE Z R 1 ,LO O P 9


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A combination of three main ideas we’ve coveredDynamic Instruction scheduling; take advantage of ILP

Dynamic branch prediction; allows instruction scheduling across branches

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Hardware based speculation uses a data-flow approach:instructions execute when their operands are available

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7UDFH�VFKHGXOLQJ��Creates a sequence of instructions that are likely to be executed -- a trace.

Two steps:

z Trace selection:Find a likely sequence of basic blocks (trace) across statically predicted branches (e.g. if-then-else)

z Trace compaction: Schedule the trace to be as efficient as possible while preserving correctness in the case the prediction is wrong

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z The assignment to B is control dependent on the if statement.

z Trace compaction has to respect data dependencies

z The rightmost (less likely) trace has to be augmented with fix up code


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Advantage: creates longer schedulable code sequences => more ILP can exploited

Example: if (A == 0) then A = B; else A = A+4;

Non speculative code Speculative codeLW R1,0(R3) LW R1,0(R3)BNEZ R1,L1 LW R14,0(R2)LW R1,0(R2) BEQZ R1,L3J L2 ADD R14,R1,4

L1: ADD R1,R1,4 L3: SW 0(R3),R14L2: SW 0(R3),R1

z What about exceptions?

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