A0.35µm1.25VPiezo-Resistance DigitalROIC ...pserra/cnm/2008 - A 0.35um 1.25V Piezo... ·...

ISCAS’08: A Piezo-Resist. Digital ROIC for MEMS Intro Balancing Preamp ADC CMOS Conclusions 1/26

A 0.35µm 1.25V Piezo-ResistanceDigital ROIC

for Liquid Dispensing MEMS

R. Durà1, F. Mathieu2, L. Nicu2, F. Pérez-Murano1

and F. Serra-Graells1

1Centro Nacional de Microelectrónica - CSIC (Spain)2 Laboratoire d’Analyse et d’Architecture des Systèmes - CNRS (France)

May 2008

R. Durà et al. Centro Nacional de Microelectrónica


1 Introduction

2 Input Gain Balancing

3 Differential Pre-Amplification

4 Integrating A/D Conversion

5 CMOS Integration

6 Conclusions



1 Introduction




5 CMOS Integration

6 Conclusions



Bioplume Scenario

I Liquid dispensing MEMSfor µdroplet patterning

I Integrated piezo-resistive stresssensor to control positioning

I Dummy-based differentialreading to cancel T/M/Edisturbing signals

I Multi channel digital ROICI Low-power to prevent dryingI Low-voltage for single cell

battery operation

microdroplets

referencepipet

digital I/O

battery

ROIC

pipet tip

activepipets

piezo-resistivestresssensor

cantilever

liquid reservoir



Integratedpiezo-resistance

I Nominal value:5KΩ to 10KΩ100% (±20%)

I Quasi-staticstress signal (9bit):±0.0004%. . .±0.1%

I Technologymismatching: ±2%

I Dynamic disturbingsignals: ±1%

⇓

±0.02% (50LSB) dynamic residual!

Rref

Rsens

nominalvalue

(100%)

mismatching( 2%)§

common disturbingsignals ( )1%§

quasi-static stress signal( )0.0004%... 0.1%§ §piezo-resistance

time1ms0

sampling period

Rsens-Rref

differential disturbingsignals ( 0.02 )%§

offset ( 2 )%§



Gain BalancingStrategy

I Maximum gaincompensation: ±2%

I Gain accuracy:±0.0002%/2%=±0.01%

I Gain dynamic range:2%/0.01%=(8+1)bit

I Residual dynamicdisturbing: ±0.25LSB

I Residual DC: ±25LSBcompensated bydigital post-processing

Rref

Rsens

nominalvalue

(100%)

mismatching( 2%)§

common disturbingsignals ( )1%§

quasi-static stress signal( )0.0004%... 0.1%§ §piezo-resistance

time1ms0

sampling period

Rsens-Rref

differential disturbingsignals ( 0.02 )%§

offset ( 2 )%§



ROIC ArchitectureI Parallel processing to

reduce noise bandwidthI Overall programmable

sensitivity (Icom)I Differential gain

balancing through sensorbias (∆Icom)

I OTA pre-amplificationI Integrating A/D

conversionI Digital only

read-out/program-inI Independent references

to avoid crosstalk

Rsens2

Rsens1

Rref

Vcom

ADC

I/O

DAC

Vsens

Icom

Ieff

Rsens3

Rsens4

Icom

Vref

¢Icom

S11-0

C8-0



1 Introduction




5 CMOS Integration

6 Conclusions



Input Gain Balancing

I Calibration throughDAC: ∆Icom(C8-0)

I Gate tuning:

∆Vtun = C2C1+C2

(Vprog − VDD2 )

I Compensation ofpiezo mismatch +OTA unbalance

I Repeated before everyacquisition

I Design parameters:C1=9pF, C2=0.5pF

Rsens

Vcom

Rref

IeffVref

Vsens

25

Icom

phasegenerator

ADC

2225 3

Á1 Á2

Á3Á4

Á5 Á7

Á6

0

1

2

3

4

5

6

7

8

Á1 Á7

Á7

C1

C2

C2 C2 C2 C2

M2 M1

Icom Icom§¢Icom

Vtun

Vprog

gain preset gain calibration refresh A/D conversion

Á1

Á2

Á3

Á4

Á5

Á6

Á7 0 1 2 3 4 5 6 7 8

Tint

C

Vsens−Vref = Icom[Rsens

(1± ∆Icom

Icom

)− Rref

]



1 Introduction




5 CMOS Integration

6 Conclusions



OTA PreamplifierI Differential V to

single ended I

Ieff = Gm (Vsens −Vref )

I Equivalent inputlow-noise

I Large diff. gain(in subthreshold):

Gm = IbiasnnUt

I High commonrejection ratio

I Design parameters:Ibiasp,n = 56µA, 44µA

M2

2Ibiasn

M1

Rsens

Vcom

Rref

IeffADC

Vref

Vsens

Icom

M6M5

M7 M8

M4M3

Ibiasp

Icom Icom§¢

DR(Vsens) ∼ 1mV/4µV

(Rsens ∼ 5kΩ and Icom ∼ 200µA)




single ended I




Gm = IbiasnnUt



Frequency [Hz]

1

processcorners

0.1

0.01100 1k101

rms

Vneq ' 2µVrms up to 1kHz

(Vnres ∼ 0.4µVrms for Rsens = 10kΩ)




single ended I




Gm = IbiasnnUt



Diffe

rential

tra

nsc

onduct

ance

[m

S]

1

Frequency [Hz]

0.1

0.01

10

0.01100 10k 1M 100M

processcorners

Gm ≥ 0.8mS

DR(Ieff ) ∼ 1µA/4nA




single ended I




Gm = IbiasnnUt



1CMRR = ∆Gm

Gm

(1− 1

1 + 12nGmRtail

)CMRR→∞ for ∆Gm → 0 or Rtail →∞

MOSFET mismatching + Ibiasn finite impedance

50

10

0

2

4

6

8

Fre

quen

cy [%

]

CMRR(DC) [dB]

100 150

1%0.0002%

=75dB



1 Introduction




5 CMOS Integration

6 Conclusions



A/D Conversion

I Spike counting:PDM+digital filter

I CDS forlow-frequency noisesuppression

I Low-voltageswitching ⇒large reset times

I Design parameters:Cint = 4pF,Vth = 312mV

X Classic PDM:reset-timenon-linearity

Vint

up

V Vref th-

digitalcounter

init

event

V Vref th+

down

Cint

Vref

IeffCCDS

init+event

init+event

Time

Vint

event

Vth

Vref

Upper range saturation of the A/D curve!



A/D Conversion

I Spike counting:PDM+digital filter

I CDS forlow-frequency noisesuppression

I Low-voltageswitching ⇒large reset times

I Design parameters:Cint = 4pF,Vth = 312mV

X New insensitive PDM

S11-0 = ± IeffTint

CintVth= ±GmTint

CintVthIcom[

Rsens

(1± ∆Icom

Icom

)− Rref

]

Vint

up

V Vref th-

digitalcounter

init

event

V Vref th+

down

Cint

Vref

init

Creset/CDS

event

Ieff

Vint

event

Vth

Vref

Time



Low-Voltage CMOS Blocks

I Compact CTIA with CDSVint

Cint Vref

Ieff

init

Creset/CDS

event

M1 M2




I Compact CTIA with CDS

I Class-AB window comparator

Vint

V Vref th+

down

V Vref th-

up

M1 M2

M3

M4




I Compact CTIA with CDS

I Class-AB window comparator

I Modular and floatingthreshold generator

∆Vth = Ut ln[

(W/L)B(W/L)A

(1 + IB

IA

)+ 1]

MA : weak inversion conductionMB : weak inversion saturation

MA1

MB1 ¢VthMA2

MB2

Vref

init V Vref th+

V Vref th-

Vth

MA3

MB3

IB

IA



1 Introduction




5 CMOS Integration

6 Conclusions



ROIC Integration

I 0.35µm 2P 4M CMOS technology 2.4mm × 1.3mm = 3.1mm2



ROIC Integration

I 0.35µm 2P 4M CMOS technology 2.4mm × 1.3mm = 3.1mm2

Singlechannel

Sensorbias

Preamp

DAC

ADC

DigitalI/O



Results

I MEMS + ROIC integrationnot completed yet. . .

I Meanwhile, results frompost-layout simulation

I 4 channel power supply:1.5mW at 1.25V

I Ideally:

∣∣∣∣ S11-0

∆Rsens/Rsens

∣∣∣∣ = GmTint

CintVthIcomRsens ≡

0.8mS× 1ms4pF× 312mV×189µA×5kΩ ' 6kLSB/%

Vth PTAT and Gm 1/PTAT. If Icom,bias PTAT ⇒ S11-0 6= f (T)

S11-0

[LSB

]

600

400

200

0

-200

-400

-6000.02 0.04 0.06 0.08 0.1-0.02-0.04-0.06-0.08-0.1 0

Rsens=5k−

Icom=189 A¹

C '100001000'8-0

=

Tint=1ms



1 Introduction




5 CMOS Integration

6 Conclusions



Conclusions

I Quad-channel ROIC for integrated piezo-resistive sensors.I Sensor balancing by digital gain tuning.I Robust built-in A/D conversion.I Low-voltage and low-power CMOS circuit realization.I Integration in 0.35µm 2-poly 4-metal technology.I Post-layout electrical simulation results.


A0.35µm1.25VPiezo-Resistance DigitalROIC ...pserra/cnm/2008 - A 0.35um 1.25V Piezo... ·...

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