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ISSCC 2004 / SESSION 17 / MEMS AND SENSORS / 17.5

17.5 A Very Low Power CMOS Mixed-Signal ICfor Implantable Pacemaker Applications

Louis S Y Wong, S. Hossain, A. Ta, L. Weaver, C. Shaquer,A. Walker, J. Edvinsson, D. Rivas, H. Naas, A. Fawzi, A. Uhrenius,J. Lindberg, J. Johansson, P. Arvidsson

St. Jude Medical, Sunnyvale, CA

Implantable pacemakers using few transistors were introduced inthe 1950s. Technology advances provide automatic sensitivity andimproves therapy. A block diagram is outlined in Fig. 17.5.1 andcontains amplifiers, filters, ADCs, a battery management system,high-voltage output generators and logic controls. It is powered bya primary battery to provide 5-10 year life.

Pacemakers need to sense very small (~V) cardiac signals which areamplified by an LNA and gain amplifier, BPF and digitized by ADC.

An SC amplifier and BPF are often used for accurate frequencyresponse and low power consumption (~20nA each). Transistors areoperated in the sub-threshold region to maximize the gm. The cardiacand respiration signals may vary within 0.01-2Hz. Their SC sam-pling rate is in tenths of a Hz so transistor leakage may become aserious issue. Assume the S/H amplifier (SHA) in Fig. 17.5.2, withChold=1pF, a S/H period of 100ms, and a 1pA of leakage will drift 0.1V

during the hold period. This is unacceptable when mV or V of reso-lution is required. It is solved by using a larger capacitor which costssilicon area and consumes more power. A technique is presented toreduce the effective leakage current seen by the capacitor[1].

To illustrate the concept, as implemented in Fig. 17.5.2, a self-adjust-ed current source is added. When the switch is off, a cancellation cur-rent Icancel is injected to Vhold to cancel all the leakages (I1, I2, I3). Theeffective leakage seen by Chold is virtually zero. Thus, Chold can be keptvery small allowing low power operation and small area. A replicaswitch and a current cancellation feedback network are also intro-duced. The replica switch is identical to the main switch, whereas thereplica capacitor Crep is smaller than the main capacitor Chold. Assumethe leakage cancellation feedback network is temporarily omittedfrom the system. When the switches are off, the leakages on the repli-ca switch are the same as the main switch. If leakage currents exist,the voltage drift on the replica node Vrep is larger than the main mode

Vhold, because Crep < Chold. Now, add back the leakage cancellation feed-back to the complete system and close the loop. M1, M4, M5 and M8are the constant leakage generators with large W/L, and theirsourcing/sinking currents are higher than I1, I2, and I3. By utilizingthe opamp A1, a closed loop system is formed with a push-pull outputstage using the leakage generators. It senses the difference between

Vhold and Vrep, and injects the counter-current Icancel, to cancel the leak-ages. A quiescent state is reached when Icancel is equal to the switchleakage, and both Vhold and Vrep do not drift any further. If A1 is idealand all transistors are matched, the leakages will cancel perfectly.However, consider the opamp gain A and offset voltage Voffset, so thatthe effective voltage drift is given in (1). The drift can be minimizedby reducing Voffset, increasing A or maximizing (Chold-Crep).

(1)

An 8b successive approximation register (SAR) ADC is shown in Fig.

17.5.3 in which, the power is typically consumed by SHA, DAC andcomparator. To minimize power, this ADC: (i) utilizes a capacitorarray (CA) for the DAC, (ii) uses a single opamp for both S/H andcomparator, (iii) combines the DAC CA for S/H usage. The operationis as follows: First, the input is sampled and stored by connecting CAto Vin, and closing the feedback loop of the S/H-comparator for auto-zero sampling. Next, the S/H feedback switch is open, and the inte-grating S/H-comparator turns into a comparator. The SAR conver-sion begins by sequentially connecting CA (MSB to LSB) to either

VREF_1 or VREF_0 for 8 cycles and to evaluate the digital output. The S/H-comparator is formed by three class AB amplifiers or inverters. TheS/H output is taken from the first amplifier to provide unity gain sta-bility for auto-zeroing. The comparator output is taken from the thirdamplifier for high voltage gain. Transistors are operated in sub-threshold region to maximize gm with minimal current. A divide-by-

two CA is used to reduce area and power. Bottom-plate-sampling isused to minimize input offset variations. The current consumption ismeasured at ~150nA @ 1KS/s.

A low power, monotonic[2], 12b slope ADC is shown in Fig 17.5.4. Atleast 4096 clock cycles are required for a 12b conversion. The con-version rate cannot exceed 8S/s as the fastest clock available is32kHz. In this ADC, a local oscillator is proposed to increase therate to 100 S/s. During1, S1 and S3 are closed, and the input volt-

age Vin, is stored in CINT. During2, S4 and S5 are closed to levelshift the CINT by Vref. During3, S2, S4 and S5 are closed to dis-charge CINT by a constant current, and the oscillator starts and thecounter measures the time for the CINT to discharge to Vref. Whenperforming a measurement, two other reference voltages Vref and

Vss are measured to calculate the gain and offset for the ADC. Noiseis the major linearity factor in this design: CINT is chosen for KT/C