A Top-down Design Methodology with Embedded Aging Sensors for Robust System Design
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A Top-down Design Methodology with Embedded Aging Sensors for Robust System Design
Xinfei Guo5/9/2014
2014 Spring ASIC/SOC Design
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Outline Motivation Aging sensor cell Top-down design methodology Future work
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Aging/Wearout Reliability: time dependent degradation Device level: parametric shift over time (e.g.Vth,u) Circuit and architecture level Irreversible and reversible(e.g. BTI)
&0
0
0
Q
QSET
CL R
S
R
Timing Error!
High Power! Failure!
Slow!
10-1 100 101 102 103 104 10510-3
10-2
10-1
100
TPHY=36A, VG=-4.5V
25OC (0.23)
90OC (0.25)
150OC (0.27)
VT (
V)
stress time (s)
[M. Alam et al. Microelectronics Reliability ’07]
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Bias Temperature Instability(BTI) Trapping/Detrapping [J. Velamala et al. DAC’12] Get worse and worse Both NBTI and PBTI Stress and Recovery
[M. Lee et al. ASP-DAC ’11]
Time
∆Vth(t1)
t1 t1+t2
∆Vth
0
Vstress RemoveVstress Vstress
RemoveVstress
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Why Aging Sensor? Track and monitor aging Adaptive circuit tuning (e.g. DVFS) “Check engine light” for recovery techniques
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Related Work Ring Oscillator based “Silicon Odometer” [T. Kim et al. VLSI ’07, JSSC ’08] - Area overhead, complex, process variation Metastable element based [A. Cabe et al. ISQED ’09][S. Wooters, et al. TVLSI ’12]
- Small and embedded - Good time resolution - Distributed
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Sensor Cell
Source: S. Wooters, et al. TVLSI ’12
Set the margin
Design the sensor
Check the engine
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Why Top-Down Design?
Top-down design for sensor itself - Reduce design time - Reduce impact of process variations - Designware cell Top-down design with sensor embedded - Different behavior of each block - Different Thermal Behavior - Distributed with Smaller area overhead
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Sensor Cell Instantiate the library cell
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Scan chain cell – Read Output
MUX
FFD
Scan_in
SE
clk
Q
Q
rst
Scan cellNew Scan Cell
MUX
FFD
Scan_in
SE
clk
Q
Q
rst
MUX
Aging Sensor
sel
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Scan chain cell
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agingsensor.v
Design Compiler
agingsensor_dc.vScancell
newscancell.v
Design Compiler
newscancell_dc.v
IC Compiler
agingsensor.CELagingsensor.FRAMIC Compiler
newscancell.CELnewscancell.FRAM
New ScanCell Flow
Std cell lib
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Architectural choices, RTL compilation and simulation(VCS)
Logic synthesis (Design Compiler)
Formal verification (Formality)
Generation of test patterns (TetraMAX)
Physical design (IC Compiler)
Physical Verification (Hercules)
Layout Parasitics Extraction (StarRC)
SPICE-level simulation of completed design (HSPICE)
Basic DC Synthesis(Design Compiler)
Basic Scan Synthesis Flow(Design For Test Compiler)
Update the netlist
Add to Reference Library (New scan cell library)
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Top-down design with aging sensor embedded
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Case Study: Johnson Counter
…n=total # of SDFF;t=user defined parameter; # application dependent for(i=0;i<=n;i+t) {Replace the SDFFARX1 with sensorSDFFX1; Add global control signals; D=deg_in; }…
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Case Study: Johnson Counter
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Case Study: Johnson Counter
t=2
t=1
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Future work Verification Tradeoff between # of sensor vs. accuracy Placement of the sensor Both NBTI and PBTI Optimize area Trigger recovery Silicon Validation
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Thanks! Q & A