A Strategy for Routing the MPC8544E in a Six-Layer PCB · Figure 2. Example Six-Layer PCB Stackup...

Freescale SemiconductorApplication Note

© Freescale Semiconductor, Inc., 2008. All rights reserved.

This application note is a design guide to assist the customer in creating a low-layer, low-cost, PCB design when using the MPC8544E device. Key items of discussion include assumed PCB stackup, power delivery, and proper signal referencing. Additionally, layout plots for the device fan-out are also included.

NOTEThe schematic and Gerber data shown within this application note are intended merely to demonstrate the fan-out and power delivery strategy necessary to achieve a six-layer PCB. The schematic and Gerber data does not include all the decoupling, nor do they show all the necessary pull-ups and AC caps required outside the BGA fan-out area. This level of detail is captured as part of the MPC8544E development system.

Document Number: AN3535Rev. 0, 2/2008

Contents1. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22. Ballmap Organization . . . . . . . . . . . . . . . . . . . . . . . . . 23. Interface Support in Six Layers . . . . . . . . . . . . . . . . . 34. Board Stackup Considerations . . . . . . . . . . . . . . . . . . 45. Signal Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66. Via Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97. Power and Ground Strategy . . . . . . . . . . . . . . . . . . . 108. Signal Layer Gerber Plot . . . . . . . . . . . . . . . . . . . . . 209. Fan-Out Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 24

10. Current Delivery in the BGA Field . . . . . . . . . . . . . . 3911. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

A Strategy for Routing the MPC8544E in a Six-Layer PCBby Michael George

NMG ApplicationsFreescale Semiconductor, Inc.Austin, Texas

A Strategy for Routing the MPC8544E in a Six-Layer PCB, Rev. 0

2 Freescale Semiconductor

References

1 ReferencesTable 1 lists references mentioned in this application note, as well as useful resources for further reading.

2 Ballmap OrganizationThe MPC8544E is a 783-pin, 28 × 28 BGA array. The bus organization of the device is shown in Figure 1.

Figure 1. MPC8544E Bus Groupings (viewed from the top of the device)

Table 1. References

Document Source

IPC Standards:IPC-D-275IPC-2221AIPC-2152

www.ipc.org

New Correlations Between Electrical Current and Temperature Rise in PCB TracesJohannes Adam,Flomerics Ltd.

20th IEEE SEMI-THERM Symposium

0-7803-8363-X/04/$20.00 ©2004 IEEE

www.flomerics.com/flotherm/technical_papers/t341.pdf

Current-Carrying Capacity, Martin Tarr, University of Bolton www.ami.ac.uk/courses/ami4817_dti/u02/pdf/meah0221.pdf

Interactive trace-width calculator http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator

TSEC

Srds2

PCI and3.3 V I/O

Srds1

LocalBus

DDR

A1 A28

PowerCore


Freescale Semiconductor 3

Interface Support in Six Layers

3 Interface Support in Six LayersThough the MPC8544E device can be fully broken out in six layers, there are a handful of signals that are not necessarily optimal from a signal integrity perspective, mainly due to splits in the reference plane. Such cases are very limited and are, therefore, manageable. Table 2 enumerates the MPC8544E interfaces and indicates whether there is proper signal referencing in the six-layer PCB fan-out example.

Table 2. Interface Support in Six Layers

Interface Configuration Reference Plane Comment

DDR2 Full 64-bit + ECC DDR Data—GND

DDR ADDR—1.8 V

DDR CLKs—1.8 V

Fully supported.

ETSEC RGMII RGMII I/O—2.5 V

GTX_CLK125—GND

Both Ethernet ports can be fully broken out in RGMII mode.

Some signals cross split boundaries; therefore, stitching caps would likely be beneficial.

POR Config All user defined POR pins are accessible.

GND and PWR Fully supported. Some POR pins cross split boundaries, but because they are static, there is no concern.

PCI Full 32-bit PCI GND and PWR

LB All signals are accessible GND and PWR LB_LAD[23:31] cross split boundaries. These signals are not edge sensitive, therefore imperfections in their transitions can be managed. Use of stitching caps could be used.

SERDES1 All eight lanes accessible GND Fully supported

SERDES2 Both lanes accessible GND Fully supported

IRQ All IRQs (0–11) and IRQ_OUT usable

GND and PWR Fully supported

JTAG/COP All signals are accessible GND and PWR Fully supported

DUARTS Both UART ports are fully accessible

GND and PWR Fully supported

Power pins and AVDD filters

All unique powers accessible N/A Fully supported

I2C Both I2C port accessible GND and PWR Fully supported

Clocking SYSCLK and RTC accessible GND and PWR Fully supported



Board Stackup Considerations

4 Board Stackup ConsiderationsThis section presents the considerations associated with the PCB and its stackup. Table 3 lists the target impedances needed in a six-layer design.

Additional considerations for the stackup include

• Must utilize high-volume, low-cost, PCB technology

• Routing density

• Aspect ratio less than 10:1

• Drill size set at 10 mil

• Common core construction

• Proper signal referencing for all critical signals

4.1 Stackup ProposalFigure 2 shows a viable stackup for achieving the target impedances noted in Table 3. The target card thickness used is 62 mils (±7 mils). All signal routing is done on the inner two signal layers, or on the top and bottom signal layers. No signal routing is performed on the power and ground layers.

Table 3. Target Impedance for a Typical MPC8544E Design

Interface Connection Target Impedance

DDR2 MPC8544E-to-DDR2 memory Single-ended impedance = 55–60 ΩDifferential impedance = 100 Ω ± 10%

SERDES1 (PCIe) MPC8544E-to-PCIe connector or device Microstrip

Single-ended impedance = 60 ± 15%

Differential impedance = 100 Ω ± 20%

Stripline



SERDES2 (SGMII/PCIe)

MPC8544E-to-connector or device Microstrip



Stripline



All other MPC8544E signals

MPC8544E-to-connector or device Single-ended interface = 55–60 Ω

Other system Items:

Ethernet differential Ethernet Phy to connector Differential impedance = 100 Ω ± 15%



Board Stackup Considerations

Figure 2. Example Six-Layer PCB Stackup (Provided by Sanmina-SCI; www.sanmina-sci.com)

Table 4. Impedance Information (Provided by Sanmina-SCI; www.sanmina-sci.com)

Layer Type Line Width Center-to-Centertpd

(ps/in.)Impedance

(Ω)

1 Single-endedmicrostrip

5 mil n/a 153 55.15

1 Differentialmicrostrip

4 mil 8 mil 154 93.28


5 mil 12 mil 154 96.54

3 Single-endedstripline

4 mil n/a 179 56.0

3 Differentialstripline

4 mil 10 mil 181 96.38

4 Single-endedstripline

4 mil n/a 179 56.0



Signal Breakout

5 Signal Breakout

5.1 Inside the BGA areaThe key strategy used in breaking out the MPC8544E is centered on the use of inexpensive through-hole vias and two-track routing for the inner and bottom layers (see Figure 4). For all mainstream PCB fabrication shops, this approach is considered “production-level” technology and is capable of being produced in high volumes. Additionally, this approach produces a cheaper overall PCB design, avoiding the additional cost associated with blind- and buried-type approaches.

The key items of the strategy are as follows:

• 1-mm (39.3 mil) ball pitch

• Plastic substrate

• 22-mil attach pad on top layer

• 19-mil via pad

• 28-mil anti-pad

• Single-track routing on top layer (between attach pads)

• Two-track routing on inner layers and on the bottom layer

— Using 4-mil traces and 4-mil space

4 Differentialstripline

4 mil 10 mil 181 96.38

6 Single-endedmicrostrip

5 mil n/a 153 55.15


4 mil 8 mil 154 93.28


5 mil 12 mil 154 96.54

Table 4. Impedance Information (Provided by Sanmina-SCI; www.sanmina-sci.com) (continued)

Layer Type Line Width Center-to-Centertpd

(ps/in.)Impedance

(Ω)



Signal Breakout

Figure 3 and Figure 4 show the track routing strategy used for each of the signal layers.

Figure 3. Signal Routing (Top and Layer #2)

2 traces per rowWidth >= 4 mil

Signal Layer #2

3 traces per rowWidth = 4 milSpace = 4 mil

Drill = 10 milPad = 19 mil

Attach Pad 22 mil

Row 1

Row 12

Row 7

Signal Layer #1 (top)



Signal Breakout

Figure 4. Signal Routing (Signal Layer 3 and Bottom)

5.2 Outside the BGA AreaInside the BGA area, two-track routing limits the minimum trace width to 4 mils and the minimum spacing to 4 mils. Outside the BGA area, this is not the case. Since wider traces have less dielectric loss, the designer may find it useful to use larger trace widths once outside the via array. Similarly, in the cases of differential pairs, the air gaps can be adjusted as needed in order to hit desired impedance targets.

5.3 Trace Spacing Outside the BGA AreaTo minimize crosstalk opportunities once outside the BGA area, the spacing between differing signal groups must be observed. This spacing, denoted as ‘S,’ is based on the dielectric thickness ‘H’ (shown in Figure 5). For the stackup shown in Figure 2, the dielectric thickness is 4.0. Using a 3:1 spacing rule, the air gap between differing signal groups should be at least 12 mil.

Signal Layer #3

2 traces per rowWidth = 4 mil

Signal Layer #4

2 traces per rowWidth = 4 mil

Row 3

Row 12

Row 7



Via Usage

Figure 5. Trace Spacing Outside the BGA Area

6 Via UsageFor the six-layer PCB a 10-mil drill is used. A 10-mil drill has favorable cost advantages because smaller drill sizes incur additional cost. During fabrication, the drill tolerance is specified as +0/–3 mil, giving a finished hole size (FHS) of approximately 7–7.5 mil.

Using a 10-mil drill, an aspect ratio of ~ 6:1 is realized. This aspect ratio is based on an 0.062-inch board thickness and is well within the high-volume production capabilities of all mainstream PCB vendors. Figure 6 depicts the via model used for the six-layer PCB.

Figure 6. Cross Section of PCB

Reference Plane

Trace 1 Trace 2

H

S

39.3 mil (1 mm) BGA Pitch

19.3 mil

11.3 mil

28 mil Anti-Pad

Standard Via

= Section of power plane flowing between vias

19 mil Pad

7–7.5 mil FHS

= Outer layer signal tracks= Inner layer signal tracks

= Via barrel/via pad copper

= PCB

Legend

10 mil Drill



Power and Ground Strategy

7 Power and Ground StrategyThe MPC8544E requires several power supplies for each subsystem (DDR, Ethernet, SerDes, and so forth) as well as the core itself. The total number of supplies a system needs depends on the interfaces, the interface voltages required to connect with external peripherals, and the number of those voltages that are common and sharable.

Consult the MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications for accurate voltage and current requirements. For convenience, Table 5 provides a snapshot of the MPC8544E power requirements at the date of this application note. The table also reflects the unique power splits constructed in the six-layer PCB example (refer to the Power Rails column). In short, a total of six unique power rails are used.

Note that Table 5 lists the power requirements for the MPC8544E only; it does not include requirements for external devices, memory, and so forth. At the very least, additional power is needed to drive connected I/O pins, and the internal logic of the other devices often shared with the MPC8544E supplies.

7.1 Power PlanesThe following pictures, Figure 7 through Figure 8, highlight the power strategy used for the six-layer PCB. The ground reference for the PCB is a solid ground plane at layer 2. Since it is a solid plane with no splits, the ground layer is not shown.

Table 5. MPC8544E Power Requirements 1

1 These figures are subject to change without notice. Consult the latest version of the MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications.

Power Rails SymbolTypical Voltage Tolerance PMAX

Core power VDD_COREAVDD_COREAVDD_PLATAVDD_PCIAVDD_LBIUAVDD_SRDSAVDD_SRDS2

1.0 V ±50 mV 7.8 W

SerDes SVDDXVDD

1.0 V ±50 mV 0.71W

DDR2 bus GVDD 1.8 V ±90 mV 2.5 W

Ethernet LVDDTVDD

2.5 V ±125 mV 0.24 W

Local bus BVDD 3.3 V ±125 mV 0.33 W

Misc/PCI OVDD 3.3 V ±125 mV 0.33 W




Figure 7. Power Plane (Layer 5 of 6)

Figure 8. SVDD, XVDD(Layer 6 of 6—Bottom)




For sensitive supplies (such as XVDD and SVDD), a key requirement for power sharing is that the planes be relatively isolated. One effective strategy is to route the power planes separately and tie them together at the power source. See Figure 9.

Figure 9. Common Source Split Planes

Another strategy is to use a low-pass filter to eliminate coupled noise, as long as there is sufficient current capacity in the components and connections. In either case, once separated, treat the two as independent power planes and route and bypass them separately.

7.2 Current DeliveryAn important consideration in the six-layer PCB is ensuring all power rails have sufficient copper for proper current delivery. The highest power on the MPC8544E is VDD_CORE. The max power requirement for VDD_CORE is 7.8W.

Within a congested BGA array, the current travels down multiple 11-mil trace segments as it travels to the power pins, assuming the via stackup referenced in Figure 6 is used. The current-carrying capacity of these 11-mil traces is highly dependent on the current model chosen, either IPC2221A or the newer research performed by Johannes Adam of Flomerics Ltd. For greater detail on these two approaches see Section 10, “Current Delivery in the BGA Field.”

MPC8544E

1.0 V Power Supply

VDD_PLAT

XVDDSVDD




In short, Table 6 depicts the current capacity differences between the two approaches assuming a maximum temperature rise of 20°C. Additionally, the last column highlights the current capacity assumed for the MPC8544E six-layer PCB.

Table 6. Current Capacity of an 11-mil Trace Adam’s Model vs. IPC

Taking the last column from Table 6 and the number of 11-mil channels achieved in the six-layer PCB, Table 7 highlights the current capacity for VDD_CORE.

7.3 PLL FiltersThe MPC8544E has six PLLs which each require a filter circuit. The PLL pins are placed on the package in order to minimize noise and to allow ease during layout. An example layout for the filters are shown in Figure 10. This figure shows example layout for an AVDD filter. For the exact filter values refer to the MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications.

To ensure a high quality filter is realized, use the following rules:

• Place the components of the filter as close a possible to their respective pin

• Keep the traces as short as possible

• Use a 10-mil trace width or larger. An area fill is also a possibility.

LocationCopper Plating

(oz.)

11-mil Trace: Adam’s Model

(A)

11-mil Trace: IPC2221A

(A)

11-mil Trace: Capacity Assumed for theMPC8544E Six-Layer PCB

(A)

Outer 0.5 1.210 0.777 1.0

1.0 1.711 1.285 1.5

1.5 2.420 1.730 N/A

2.0 3.422 2.130 N/A

Inner 0.5 1.149 0.390 0.75

1.0 1.625 0.582 1.1

1.5 2.299 0.865 N/A

2.0 3.251 1.065 N/A

Table 7. Current Capacity Achieved in the Six-Layer PCB

Power RailCopper Weight

Used(oz.)

No. of 11-mil TracesSupplying Power

Current per Trace

(A)

Total Current Suppliedin Six-Layer PCB

(A)

Assumed Worst Case Current (A)

VDD_CORE 1.0 10 1.1 11 7.8 (7.8 W/1.0 V)




• Maintain at least 20-mil clearance between the filter and other signals.

Figure 10. Example Layout for AVDD Filters

7.4 Sharing Power SuppliesThe six-layer design referenced in this application note assumes all processor powers referenced in Table 5 are supplied by unique power supplies. If the customer chooses, further sharing of power supplies can be achieved to reduce the number of supplies needed at the board level. Table 8 shows some acceptable options for sharing MPC8544E power rails.

Table 8. MPC8544E Power Requirements

Power Source Symbol Voltage Comments

Core power + PLL filter

VDD_COREAVDD_COREAVDD_PCIAVDD_PLATAVDD_LBIUAVDD_SRDSAVDD_SRDS2

1.0 V PLLs are sourced from RC filter circuit derived from 1.0-V rail.

SerDes SVDDXVDD

Separate filtered plane but derived from the same 1.0-V power regulator.

Memory GVDD 1.8 V Unique rail on the MPC8544E device. Could possibly be shared with another 1.8-V device on the board.

Ethernet LVDDTVDD

2.5 V 2.5 V is readily usable by most PHYs; however, 3.3 V is not suitable for RGMII mode.

Local bus BVDD 2.5 V requires low-voltage flash memory and so forth

Or alternatively

Filters




7.5 Bypass Capacitor PlacementBecause of the high current transients on the VDD_CORE power pins, take care to bypass these power pins and to provide a good connection between the BGA pads and the power and ground planes. In particular, the SMD capacitors should have pads directly attached to the via ring (or even better, within it using via-in-pad methods).

Ethernet LVDDTVDD

3.3 V 3.3 V is not suitable for RGMII mode

Local bus BVDD

PCI/Misc OVDD

Table 8. MPC8544E Power Requirements (continued)

Power Source Symbol Voltage Comments




Figure 11 shows the dispersion of VDD_CORE power pins along with the ground pattern. This is a bottom view of the center portion of interest within the BGA array.

Figure 11. MPC8544E VDD_CORE and Ground Pattern (Bottom View)

Ground

L M N P R T U

11

12

13

14

15

16

V W Y

17

18

19

20

21

22

23

VDD_CORE

24




After the power and grounds are escaped, the SMD 0402 capacitors can be placed so that the capacitor pads attach directly to the power vias on the side. Minimize or eliminate the trace between the via and the capacitor pad. Figure 12 shows three possible attachment methods.

Figure 12. MPC8544E SMD Capacitor Via Placement

Vias Embedded in Pads Vias to the Side of Pads

All are SMD0402

Vias Offset From PadsBest Good OK




Figure 13 shows the relative attachment of the SMD 0402 capacitors using any of the methods shown in Figure 12. This is a view through the top of the board.

Figure 13. MPC8544E CORE and Ground SMD 0402 Capacitor Placement (Bottom View)

Other capacitors, such as those required for the other power rails, are not shown but can be attached in the same manner. If the PCB is not permitted to use via-in-pad connections, the capacitors can be shifted to attach to a pad in the area between the BGA pads. In that case, use the same relative pattern, but each capacitor shifts a little.

VDD_PLAT GROUND

L M N P R T U

11

12

13

14

15

16

V W Y

17

18

19

20

21

22

23

VDD_CORE

24

C

C C C C C

C C C C C C

22

C

C C C C C C




7.6 Bulk CapacitorsBulk capacitors can be placed outside the periphery of the MPC8544E die, as close as reasonably possible. Systems with heatsinks and/or sockets probably need some additional spacing, but the high-frequency capacitors handle the fastest transients, allowing the bulk capacitors to be spaced a little further away. Keep them within 2 cm. Figure 14 shows the MPC8544E VDD_CORE bulk capacitor placement.

Figure 14. MPC8544E Bulk Capacitor Placement (Top View)

MPC8544E

0.46 mils

Low-ESRBulk Capacitors

0.46 mils

VCORE PowerSplit

A28A1



Signal Layer Gerber Plot

8 Signal Layer Gerber PlotFigure 15 through Figure 18 show the signal layers for the six-layer PCB example. The intent is to demonstrate that the MPC8544E signals can be broken in a six-layer PCB; the figure does not include all the decoupling, nor does it show all the necessary pull-ups, AC caps, and other circuitry that would be required outside the BGA fan-out area. This level of detail is captured as part of the MPC8544E development system.

Figure 15. Top Gerber Plot (Layer 1 of 6)




Figure 16. Signal 2 Gerber Plot (Layer 3 of 6)




Figure 17. Signal 3 Gerber Plot (Layer 4 of 6)




Figure 18. Bottom Gerber Plot (Layer 6 of 6)



Fan-Out Schematics

9 Fan-Out SchematicsThis section contains the fan-out schematics used to perform the six-layer PCB study. It does not include all the decoupling, nor does it show all the necessary pull-ups, AC caps, and other circuitry that would be required outside the BGA fan-out area. This level of detail is captured as part of the MPC8544E development system.



Fan-Out Schematics

Figure 19. DDR Section

MCK5

MCK1MCK1MCK2MCK2MCK3MCK3MCK4MCK4

MCK0MCK0

MCK5 D13

C23A22E17B16K5D2M3P2

D24B22C18A17J5C1M4M2E13

G12D14F11C11G14F14C13D12

C25B23D18B17G4C2L3L2F13

A4B5B13

B7G8C8A10D9C10A11F9E9B12A5A12D11F7E10F10

B4C5E7D3H6C4G6H10K10G10H9F6E6H7E5

A28

8

01234567

012345678

01234567

012345678

012

0123456789

101112131415

MDQS[0:8]9A6 10A6

9D2 10D3MVREF

MDQS[0:8]9A6 10A6

MECC[0:7]9A2 10A3

C10.1µF

MDM[0:8]9A2 10A3

MBA[0.2]9B2 10B3

MA[0:15]9B2 10B3

9C2 10C39C3 10C3 9C2 10C3 9C29C210C310C39C29C210C310C310C310C39C29C2

MWEMRASMCASMSC0MCS1MCS2MCS3

MCKE0MCKE1MCKE2MCKE3MODT3MODT2MODT1MODT0

MDQS8

MDQS0MDQS1MDQS2MDQS3MDQS4MDQS5MDQS6MDQS7

MDQS0*MDQS1*MDQS2*MDQS3*MDQS4*MDQS5*MDQS6*MDQS7*MDQS8*

MECC0MECC1MECC2MECC3MECC4MECC5MECC6MECC7

MDM0MDM1MDM2MDM3MDM4MDM5MDM6MDM7MDM8

MBA0MBA1MBA2

MA0MA1MA2MA3MA4MA5MA6MA7MA8MA9

MA10MA11MA12MA13MA14MA15

MWE*MRAS*MCAS*MCS0*MCS1*MCS2*MCS3*MCKE0MCKE1MCKE2MCKE3MODT3MODT2MODT1MODT0

MVREF

MPC8544DDR_SDRAM

1 OF 10

MCK5*

MCK1MCK1*MCK2MCK2*MCK3MCK3*MCK4MCK4*

MDQ1MDQ2MDQ3MDQ4MDQ5MDQ6MDQ7MDQ8

MDQ10MDQ11MDQ12MDQ13MDQ14MDQ15MDQ16

MDQ20MDQ21MDQ22MDQ23MDQ24MDQ25MDQ26MDQ27MDQ28

MDQ30MDQ31MDQ32

MDQ34MDQ35MDQ36MDQ37MDQ38MDQ39MDQ40MDQ41MDQ42MDQ43MDQ44MDQ45MDQ46MDQ47MDQ48MDQ49

MDQ51MDQ52MDQ53MDQ54MDQ55MDQ56MDQ57MDQ58MDQ59MDQ60MDQ61MDQ62MDQ63MDIC1MDIC0

MCK0A9B9

J11H11

J6K6A8B8

J13H13H8J8

9C29D29D29D29D29D2

10C310C310C310D310D310D3

MCK0*

MCK5

A26B26C22D21D25B25D22E21A24A23B20A20A25B24B21A21

0123456789101112131415

MDQ[0:63]10B6 9C6

E19D19E16C16F19F18F17D16B18A18A15B14B19A19A16B15

16171819202122232425262728293031

D1F3G1H2E4G5H3J4B2C3F2G2A2B3E1F1

32333435363738394041424344454647

L5L4N3P3J3K4N4P4J1K1P1R1J2K2N1R2

48495051525354555657585960616263

MDQ29

MDQ33

MDQ18

MDQ9

MDQ17

MDQ50

MDQ19

MDQ0

GVDD

R4

R3

1818

K15H15

MDIC1MDIC0



Fan-Out Schematics

Figure 20. SerDes1 and SerDes2

PEX1_RX1_PPEX1_RX1_NPEX1_RX2_PPEX1_RX2_NPEX1_RX3_PPEX1_RX3_N

PEX1_RX0_PPEX1_RX0_N

T22SD_TST_CLK

MPC8544SERDES 1

SD_RX1SD_RX1*SD_RX2SD_RX2*SD_RX3SD_RX3*

SD_RX0N28N27P26P25R28R27T26T25

11D611D611D611D611D611D611C611C6

SD_RX0*

T23SD_TST_CLK_PSD_TST_CLK_N

SD_TST_CLK*

PEX1_TX1_PPEX1_TX1_NPEX1_TX2_PPEX1_TX2_NPEX1_TX3_PPEX1_TX3_N

PEX1_TX0_PPEX1_TX0_N

SD_TX1SD_TX1*SD_TX2

SD_TX2*SD_TX3

SD_TX3*

SD_TX0 M23M22N21N20P23P22R21R20

11D311D311D311D311D311D311C311C3

SD_TX0*

PEX2_RX1_PPEX2_RX1_NPEX2_RX2_PPEX2_RX2_NPEX2_RX3_PPEX2_RX3_N


SD_RX5SD_RX5*SD_RX6SD_RX6*SD_RX7SD_RX7*

SD_RX4Y26Y25

AA28AA27AB26AB25AC28AC27

11C611C611C611C611C611C611C611C6

SD_RX4*PEX2_TX1_PPEX2_TX1_NPEX2_TX2_PPEX2_TX2_NPEX2_TX3_PPEX2_TX3_N

PEX2_TX0_PPEX2_TX0_N

SD_TX5SD_TX5*SD_TX6

SD_TX6*SD_TX7

SD_TX7*

SD_TX4 U21U20V23V22W21W20Y23Y22

11C311C311C311C311C311C311C311C3

SD_TX4*

TP5TP6

U28SD_REF_CLKU27

SD_REF_CLK_PSD_REF_CLK_N

SD_REF_CLK*TP141TP142

V28SD_PLL_TPD*V26

SD_PLL_TPDSD_PLL_TPA

SD_PLL_TPA*TP7TP8

AE28SD_IMP_CAL_TXM26

SD_IMP_CAL_TXSD_IMP_CAL_RX

SD_IMP_CAL_RX

TP13TP14

R2

1

0 No_Stuff

R1

No_Stuff 1

0

XVDD

R8

R7

100200

2 OF 10


AG4SD2_TST_CLK

MPC8544SERDES 2

SD2_RX0SD2_RX0*

AD26AD25

11B611B6

AF4SD2_TST_CLK_PSD2_TST_CLK_N

SD2_TST_CLK*

SGMII_RX1_NSGMII_RX1_P

SGMII_RX0_NSGMII_RX0_P

SD2_RX3*SD2_RX3

SD2_RX2*AC1AD1AA2AB2

TP1TP2TP3TP4

SD2_RX2

SGM II_TX0_P

SGMII_TX1_NSGMII_TX1_P

SGMII_TX0_N

SD2_TX2

SD2_TX3*SD2_TX3

AB4AC4

Y5AA5

TP89TP90

TP128TP129

SD2_TX2*

TP9TP10

AE2SD2_REF_CLKAF2

SD2_REF_CLK_PSD2_REF_CLK_N

SD2_REF_CLK*TP17TP18

AG3SD2_PLL_TPD*AH1

SD2_PLL_TPDSD2_PLL_TPA

SD2_PLL_TPA*TP11TP12

Y1SD2_IMP_CAL_TX*AH3

SD2_IMP_CAL_TXSD2_IMP_CAL_RXSD2_IMP_CAL_RX*

TP15TP16

R6

1

0 No_Stuff

R5

No_Stuff 1

0

XVDD

R10

R9

100200

3 OF 10

PEX3_TX0_NPEX3_TX0_P

SD2_TX0*

AA21AA20

11B311B3

SD2_TX0

PCI EXPRESS #1 X4

PCI EXPRESS #0 X4

PCI EXPRESS #1 X4

PCI EXPRESS #0 X4

PCI EXPRESS #2 X1PCI EXPRESS #2 X1

AGND_SRDS2AF1

AGND_SRDSV27



Fan-Out Schematics

Figure 21. PCI 32-Bit

AD17AA14AE12AC10

AE14AC14

AB8AD6AH10AG10AF9

AE6

0123

DUT_PCI32_PERR*DUT_PCI32_SERR*

PCI32_SLOT_REQ*PCI_REQ1PCI_REQ2PCI_REQ3PCI_REQ4

PCI32_SLOT_GNT*

DUT_PCI32_C_BEX[3:0]12D2

PCI1_C_BE0*PCI1_C_BE1*PCI1_C_BE2*PCI1_C_BE3*

PCI1_PERR*PCI1_SERR*

PCI1_REQ0*PCI1_REQ1*PCI1_REQ2*PCI1_REQ3*

PCI1_GNT0*

MPC8544PCI1

4 OF 10

PCI1_AD0AA16AB18AB17AD19AE19AC17AE18AF18AB16

Y15AD16AA15AB15AC15AE15

Y14

0123456789101112131415

AE11AF12AC12AB12AB11AC11AE10AD10

AE9AC9AB9

AG12AH12

AF8AD8AE8

16171819202122232425262728293031

PCI1_AD1PCI1_AD2PCI1_AD3PCI1_AD4PCI1_AD5PCI1_AD6PCI1_AD7PCI1_AD8PCI1_AD9PCI1_AD10PCI1_AD11PCI1_AD12PCI1_AD13PCI1_AD14PCI1_AD15PCI1_AD16PCI1_AD17PCI1_AD18PCI1_AD19PCI1_AD20PCI1_AD21PCI1_AD22PCI1_AD23PCI1_AD24PCI1_AD25PCI1_AD26PCI1_AD27PCI1_AD28PCI1_AD29PCI1_AD30PCI1_AD31

AB14 DUT_PCI32_PARPCI1_PAR

AH26 CLK_DUT_PCIXPCI1_CLK

AD12AD13AF13AA13AC13

DUT_PCI32_FRAME*DUT_PCI32_TRDY*DUT_PCI32_IRDY*

DUT_PCI32_STOP*DUT_PCI32_DEVSEL*

PCI1_FRAME*PCI1_TRDY*PCI1_IRDY*

PCI1_STOP*PCI1_DEVSEL*

AG6 PCI_IDSELPCI1_IDSEL

PCI1_REQ4*

AC8AH11AG11AE7

PCI_GNT1PCI_GNT2PCI_GNT3PCI_GNT4

PCI1_GNT1*PCI1_GNT2*PCI1_GNT3*PCI1_GNT4*

TP23TP22TP21TP20

TP25

TP19

TP24TP143TP144TP145

12B5

12A312B312B312B312A3

12B312B3

12B3

12B3

DUT_PCI32_AD[32:0]12D2



Fan-Out Schematics

Figure 22. Local Bus

J25 LBCTLLBCTL

MPC8544LOCAL BUS

5 OF 10

LAD0K22L21L22K23K24L24L25K25L28L27K28K27J28H28H27G27

0123456789101112131415

G26F28F26F25E28E27E26F24E24C26G24E23G23F22G22G21

16171819202122232425262728293031

LAD1LAD2LAD3LAD4LAD5LAD6LAD7LAD8LAD9LAD10LAD11LAD12LAD13LAD14LAD15LAD16LAD17LAD18LAD19LAD20LAD21LAD22LAD23LAD24LAD25LAD26LAD27LAD28LAD29LAD30LAD31

13B2

LAD[0:31]13A2

K18G19H19H20

LCS0LCS1LCS2LCS3

LCS0*LCS1*LCS2*LCS3* TP30

TP29TP28TP27

G16H16J16L18

LCS4LCS5LCS6LCS7

LCS4*LCS5_DMA_DREQ2*LCS6_DMA_DACK2*

LCS7_DMA_DDONE2* TP34TP33TP32TP31

J22H22H23H21

LWE0LWE1LWE2LWE3

LWE0*LWE1*LWE2*LWE3* TP38

TP37TP36TP35

J26 LALELALE 13C1

J20K20

LGPL0LGPL1

LGPL0_LSDA10LGPL1_LSDWE TP44

TP47

G20H18L20K19

LGPL2LGPL3LGPL4LGPL5

LGPL2_LO3_LSDDASLGPL3_LSDCAS

LGPL4_LGTA_LUPWAIT_LPBSELGPL5 TP43

TP49TP42TP45

L17 LCKELCKE TP48

H24J24

LCLK0LCLK1

LCLK0LCLK1 TP40

TP39

H25 LCLK2LCLK2 TP41

D27 LSYNC_INLSYNC_IN TP46

D28 LSYNC_OUTLSYNC_OUT TP26

LA27L19K16K17H17G17

2728293031

LA28LA29LA30LA31

LA[27:31]13D2

K26B27G28E25

LDP0LDP1LDP2LDP3

LDP0LDP1LDP2LDP3TP132

TP131TP130TP160



Fan-Out Schematics

Figure 23. Gigabit Ethernet—RGMII

MPC8544ETHERNET

6 OF 10

TSEC1_TXD0U1U2V1V2V3V5U5T5

0123

GMAC1_TXD[7:0]14C3

M6P6R6L7M8P7N7M7

TP155TP154TP153TP152

TSEC1_TXD4TSEC1_TXD5TSEC1_TXD6TSEC1_TXD7

TP149TP148TP147TP146

TSEC1_TXD7TSEC1_TXD6TSEC1_TXD5TSEC1_TXD4TSEC1_TXD3TSEC1_TXD2TSEC1_TXD1

U4T3V6T1

TSEC1_TX_ENTSEC1_TX_ERTSEC1_TX_CLKTSEC1_GTX_CLK

TP151TP150

TSEC1_GTX_CLKTSEC1_TX_CLKTSEC1_TX_ERTSEC1_TX_EN

T4R5

TSEC1_CRSTSEC1_COL

TSEC1_COLTSEC1_CRS

14C3

14C3

TSEC1_RXD0T6T7T8U8T9

T10U9

U10

0123

GMAC1_RXD[7:0]14D3

TSEC1_RXD4TSEC1_RXD5TSEC1_RXD6TSEC1_RXD7

TSEC1_RXD7TSEC1_RXD6TSEC1_RXD5TSEC1_RXD4TSEC1_RXD3TSEC1_RXD2TSEC1_RXD1

U7R9V7

TSEC1_RX_ER

TSEC1_RX_CLKTSEC1_RX_ERTSEC1_RX_DV14D3

14D3

GMAC1_RX_DV

GMAC1_RX_CLK

AC7MDCEC_MDC14A1

Y9MDIOEC_MDIO14A1

TSEC3_TXD0

TSEC3_TXD7TSEC3_TXD6TSEC3_TXD5TSEC3_TXD4TSEC3_TXD3TSEC3_TXD2TSEC3_TXD1

TSEC3_TXD0

TSEC3_TXD3TSEC3_TXD2TSEC3_TXD1 14B4

14B414B414B4TSEC3_TXD4

TSEC3_TXD7TSEC3_TXD6TSEC3_TXD5

N6L8L10R7

TSEC3_TX_ENTSEC3_TX_ER

TSEC3_TX_CLKTSEC3_GTX_CLK

TP157TP156

TSEC3_GTX_CLKTSEC3_TX_CLKTSEC3_TX_ERTSEC3_TX_EN

L9M9

TSEC3_CRSTSEC3_COL

TSEC3_COLTSEC3_CRS

14B4

14B4

P10N9N10R8L11M11N11P11

TSEC3_RXD0

TSEC3_RXD7TSEC3_RXD6TSEC3_RXD5TSEC3_RXD4TSEC3_RXD3TSEC3_RXD2TSEC3_RXD1

TSEC3_RXD0

TSEC3_RXD3TSEC3_RXD2TSEC3_RXD1 14C4

14C414B414B4TSEC3_RXD4

TSEC3_RXD7TSEC3_RXD6TSEC3_RXD5

P8R11P9

TSEC3_RX_DV

TSEC3_RX_CLKTSEC3_RX_ER

TSEC3_RX_DV

TSEC3_RX_CLKTSEC3_RX_ER 14C4

14C4

T2TP50EC_GTX_CLK125

CLK_DUT_GTXCLK125

GMAC1_TXD0GMAC1_TXD1GMAC1_TXD2GMAC1_TXD3

GMAC1_RXD0GMAC1_RXD1GMAC1_RXD2GMAC1_RXD3



Fan-Out Schematics

Figure 24. Miscellaneous Control

MPC8544MISC / OTHERS

7 OF 10Y3AA3

AB5

THERM1THERM0

TRIG_OUT

TEMP_ANODETEMP_CATHODE

TRIG_OUT TP84

TP83TP82

AC5

AG16AG19

TRIG_IN

HRESETSRESET

TRIG_IN

HRESET*SRESET* TP87

TP86

TP85

Y7W9

MSRCID0MSRCID1

MSRCID0TP92TP91

AA9AB6AD5

MSRCID2MSRCID3MSRCID4MSRCID4 TP95

TP94TP93

AE17AC20

L2_TSTCLKL1_TSTCLK

L2_TSTCLKL1_TSTCLK TP103

TP102

10D3 9D2

AG18

AA10AA11

MCP

DMA_DREQ0DMA_DREQ1

MCP*

DMA_DREQ0*DMA_DREQ1*TP53

TP52

TP51

AG15 HRESET_REQHRESET_REQ* TP88

AH21 IIC1_SDAIIC1_SDA TP158

AG21 IIC1_SCLIIC1_SCL TP159

MSRCID3MSRCID2MSRCID1

Y8 MDVALMDVAL TP96

AH13AE16AH16

TEST_SELCLK_OUT

SYSCLKSYSCLK TP99TP98TP97

CLK_OUTTEST_SEL*

AG13 IIC2_SCLIIC2_SCL TP100

AG14 IIC2_SDAIIC2_SDA TP101

AH28AF28AG28

TDITDOTCKTCK TP106

TP105TP104

TDOTDI

AH22AH27

TRSTTMS

TRST*TMS TP108

TP107

AH17 ASLEEPASLEEP TP109

AH19 LSSD_MODELSSD_MODE* TP110

AF15 RTCRTC TP111

AF26 GPOUT7TP112

AG26AF25AF21

GPOUT6GPOUT5GPOUT4

TP115TP114TP113

GPOUT7

AH25 GPOUT3TP116

AG27AH23AF22

GPOUT2GPOUT1GPOUT0GPOUT0 TP119

TP118TP117

GPOUT6GPOUT5GPOUT4GPOUT3GPOUT2GPOUT1

AE20 GPIN7TP120

AG25AF23AD22

GPIN6GPIN5GPIN4

TP123TP122TP121

GPIN7

AE21 GPIN3TP124

AD23AG24AH24

GPIN2GPIN1GPIN0GPIN0 TP127

TP126TP125

GPIN6GPIN5GPIN4GPIN3GPIN2GPIN1

Y13Y12

DMA_DACK0DMA_DACK1

DMA_DACK0*DMA_DACK1*TP55

TP54

AA7Y11

DMA_DDONE0DMA_DDONE1

DMA_DDONE0*DMA_DDONE1*TP57

TP56

AH15UDE UDE*TP58

AG22IRQ0TP59

AF17AD21AF19

IRQ1IRQ2IRQ3

TP62TP61TP60

IRQ0

AG17IRQ4TP63

AF16AC23AC22

IRQ5IRQ6IRQ7 IRQ7TP66

TP65TP64

IRQ1IRQ2IRQ3IRQ4IRQ5IRQ6

AC19IRQ8TP67

AG20AE27AE24

IRQ9IRQ10IRQ11 IRQ11TP70

TP69TP68

IRQ8IRQ9IRQ10

AD14IRQ_OUT_ODIRQ_OUT*TP71

AH7UART_SOUT0TP72

AG7AH8AG8

UART_SIN0UART_CTS0UART_RTS0

TP75TP74TP73

UART_SOUT0UART_SIN0UART_CTS0*UART_RTS0*

AF7UART_SOUT1TP76

AH6AF6AG9

UART_SIN1UART_CTS1UART_RTS1

TP79TP78TP77

UART_SOUT1UART_SIN1UART_CTS1*UART_RTS1*

AH5AA12

CKSTP_INCKSTP_OUT

TP81TP80 CKSTP_IN*

CKSTP_OUT*

A13 TEST_INMAPAR_IN

10D3 9D2A6 TEST_OUT

MAPAR_OUT



Fan-Out Schematics

Figure 25. Power

MPC8544POWER8 OF 10

OVDD15AF20AE5

AD20AE13AD11AC6

AB13Y16AB7

AB10AC18AD9

AD15AE22AF10AF24AF27

OVDD12OVDD11OVDD9OVDD8OVDD5OVDD4OVDD1OVDD2OVDD3OVDD6OVDD7OVDD10OVDD13OVDD14OVDD16OVDD17

OVDD

SVDD_SRDS1M27N25P28R24R26T24T27U25W24W26Y24Y27

AA25AB28AD27

SVDD_SRDS15

SVDD

AG2AE26AD2

AC26AB1

SVDD_SRDS2_5SVDD_SRDS2_4SVDD_SRDS2_3SVDD_SRDS2_2SVDD_SRDS2_1

SVDD_SRDS2SVDD_SRDS3SVDD_SRDS4SVDD_SRDS5SVDD_SRDS6SVDD_SRDS7SVDD_SRDS8SVDD_SRDS9SVDD_SRDS10SVDD_SRDS11SVDD_SRDS12SVDD_SRDS13SVDD_SRDS14

XVDD_SRDS2_1Y6

AA6

AA23

AF5

AG5

XVDD_SRDS2_2

XVDD_SRDS2_3

XVDD_SRDS2_4

XVDD_SRDS2_5

XVDD

M21

N23

P20

R22

T20

U23

V21

XVDD_SRDS1

XVDD_SRDS2

XVDD_SRDS3

XVDD_SRDS4

XVDD_SRDS5

XVDD_SRDS6

XVDD_SRDS7

W22

Y20

XVDD_SRDS8

XVDD_SRDS9

GV

DD

34

N5

M1

E11

D20

H14

K14

K12

K3

J10

F15

E22

H12

H5

G11

G9

G7

G3

GV

DD

33

GV

DD

32

GV

DD

31

GV

DD

30

GV

DD

29

GV

DD

28

GV

DD

27

GV

DD

26

GV

DD

25

GV

DD

24

GV

DD

23

GV

DD

22

GV

DD

21

GV

DD

20

GV

DD

19

GV

DD

18

GV

DD

17

C21

E14

F5

E18

C24

E8

E2

D15

R3

D6

D4

C17

C14

C9

C7

B11

B1

GV

DD

16

GV

DD

15

GV

DD

14

GV

DD

13

GV

DD

12

GV

DD

11

GV

DD

10

GV

DD

9G

VD

D8

GV

DD

7G

VD

D6

GV

DD

5G

VD

D4

GV

DD

3G

VD

D2

GV

DD

1

U18

U16

U14

U12

T17

T15

VD

D23

VD

D22

VD

D21

VD

D20

VD

D19

VD

D18

VD

D17

T13

R18

R16

R14

R12

P17

P15

P13

N18

N16

N14

N12

M17

M15

M13

L14

L16

VD

D16

VD

D15

VD

D14

VD

D13

VD

D12

VD

D11

VD

D10

VD

D9

VD

D8

VD

D7

VD

D6

VD

D5

VD

D4

VD

D3

VD

D2

VD

D1

W11

W10R4

U3

W28

C28

AH

20

SE

NS

EV

DD

SE

NS

EV

SS

LVD

D1

LVD

D2

AV

DD

_S

RD

SA

VD

D_LB

IU

AV

DD

_P

CI1

AV

DD

_P

LAT

AH

18A

G1

J23

J21

H26

F23

F20J19

J18

L23

AH

14

R10N8

AV

DD

_S

RD

S2

BV

DD

9B

VD

D8

BV

DD

7B

VD

D6

BV

DD

5B

VD

D4

BV

DD

2B

VD

D1

AV

DD

_C

OR

E

TV

DD

2T

VD

D1

SENSEVDDTP133

SENSEVSSAVDD_SRDSAVDD_LBIU

TP136TP135TP134

AVDD_CORETP137AVDD_PCI1

AVDD_PLATAVDD_SRDS2

TP140TP139TP138

GVDD VDD

ANALOG FILTERS

VCC_2.5

DDR PWR

PCI EXPRESS RCVR PWR

PCI / MISC SIGNALS

PCI EXPRESS XMTR PWR

CORE / PLATFORM

BVDD

GIGABIT ETHERNET

LOCAL BUS



Fan-Out Schematics

Figure 26. Ground and No-Connect

GND76GND74GND72GND70GND68GND66GND64GND62

GND58GND56GND54GND52GND50GND48GND46

GND38GND36GND34GND32GND30GND28GND27GND25GND23

GND19GND17GND15

GND10GND8GND6GND80GND4GND3GND2GND1GND5GND7GND9GND12GND14GND16GND18GND20

GND24GND26GND29GND31GND33GND35GND37GND39GND41GND43GND45GND47GND49

AH9AF14AE23AD7

AC16AC21

U6U17U13T16R17R13P16P5

N17N13M16L15K8

L26J27F27J15C20G25A14C6

G15H1L1

E15F16F8

J14B10E20C12B28D26

F4M10

D5D23C15D8E3

K21A3

E12D17F21G13G18

A7H4

J12J17M5

K11K7

L12M14M18N15

GND21

GND13

GND42

GND60

GND44

GND22

GND40

GND78

GND51GND53GND55GND57GND59GND61GND63GND65GND67

N2P14P18R15T14T18U15AA8Y10

GND69GND71GND73GND75GND77

V4AD18AF11AG23

AA17

GND79GND81

C27A27

SGND_SRDS17

M28N26P24P27R25T28U24U26V24W25Y28AA24AA26AB24AB27AC24AD28

SGND_SRDS1

M20M24N22P21R23T21U22V20W23Y21

Y4AA4AA22AD4AE4AH4

SGND_SRDS2_13AH2AF3AE25AE1AE3AD24AD3AC25AC3AC2AB3AA1Y2

MPC8544GROUND9 OF 10

SGND_SRDS2SGND_SRDS3SGND_SRDS4SGND_SRDS5SGND_SRDS6SGND_SRDS7SGND_SRDS8SGND_SRDS9

SGND_SRDS10SGND_SRDS11SGND_SRDS12SGND_SRDS13SGND_SRDS14SGND_SRDS15SGND_SRDS16

XGND_SRDS1

XGND_SRDS10

XGND_SRDS2XGND_SRDS3XGND_SRDS4XGND_SRDS5XGND_SRDS6XGND_SRDS7XGND_SRDS8XGND_SRDS9

XGND_SRDS2_1

XGND_SRDS2_6

XGND_SRDS2_2XGND_SRDS2_3XGND_SRDS2_4XGND_SRDS2_5

SGND_SRDS2_1

SGND_SRDS2_12SGND_SRDS2_11SGND_SRDS2_10SGND_SRDS2_9SGND_SRDS2_8SGND_SRDS2_7SGND_SRDS2_6SGND_SRDS2_5SGND_SRDS2_4SGND_SRDS2_3SGND_SRDS2_2

NC2NC3NC4NC5

NC7NC8NC9

NC11NC12NC13NC14NC15NC16NC17

NC21NC22NC23

NC25NC26

C19D7

D10K13

L6

K9B6

F12J7

M19M25N19N24P19R19

AB19T12W3

M12W5P12T19

W1W7

NC19

NC10

NC18

NC20

NC1

MPC8544NO CONNECT

10 OF 10

NC63NC61NC59NC57NC55NC27NC28NC29

NC31NC32NC33NC34NC35NC36NC37

NC41NC42NC43NC44NC45NC46NC47NC48NC49

NC51NC52NC53

NC56NC58NC60NC62NC64NC66

AB23AB21AA19Y19Y17W27L13U19W4V8V9V10V11V12V13V14V15V16V17V18V19W2W6W8T11U11W12W13W14W15W16W17W18W19V25Y18AA18AB20AB22J9

NC50

NC54

NC39

NC30

NC38

NC40

NC65



Fan-Out Schematics

Figure 27. Memory Connector 1

MPC8544

DQ0

DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12

DQ14DQ15DQ16

DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQ32DQ33

DQ35DQ36DQ37DQ38DQ39DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47

2837849310511446

349101221231281291213212213113214014124253031143144149150333439401521531581598081868719920020520689909596208209214215

DQ13

DQ17

DQ2DQ1

DQ34

DQ3

DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQ56

9899107108217218226227110

DQ57DQ58DQ59DQ60DQ61

116117229230

111

DQ62DQ63

236235

DQS8DQS7DQS6DQS5DQS4DQS3DQS2

716

DQS1DQS0

0

456789

101112

141516

18192021222324252627282930313233

35363738394041424344454647

13

17

21

34

3

48495051525354555657585960616263

MDQ[0:63]1B2 10B6

01234

MWEWE

7310C3 1D6

CB0 (ECC0)CB1 (ECC1)

CB3 (ECC3)CB4 (ECC4)CB5 (ECC5)CB6 (ECC6)CB7 (ECC7)

42434849

161162167168

CB2 (ECC2)

01

34567

2

MECC[0:7]10A3 1B6

DM0 (DQS9)DM1 (DQS10)

DM3 (DQS12)DM4 (DQS13)DM5 (DQS14)DM6 (DQS15)DM7 (DQS16

125134146155202211223232

DM2 (DQS11)

01

34567

2

MDM[0:8]10A3 1C6

DM8 (DQS17)1648

BA0BA1

7119054

BA2

012

MBA[0:2]10B3 1C6

A0A1

A3A4A5A6A7

18818363

1826160

18058

A2

01

34567

2

MA[0:15]10B3 1C6

A81798

A10A11A12A13A14

1777057

176196174

A91011121314

9

A1517315

(AP)

MRAS RAS19210C3 1D6

MCAS CAS74

10C3 1D6

MCS0 S0193

1D6MCS1 S1

761D6

MODT0ODT0

1951D6

MODT1 ODT1771D6

MCKE0CKE0

521D6

MCKE1CKE1

1711D6

MCK0CK_H0

1851A2

MCK0 CK_L0186

1A2MCK1 CK_H1

1371A2

MCK1 CK_L1138

1A2MCK2 CK_H2

2201A2

MCK2 CK_L2221

1A2

MVREF VREF110D3 1A7

MAPAR_INRC

556D2 10D3

I2C_SDASDA

11910D3

I2C_SCLSCL120

10D3

MAPAR_OUTPWR1_SEL_OPT1

6810D3 6D2

CONN_240_DDR2_VERT_

SPECIAL_1OF2P1

DDR2 DIMM

NC1NC2NC3

NC5NC6NC7NC8NC9

VDD1VDD2

VDD6VDD7VDD8

VDD10

NC10

102126135147156165203212224

5359646769

172178184

189

233

VDD4

NC4

VDD3

VDD5

MPC8544CONN_240_

DDR2_VERT_

VDDQ11

515662727578170175181191194

VDDQ1

VDD9187

PWR1_SEL_OPT250

PWR2_SEL_OPT266

VDD11197

VDDQ2VDDQ3VDDQ4VDDQ5VDDQ6VDDQ7VDDQ8VDDQ9VDDQ0

SPECIAL_1OF2P2

19PWR2_SEL_OPT1 NORMALLY

NC ONDDR2

18RESET

239240101238

SA0SA1SA2VDDSPD

MDQS[0:8]1A6 10A6

GVDD

GVDD

NC102

126, 135, 147,156, 165, 203,212, 224, 233

NOTSUPPORTED

2, 5, 8, 11,14, 17, 20, 23,26, 29, 32, 35,38, 41, 44, 47,65, 79, 82, 85,88, 91, 94, 97,100, 103, 106,109, 112, 115,118, 121, 124,127, 130, 133,136, 139, 142,145, 148, 151,154, 157, 160,163, 166, 169,198, 201, 204,207, 210, 213,216, 219, 222,225, 228, 231,

234, 237

GROUND

5678

2736839210411345

DQS8nDQS7nDQS6nDQS5nDQS4nDQS3nDQS2n

615

DQS1nDQS0n

01234

MDQS[0:8]1B6 10A6

5678



Fan-Out Schematics

Figure 28. Memory Connector 2

2837849310511446

DQS8DQS7DQS6DQS5DQS4DQS3DQS2

716

DQS1DQS0

01234

NC1NC2NC3

NC5NC6NC7NC8NC9

VDD1VDD2

VDD6VDD7VDD8

VDD10

NC10

102126135147156165203212224

5359646769

172178184

189

233

VDD4

NC4

VDD3

VDD5

MPC8544CONN_240_

DDR2_VERT_

VDDQ11

515662727578170175181191194

VDDQ1

VDD9187

PWR1_SEL_OPT250

PWR2_SEL_OPT266

VDD11197

VDDQ2VDDQ3VDDQ4VDDQ5VDDQ6VDDQ7VDDQ8VDDQ9VDDQ0

SPECIAL_1OF2P2

MDQS[0:8]1A6 10A6

GVDD

GVDD

2, 5, 8, 11,14, 17, 20, 23,26, 29, 32, 35,38, 41, 44, 47,65, 79, 82, 85,88, 91, 94, 97,100, 103, 106,109, 112, 115,118, 121, 124,127, 130, 133,136, 139, 142,145, 148, 151,154, 157, 160,163, 166, 169,198, 201, 204,207, 210, 213,216, 219, 222,225, 228, 231,

234, 237

GROUND

5678

2736839210411345

DQS8nDQS7nDQS6nDQS5nDQS4nDQS3nDQS2n

615

DQS1nDQS0n

01234

MDQS[0:8]1B6 10A6

5678

MPC8544

DQ0

DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12

DQ14DQ15DQ16

DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQ32DQ33

DQ35DQ36DQ37DQ38DQ39DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47

349101221231281291213212213113214014124253031143144149150333439401521531581598081868719920020520689909596208209214215

DQ13

DQ17

DQ2DQ1

DQ34

DQ3

DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQ56

9899107108217218226227110

DQ57DQ58DQ59DQ60DQ61

116117229230

111

DQ62DQ63

236235

0

456789

101112

141516

18192021222324252627282930313233

35363738394041424344454647

13

17

21

34

3

48495051525354555657585960616263

MDQ[0:63]1B2 10B6

MWEWE

7310C3 1D6

CB0 (ECC0)CB1 (ECC1)

CB3 (ECC3)CB4 (ECC4)CB5 (ECC5)CB6 (ECC6)CB7 (ECC7)

42434849

161162167168

CB2 (ECC2)

01

34567

2

MECC[0:7]10A3 1B6

DM0 (DQS9)DM1 (DQS10)

DM3 (DQS12)DM4 (DQS13)DM5 (DQS14)DM6 (DQS15)DM7 (DQS16

125134146155202211223232

DM2 (DQS11)

01

34567

2

MDM[0:8]10A3 1C6

DM8 (DQS17)1648

BA0BA1

7119054

BA2

012

MBA[0:2]10B3 1C6

A0A1

A3A4A5A6A7

18818363

1826160

18058

A2

01

34567

2

MA[0:15]10B3 1C6

A81798

A10A11A12A13A14

1777057

176196174

A91011121314

9

A1517315

(AP)

MRAS RAS19210C3 1D6

MCAS CAS74

10C3 1D6

MCS2 S2193

1D6MCS3 S3

761D6

MODT2ODT2

1951D6

MODT3 ODT3771D6

MCKE2CKE2

521D6

MCKE3CKE3

1711D6

MCK3CK_H3

1851A2

MCK3 CK_L3186

1A2MCK4 CK_H4

1371A2

MCK4 CK_L4138

1A2MCK5 CK_H5

2201A2

MCK5 CK_L5221

1A2

MVREF VREF110D3 1A7

MAPAR_INRC

556D2 10D3

I2C_SDASDA

11910D3

I2C_SCLSCL120

10D3

MAPAR_OUTPWR1_SEL_OPT1

6810D3 6D2

CONN_240_DDR2_VERT_

SPECIAL_1OF2P1

DDR2 DIMM

19PWR2_SEL_OPT1 NORMALLY

NC ONDDR2

18RESET

239240101238

SA0SA1SA2VDDSPD

NC102

126, 135, 147,156, 165, 203,212, 224, 233

NOTSUPPORTED



Fan-Out Schematics

Figure 29. PCI Express Connector




MPC8544PCIEXPRESS_CONN_X16

PETN6PETP6

PETN5PETP5

PETN7B46B45

B42B41

B38B37

2B72B7

2B72B7

2B72B7

PETP7




PETN3PETP3

PETN2PETP2

PETN4B34B33

B28B27

B24B23

2B72B7

2B72B7

2B72B7

PETP4

X4 LANE

X4 LANE

A13A14

A11B10

B5B6

B11

B79B78

B75B74

B71B70

B67B66

B63B62

B59B58

B55B54

B51B50

REFCLKPREFCLKN

PERSTP3.3V_AUX

SMCLKSMDAT

WAKE_N

PETN15PETP15

PETN14PETP14

PETN13PETP13

PETN12PETP12

PETN11PETP11

PETN10PETP10

PETN9PETP9

PETN8PETP8

PERN14PERP14

PERN13PERP13

PERN12PERP12

PERN11PERP11

PERN10PERP10

PERN9PERP9

PERN8PERP8

PRSNT1PRSNT2_1

PRSNT2_3PRSNT2_4

TDOTCK

TRST*

PERN15PERP15

A1B17

B48B81

A7A5

B9

A81A80

A77A76

A73A72

A69A68

A65A64

A61A60

A57A56

A53A52

A8

A6

B31PRSNT2_2

TDI

TMS

PEX3_TX0_NPEX3_TX0_P2C7

2C7

PEX3_RX0_NPEX3_RX0_P 2C2

2C2

SD_REF1_CLK_PSD_REF1_CLK_N



PETN1PETP1

PETN0PETP0

B20B19

B15B14

2B72B7

2B72A7

X1 LANE

PEX2_RX2_NPEX2_RX2_P



PERN6PERP6

PERN5PERP5

PERN7 A48A47

A44A43

A40A39

2B22B2

2B22B2

2B22B2

PERP7




PERN3PERP3

PERN2PERP2

PERN4 A36A35

A30A29

A26A25

2B22B2

2B22B2

2B22B2

PERP4

X4 LANE

X4 LANE



PERN1PERP1

PERN0PERP0

A22A21

A17A16

2B22B2

2B22A2

X1 LANE

B4, A4, B7,A12, B13, A15,B16, B18, A18,A20, B21, B22,A23, A24, B25,B26, A27, A28,B29, A31, B32,A34, B35, B36,A37, A38, B39,B40, A41, A42,B43, B44, A45,A46, B47, B49,A49, A51, B52,B53, A54, A55,B56, B57, A58,A59, B60, B61,A62, A63, B64,B65, A66, A67,B68, B69, A70,

GND

B8, A9, A10

+12VB1, B2, B3,

A2, A3

+3.3V

NCB3, B12, B30,A32, A33, A50,

B82, A19

A71, B72, B73,A74, A75, B76,B77, A78, A79,

B80, A82

J1



Fan-Out Schematics

Figure 30. PCI 32-Bit Connector

MPC8544PCICONN_3V_32BIT_BLOCK

B16A15

A34B37

A36A38

B40B42

A40A41B49

A60B60

A26

CLKRST

FRAMEDEVSEL

TRDYSTOP

PERRSERR

SDONESBOM66EN

REQ64ACK64

IDSEL

NC1

PRSNT1PRSNT2

TDITDO

TMSTRST*

B9B11

A4B4

A3A1

A9

B2TCK

DUT_PCI32_PERR*DUT_PCI32_SERR*

A12, A13, B12,B13, A18, A24,A30, A35, A37,A42, A48, A56,B3, B15, B17,B22, B28, B34,B38, B46, B57

GND

A21, A27, A33,

+12VA2

+3.3V

NCA9, A11, A14,A19, B10, B14

J5

DUT_PCI32_TRDY*DUT_PCI32_STOP*

DUT_PCI32_FRAME*DUT_PCI32_DEVSEL*

B35DUT_PCI32_IRDY*IRDY

A17B18

GNTREQ

PCI32_SLOT_GNT*PCI32_SLOT_REQ*

AD31B20A20B21A22B23A23B24A25B27A28B29A29B30A31B32A32

31302928272625242322212019181716

A44B45A46B47A47B48A49B52B53A54B55A55B56A57B58A58

1514131211109876543210

AD30AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0

DUT_PCI32_AD[31:0]3C3

3C53C5

3B53B5

3B53B53B53B53B5

B39LOCK

INTA

INTCINTD

A6

A7B8

B7INTB

NC3

NC5NC6

A14

B10B14

A19NC4

NC2A11

B26B33B44A52

3210

C_BE3C_BE2C_BE1C_BE0

A43PAR

DUT_PCI32_PAR3B5

DUT_PCI32_C_BEX[3:0]3B5

VIO: 3.3V OR 5V

A10

A59A16

B19B59

VCC_3.3

A39, A45, A53,B25, B31, B36,B41, B43, B54

+5VA5, A8, A61,A62, B5, B6,

B61, B62

5V: 145154_13V: 145154_1



Fan-Out Schematics

Figure 31. Local Bus Latches

MPC8544U507

1Q11Q2

1Q41Q5

1Q71Q8

A6B6

D6E6

G6H6

F6

C61Q3

1Q6

B3, B4,D3, D4,E3, E4,G3, G4,K3, K4,M3, M4,N3, N4,R3, R4

GND

74ALVCH32973KR_LFBGA96

1B11B2

1B41B5

1B71B8

A5B5

D5E5

G5H5

F5

C51B3

1B6

2Q12Q2

2Q42Q5

2Q72Q8

J6K6

M6N6

R6T6

P6

L62Q3

2Q6

2B12B2

2B42B5

2B72B8

J5K5

M5N5

R5T5

P5

L52B3

2B6

Y1Y2

Y4Y5

Y7Y8

B2D2

H2K2

P2T2

M2

F2Y3

Y6

1A11A2

1A41A5

1A71A8

A1B1

D1E1

G1H1

F1

C11A3

1A6

D1D2

D4D5

D7D8

A2C2

G2J2

N2R2

L2

E2D3

D6

2A12A2

2A42A5

2A72A8

J1K1

M1N1

R1T1

P1

L12A3

2A6

1LE

1TOEA3A4

H41LOE

1DIR

H3

2LE

2TOEJ3J4

T42LOE

2DIR

T3

LA[27:31]4D1

LALE4C5

LBCTL4C5

LAD[0:31]4B1

76

43

10

2

5

1514

1211

98

10

13

MPC8544U508

1Q11Q2

1Q41Q5

1Q71Q8

A6B6

D6E6

G6H6

F6

C61Q3

1Q6

B3, B4,D3, D4,E3, E4,G3, G4,K3, K4,M3, M4,N3, N4,R3, R4

GND

74ALVCH32973KR_LFBGA96

1B11B2

1B41B5

1B71B8

A5B5

D5E5

G5H5

F5

C51B3

1B6

2Q12Q2

2Q42Q5

2Q72Q8

J6K6

M6N6

R6T6

P6

L62Q3

2Q6

2B12B2

2B42B5

2B72B8

J5K5

M5N5

R5T5

P5

L52B3

2B6

Y1Y2

Y4Y5

Y7Y8

B2D2

H2K2

P2T2

M2

F2Y3

Y6

1A11A2

1A41A5

1A71A8

A1B1

D1E1

G1H1

F1

C11A3

1A6

D1D2

D4D5

D7D8

A2C2

G2J2

N2R2

L2

E2D3

D6

2A12A2

2A42A5

2A72A8

J1K1

M1N1

R1T1

P1

L12A3

2A6

1LE

1TOEA3A4

H41LOE

1DIR

H3

2LE

2TOEJ3J4

T42LOE

2DIR

T3

2322

2019

1716

18

21

3130

2827

2524

26

29

3130

2827

29

LOCAL BUSLATCHES

LOCAL BUSLATCHES

PWR PINSSEE MAP FOR

PWR PINSSEE MAP FOR



Fan-Out Schematics

Figure 32. GBE PHYs

TXD3_1

TXD1_1TXD0_1

T13

U14T14

V14TXD2_1

3

10

2

TDOTMSTCK

TRST*

CLK125MACCLK125MICRO

REF_FILT

VSS1

J16K16K18K17L16

R17M18

C9

C10

C11C12C13C14D7D8F2G4G7G8G9G10G11G12H7H8H9H10H11H12J7J8J9J10J11J12K2K3K4K7K8K9K10K11K12L3L7L8L9

REF_REXT

TDI

MPC8544U6

VSC8244_3of3_SYS_PWR_PBGA260

VSC8244HG1 OF 3

VSS48

L10L11L12M4N4N15P2P3P15

VSS47VSS46VSS45VSS44VSS43VSS42VSS41VSS40VSS39VSS38VSS37VSS36VSS35VSS34VSS33VSS32VSS31VSS30VSS29VSS28VSS27VSS26VSS25VSS24VSS23VSS22VSS21VSS20VSS19VSS18VSS17VSS16VSS15VSS14VSS13VSS12VSS11VSS10VSS9VSS8VSS7VSS6VSS5VSS4VSS3VSS2

VSSIO7

M7M8M9M10M11M12M15

VSSIO6VSSIO5VSSIO4VSSIO3VSSIO2VSSIO1

MDIO

MDINT0MDINT1

MDINT3

XTAL1

P16P17

P18N16

N18

L17L18

D17D18

M16M17

D14D15

E4F4H3J3

M3N3R3

H4H15

J4J15P4R4

R14R15

R5R6R7R9

R11R12

C8D4D5D6D9

D10D11D12D13

EEDAT

MDC

F15G15

L4R16

VDD33_13VDD33_12VDD33_11VDD33_10VDD33_9VDD33_8VDD33_7VDD33_6VDD33_5VDD33_4VDD33_3VDD33_2VDD33_1

VDDIO_MAC6VDDIO_MAC5VDDIO_MAC4VDDIO_MAC3VDDIO_MAC2VDDIO_MAC1

VDDDIG8VDDDIG7VDDDIG6VDDDIG5VDDDIG4VDDDIG3VDDDIG2VDDDIG1

VDD12_9VDD12_8VDD12_7VDD12_6VDD12_5VDD12_4VDD12_3VDD12_2VDD12_1

SOFT_RESETRESET

VDD_MICRO

K15L15

VDD_CTL

MDINT2N17

EECLK

XTAL2

SEE SPECNC

TSEC1TSEC1TSEC1TSEC1

MPC8544U6

VSC8244_1of3_PORTS_PBGA260

VSC8244HG3 OF 3

MPC8544U6

VSC8244_2of3_MACS_PBGA260

VSC8244HG2 OF 3

MDC5C3

MDIO5C3

TXD3_0T17TSEC3_TXD3

5B6V18TSEC3_TXD2

5B6U18TSEC3_TXD1

5B6T18

5B6

TXD2_0TXD1_0TXD0_0

TSEC3_TXD0

T11GMAC1_RX_CLK5C3

U115C3

RX_CLK1RX_CTL1

GMAC1_RX_DVTSEC1TSEC1

TX_CTL0U17TSEC3_TX_EN

5B6V17TSEC3_GTX_CLK

5B6 TX_CLK0

B1C1C2C6C7

C15NC6NC5NC4NC3NC2NC1

RXD3_0T15TSEC3_RXD3

5C6V16TSEC3_RXD2

5C6U16TSEC3_RXD1

5C6T16

5C6

RXD2_0RXD1_0RXD0_0

TSEC3_RXD0

RX_CLK0V15TSEC3_RX_CLK

5C6U15TSEC3_RX_DV

5C6 RX_CTL0

D2D1E1E2

E15NC11NC10NC9NC8NC7

V13TSEC1_TX_EN5B2

U135B2

TX_CTL1TX_CLK1

TSEC1_GTX_CLKTSEC1TSEC1

RXD3_1

RXD1_1RXD0_1

V11

U12T12

V12RXD2_1

GMAC1_RXD[3:0]5B1

3

10

2TSEC1TSEC1TSEC1TSEC1

G1F1G2H1H2

NC16NC15NC14NC13NC12

TXD3_3

TXD1_3TXD0_3

V5

U6V6

T6TXD2_3

TXD3_2V9T10U10V10

TXD2_2TXD1_2TXD0_2

V2U3

RX_CLK3RX_CTL3

TX_CTL2U9T9

TX_CLK2

J1J2K1L1L2M1

NC22NC21NC20NC19NC18NC17

RXD3_2V7T8U8V8

RXD2_2RXD1_2RXD0_2

RX_CLK2T7U7

RX_CTL2

M2N1N2P1R1


U5T5

TX_CTL3TX_CLK3

RXD3_3

RXD1_3RXD0_3

V3

U4V4

T4RXD2_3

T1T2U1U2V1


R2NC29

A18B18A17B17A16B16A15B15

TXVND_0TXVPD_0TXVNC_0TXVPC_0TXVNB_0TXVPB_0TXVNA_0TXVPA_0

J18J17H18H17H16

LED0_0LED1_0LED2_0LED3_0LED4_0

A14B14A13B13A12B12A11B11


G18G17G16F18F17


F16E18E17E16D16C18C17C16

CMODE7CMODE6CMODE5CMODE4CMODE3CMODE2CMODE1CMODE0

A10B10A9B9A8B8A7B7


C5C4C3B2A2


A6B6A5B5A4B4A3B3


A1D3E3F3G3


R13R10R8T3

R18MICRO_REF

TXREF3TXREF2TXREF1TXREF0

1 3

0 2

GMAC1_TXD[3:0]5B1



Current Delivery in the BGA Field

10 Current Delivery in the BGA FieldThe MPC8544E comes in a 1 mm pitch, 783 BGA package arranged as a 28 × 28 array (with pin A1 missing). The BGA pads and vias usually have the physical parameters listed Table 9.

Keep the following points in mind while reading this section:

• The remainder of this section is based on the padstack dimensions in Table 9. If a different padstack is used, most or all of the numbers derived probably need to be recalculated.

• It is assumed that each BGA connection carries current equally, no matter its proximity to the power supply and/or processor internal power pads. In reality, the current is non-uniformly distributed due to internal BGA-to-die substrate connections and other factors. There are no guaranteeable distributions among the power pins.

All comments in this section about power planes apply equally to the return ground. Multilayer PCBs often have multiple ground planes, so this restriction is occasionally overlooked; however, the ground return path requirements are exactly equal to the power source path requirements.

In addition to bypass capacitor placement, the designer must also consider the wholesale delivery of power to the VDD pins. On most PCBs, the power plane is not actually solid, but is perforated by numerous vias. This is illustrated in Figure 33, where the wide plane is actually only as wide as its narrowest point.

Figure 33. Restricted Current Flow

Table 9. MPC8544E Escape Dimensions

Dimension Size Notes

Drill diameter 10 mils Via drill

Finished hole size (FHS) 7–7.5 mils After plating

Pad 19 mils

Anti-pad 28 mils Clearance from via pads to adjacent plane area-fills

Thermal relief 33 mils2

Via keepout 23 mils As above, but for traces on signal (inner) planes

W=7 Units

W=3 * 1U

PSU

CPU

Power Plane Area-Fill

Effective Width =




For many applications, the effect of the vias passing through the power plane on the flow of current is insignificant. However, as the power reaches the outer periphery of the MPC8544E, it must flow through the outer array of signal BGA vias. While some BGA pads may not need vias (outer BGA pads may be able to route out on the top layers); in most cases the number of interfering vias ranges from 8 to 11.

For many layouts, the outer one or two BGA pads do not require vias as these signals are usually “escaped” on the top layer of the PCB. Delivering power properly to the power pins requires planning the flow of current around these vias, or more properly, the antivias or antipads that surround the via and cause a hole on the power plane layer. When coupled with a 1-mm spacing, the cross section of the PCB typically resembles that shown in Figure 6.

The anti-pad is larger than the spacing between the via barrels, which in effect reduces the width and capacity of the trace. In effect, the power plane is not a solid plane but a parallel array of traces with one of the following widths:

• 11.3 mils, when planes must be isolated from both vias

• 19.3 mils, when planes connect to one of the vias

The standard formulae to determine the limits of the copper trace are described in the IPC-2221A standard and are given by:

Eqn. 1

Eqn. 2

Using these formulae, and using an 11-mil trace as a standard (rounded down from the actual 11.3-mil max trace width), for various layout rules the amount of current that can be safely carried, assuming a maximum temperature rise of 20°C, is shown in Table 10.

10.1 Via Current CapacityUnless the power is delivered on the top plane and attaches directly to the BGA pad of the processor (which as noted is fairly difficult to accomplish), power is delivered from one or more PCB planes to the processor through vias. Given the padstack parameters in Table 9 and the number of vias allocated, the next step to

Table 10. Current-Carrying Capacity per Standard IPC2221A

Location Copper Plating(oz.)

11-mil Trace(A)

Outer 0.5 0.777

1.0 1.285

1.5 1.730

2.0 2.130

Inner 0.5 0.390

1.0 0.582

1.5 0.865

2.0 1.065

Trace, Outer) 0.048 maxTempRise( )0.44× viaPlating viaDiameter π××( )0.7×=

Trace, Inner) 0.024 maxTempRise( )0.44× viaPlating viaDiameter π×¥( )0.7×=




ensure a quality PDS is to evaluate the individual and aggregate via current capacity using the following formula:

Eqn. 3

Table 11 shows a few via current capacities for given PCB process parameters.

At 1.609 A/via, we have a maximum current capacity of 22.5 A for VDD_CORE (14 vias * 1.609), and 16 A for VDD_PLAT (10 * 1.609).

10.2 Alternate Plane Current CapacityResearch performed by Johannes Adam of Flomerics as preparatory work for a revision to one of the rules of the IPC2221 standard (specifically, design rule 2152), found that the formula for outer traces was based on materials and assumptions no longer prevalent. Additionally, he discovered that the 50-percent derating factor used for inner traces is wholly arbitrary and should be approximately 5 percent. In particular, thermal conduction to adjacent traces and power planes was found to be vastly more important than conduction to free space. Refer to Section 1, “References,” for details on this paper and associated historical data.

At the time of publication, the IPC2221 has not been updated based on these findings, so the designer can either follow the published standards and accept overly conservative numbers or incorporate the pending changes. Freescale cannot recommend one course over the other and advises designers to consult the original source documentation and decide for themselves. In New Correlations Between Electrical Current and Temperature Rise in PCB Traces, an examination of “Case 5” shows an outer trace of variable width over a 35-μm (1-oz. copper) plane (see Section 1, “References”). This correlates nicely with an external power connection residing over an inner ground plane immediately adjacent to it. Such a plane is desirable not only for power purposes but for routing differential pairs such as those on the SerDes or DDR interfaces. Extracting the data for a 0.3-mm trace (~11 mils) and applying a curve fitting process to the data produces the following formula, represented in Figure 34:

Eqn. 4

Table 11. Via Capacity

maxTempRise(°C)

viaPlating(mil)

viaDiameter(mil)

IVIA(A) Notes

10 1 10 1.609 Standard

10 1 11 1.724 —

10 1 15 2.159 —

10 1.5 10 2.159 —

20 1 10 2.183 —

VIA 0.048 maxTempRise( )0.44× viaPlating viaDiameter π××( )0.72×=

T trace( ) 19.473 3.228IMAX 4.469IMAX2 0.385IMAX3+ + +=




Figure 34. Extrapolated Current Flow

CAUTIONThis curve is valid only for the 0.3 mm trace. The IPC standard will likely include a more complicated curve equation that accepts both current and trace width as a parameter.

Note that the Y-axis is the total trace temperature. Because we are concerned with a maximum 20°C rise, the Y-axis starts at 20 as the ambient temperature is also assumed to be 20°C. The crossover point of 40°C occurs when I = 1.711 A. Using this new data, Table 10 can be updated as shown in Table 12:

Table 12. Current-Carrying Capacity Extrapolated from Adams


(oz.)A/11-mil Trace

(A)

Outer 0.5 1.210

1.0 1.711

1.5 2.420

2.0 3.422

0

10

20

30

40

50

60

70

80

90

0 0.5 1 1.5 2 2.5 3 3.5

Current, A

Tra

ce T

emp

, deg

C

0.3 mm (ADAMS)

0.3 mm (curve fit)



Revision History

New Correlations Between Electrical Current and Temperature Rise in PCB Traces explains why the classic IPC-275/IPC2221A values for inner current layers are extremely misleading. IPC-2152 is not published at the time of this application note.

11 Revision HistoryTable 13 provides a revision history for this application note.

Inner 0.5 1.149

1.0 1.625

1.5 2.299

2.0 3.251

Table 13. Document Revision History

Rev.Number

Date Description

0 01/08 Initial release.

Table 12. Current-Carrying Capacity Extrapolated from Adams (continued)


(oz.)A/11-mil Trace

(A)

Document Number: AN3535Rev. 02/2008

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