Christopher R. Anderson 1

AbstractSoftware Defined Radios (SDR) have the potential

of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited by the speed of the underlying ADCs, DSPs, and FPGAs. A SDR receiver provides tremendous flexibility and rapid prototyping capabilities over a fixed hardware implementation. Such a receiver has the capability of supporting multiple data rates, modulation or multiple access schemes, can adapt to the propagation environment, and is capable of operating with a variety of waveforms and communication standards. Currently, state-of-the-art Impulse Ultra Wideband (UWB) communication systems are composed of custom-developed hardware, and do not use SDR architectures. Several major challenges are involved in developing such a communication system—such systems require extremely high sampling rates, generate huge amounts of sample data, and require a tremendous amount of digital processing power. These challenges are particularly daunting when Commercially available Off-The-Shelf (COTS) components are used in the development of such a system. In this paper, we investigate the development of a UWB SDR Transceiver Testbed based around an 8 GHz-8 ADC Time Interleaved Sampling array. The overall objective is to develop a testbed that will allow researchers to evaluate different UWB modulation, multiple access, and coding schemes, and will support raw data rates of up to 100 MB/s.

1. IntroductionUltra wideband (UWB) communication systems

can be broadly classified as any communication system whose instantaneous bandwidth is many times greater than the minimum required to deliver a particular

information data rate, and is the defining characteristic of UWB systems. UWB has three primary features, which differentiate it from conventional narrowband systems [1]:1. Large instantaneous bandwidth enables fine time

resolution for use as a radar, for imaging, or for precision location capability.

2. Short-duration pulses prevent signal fading (fluctuations in the received signal power) in very harsh communication environments.

3. Low transmitter power and very wide bandwidths allows coexistence with existing users and provides Low Probability of Intercept (LPI).

A Software Defined Radio UWB receiver provides tremendous flexibility and rapid prototyping capabilities over a fixed hardware implementation [2]. Such a receiver has the capability of supporting multiple data rates, modulation or multiple access schemes, and can adapt to the propagation environment. Currently, state-of-the-art UWB communication systems are composed of custom-developed hardware, and do not use SDR architectures. The challenges involved in developing such as communication testbed—extremely high sampling rates, huge amounts of input/output data, and a tremendous amount of digital processing power—have been fairly daunting. These challenges become particularly poignant when Commercially available Off-The-Shelf (COTS) components are used in the development of such a system.

This paper presents an overview of a Software Defined UWB Communication System Testbed. The testbed was designed to operate at a data rate of 100 Mbps, to utilize any of the two popular UWB modulation schemes (Pulse Position or Pulse Amplitude), and to

A SOFTWARE DEFINED ULTRA WIDEBAND COMMUNICATION SYSTEM

TESTBED

Christopher R. Anderson and Jeffrey H. Reed

2Mobile and Portable Radio Research GroupBradley Department of Electrical and Computer Engineering

Virginia Polytechnic Institute and State UniversityBlacksburg, VA 24061

chanders@vt.edu

Christopher R. Anderson 2

The SDR pulse generator circuit (shown in Figure 2), is based on the circuit presented in [3]. The circuit operates by taking the step waveform generated by the diode and dividing it along two transmission lines into a forward- and reverse-traveling pulse. The step pulse which travels in the reverse direction along the transmission line shorted to ground will be inverted and reflected back toward the forward-traveling pulse. At the end of the forward transmission line, the two step pulses will be combined to form a short-duration impulse. Because the Analog-to-Digital Converters (ADCs) on the receiver have an input bandwidth of 2.2 GHz, and because the bandwidth of a UWB pulse is approximately equal to the inverse of its time duration, the time duration of the SRD generated pulse was set at 500 picoseconds. A simulated output signal from the SRD pulse generator is shown in Figure 3.

The transmitter was designed to support three distinct UWB modulation schemes:1. Pulse Amplitude Modulation (PAM) [1]. 2-ary PAM

can be generated by triggering the positive SRD pulser to transmit a “1” and the negative SRD pulser to transmit a “0”. Because the SRD pulsers create a pulse with a fixed amplitude, this modulation scheme is limited to transmitting only one data bit per UWB symbol.

2. Pulse Position Modulation (PPM) [1]. M-ary PPM can be generated by triggering one of the SRD pulsers at non-regular instances in time. The dime difference between successive pulses thus determines which bit/symbol was transmitted. Because the data symbol is contained in the timing of the UWB pulse–which is under full control of the user–it is possible to transmit multiple data bits per UWB symbol.

3. Combination PAM/PPM. PAM and PPM can be combined to transmit multiple data bits per UWB pulse. For example, by applying 2-PPM to both the positive and negative SRD pulsers, two data bits can be transmitted per UWB symbol.

The outputs of the SRD pulse generators are combined via a filtering/combining circuit. The circuit is composed of a 3dB resistive attenuator at the output of each pulse generator circuit, a power combiner, and a low pass filter. The purpose of the filtering/combining circuit is to combine the outputs of the positive and negative pulse generator circuits and output them to a single antenna. Additionally, the combining circuit isolates the two pulse generator circuits, in order to ensure that the output from one pulse generator does not wreak havoc with the operation of the other pulse generator.

support a variety of multiple access or coding schemes. Additionally, due to the SDR architecture of the system, a simple software change would allow the testbed to operate with any number of other broadband waveforms, such as Wireless LAN, Bluetooth, Cellular Radio, etc.

The UWB SDR Transceiver was designed to meet a number of performance and flexibility objectives, as listed below:

Performance• Data Rate: Raw data rate of 100 Mbits/sec, assuming

one UWB symbol per data bit.

• RF Bandwidth: DC to 2.2 GHz, which utilizes the full analog input bandwidth of the ADCs.

• Sampling Frequency: Effective Sampling Frequency of 8 GS/s, using eight 1 GS/s ADCs in a Time Interleaved Array.

• Receiver Dynamic Range: 40dB, corresponding to 7 ENOB (Effective Number Of Bits of quantization) for the ADC.

Flexibility• Waveform Agnostic Receiver: Capable of handling

other types of broadband signals (DSSS, OFDM, etc.).

• Fully Digital Receiver: All receiver functions (downconversion, filtering, demodulation, etc.) implemented inside the FPGA.

• Customizable Air Interface: Full control over frame/packet structure, channel/error control coding, as well as pulse shaping.

To meet these objectives, the transceiver is partitioned into three primary subsystems: the Transmitter Board, the RF Front End, and the Receiver. Each of these subsystems will be discussed in greater detail in Sections 2-4. Section 5 will present initial performance results from a prototype version of the transceiver. Finally, Section 6 summarizes the results in this paper and presents conclusions.

2. Transmitter BoardA block diagram of the Transmitter Board is given

in Figure 1. The transmitter generates UWB pulses via a Step Recovery Diode (SRD) pulse generator circuit [3]. The SRD operates almoste exactly like a normal diode, but features a fast switching characteristic. When the forward biased SRD is suddenly reverse biased, current will continue to flow in the forward direction as long as recombination takes place. When the stored charge carriers are depleted, the diode immediately switches off to a high impedance state, a transition which occurs in around 100 picoseconds.

Christopher R. Anderson 3

3. RF Front EndIn keeping with the design objective to produce an

extremely flexible, general-purpose transceiver, the RF front end consists of only the most basic elements: a transmitter/receiver switch, low noise amplifiers and filters, and a digital step attenuator. To save cost and time, the RF front end was implemented with discrete MiniCircuits components, although a provision was included for a custom-designed RF board to be added at a later time. A block diagram of the RF Front end is given in Figure 4. The specific components, along with some important parameters, used in each block are listed in Table 5.

One of the important design tradeoffs in the RF front end was to provide enough gain to allow the receiver to operate at or near the desired 10 meter range while still preserving an approximately 40 dB dynamic range. At 10 meters, the worst-case UWB path loss is aproximately 60 dB [1]. The transmitter produces a UWB pulse with

Figure 1: Block Diagram of the UWB Transmitter.

Figure 3: Simulated SRD pulse generator output.

Figure 2: Schematic of the Step Recovery Diode Pulse Generator (Based on [3]).

Christopher R. Anderson 4

a peak of 2.0 Volts (20 dBm); therefore, the received power is approximately -40 dBm. The ADCs on the receiver can tolerate a maximum input power of 0 dBm, therefore to maximize the dynamic range of the receiver, approximately 40 dB of amplifier gain will be required, necessitating the use of two ZX60-3018G Amplifiers.

The Mini-Circuits SLP-2950 low pass filter serves as a bandlimiting pre-select filter on the RF front end. Its purpose is to prevent out-of-band signals from overdriving either the RF amplifiers or the ADCs. Additionally, it limits the amount of noise allowed to enter the receiver, an important feature given the dynamic range requirements and noise issues discussed above.

The Hittite Microwave HMC307QS16G is a DC-4 GHz digital step attenuator that provides 2 – 32 dB of attenuation in 1 dB step sizes. The variable attenuator is used in the RF front end as an automatic gain control (AGC). The UWB SDR transceiver uses a very basic AGC algorithm by monitoring the ADCs overrange bits, as well as the ADCs two most significant bits. If the overrange bit is set for any one of the ADCs, then the receiver will increase the attenuation. Conversely, if the received signal fails to assert the two most significant bits in any of the ADCs, the receiver will decrease the attenuation. More sophisticated ADC algorithms can easily be implemented as well, due to the highly

programmable/reconfigurable nature of the transceiver.

4. ReceiverThe Receiver design is based on Time-Interleaved

Sampling (TI-Sampling) architecture. The basic concept is to oversample the analog received signal using a number of Analog to Digital Converters (ADCs), and then perform demodulation in the digital domain. Essentially, each ADC samples the received signal at a slightly different point in time in a round-robin type approach, as illustrated in Figure 6. The digital processing hardware on the board can then reconstruct the received signal to appear as if it were sampled by a single ADC. TI Sampling is advantageous in a COTS implementation as it significantly relaxes the requirements on the interface between the ADCs and the FPGA while still preserving the quality of the received signal.

A block diagram of the overall Receiver is shown in Figure 7. The RF front-end utilizes several ultra-broadband amplifiers, attenuators, and filters and feeds the received signal to the ADCs, as discussed in Seciton 3. An array bank of Dallas/Maxim MAX104 ADCs is used to sample the input analog signal. The samples are then sent to a Xilinx Virtex-II Pro FPGA for digital processing.

The UWB pulse width used in this communication system was chosen at 500 picoseconds. Accurately reconstructing this pulse in the digital domain requires a sampling rate of 8 GHz. At the target data rate (100 Mbps), an 8 GHz sampling rate results in exactly 80 samples per UWB pulse. Because the MAX104’s have a maximum sampling frequency of 1 GHz, a TI-Sampling array of eight of these ADCs can be used to achieve the target sampling frequency of 8 GHz [4, 5].

The performance of the TI-Sampling technique is highly dependant on sampling the received signal at precisely spaced intervals [6]. In most cases, clock distribution could be performed inside the FPGA; however, the Virtex II-Pro XC2VP70 FPGA has a timing jitter spec of ±100 picoseconds [7]. Considering that each

Table 5: Components and Component Parameters for the UWB SDR RF Front End

Item Part Number Gain(dB)

Noise Figure(dB)

3 dB Bandwidth

(MHz)

TX/RX Switch* ZSDR-230 -1.3 1.3 10 – 3000

Lowpass Filter* SLP-2950 -0.4 0.4 DC – 2950

RF Amplifier* ZX60-3018G 20 2.7 0.02 – 3000

Attenuator** HMC307QS16G -1.8 1.8 DC – 4000

* Minicircuits Part** Hittite Microwave Part

Figure 4: Block Diagram of the RF Front End.

Christopher R. Anderson 5

ADC samples the signal at 125 picoseconds increments, a clock jitter of ±100ps produces an unacceptable degradation in the received SNR. Thus, an ultra-low skew clock distribution network with tight tolerances on the clock jitter is required.

Fortunately, a number of manufacturers produce clock distribution and delay chips with very low jitter. The clock network was created using a FOX Oscillator RFV300 low-jitter oscillator (5 ps RMS jitter), an ON Semiconductor 10EL14D low-skew clock distribution chip (1.6 ps RMS jitter), and an ON Semiconductor

10EP195 programmable delay chip (3 ps RMS jitter) . When combined, these components produce an overall clock jitter of less than 10 ps RMS, and provide clock delay resolution of ±10 ps. The use of programmable delay chips, rather than fixed delay lines, provides skew management and the ability to accurately set the phase of the ADC clocks.

The MAX104 ADCs have an integrated demultiplexer that produces samples on a primary and auxiliary bus, each operating at half the sampling frequency (i.e. 500 MHz). The ADC also asserts a data ready (DREADY)

Figure 7: Block Diagram of the UWB SDR Receiver.

Figure 6: (a) TI-Sampling Illustrated using four ADCs. The first ADC samples the received signal at Point A, the second at Point B, the third at Point C, and the fourth at Point D. (b) The FPGA is then able to reconstruct the received signal as if it were

sampled by a single ADC, from [8, 9].

Christopher R. Anderson 6

signal, which is in-phase with the data. The DREADY signals are used as a clock in the FPGA to capture the ADC sample data. To input data at such high speeds, the FPGA uses Double Data Rate (DDR) Registers operating at half the DREADY frequency (i.e. 250 MHz). Due to analog RF constraints, all of the ADCs busses are connected to IOBs on only two quadrants of the FPGA.

Data demodulation is performed by a Digital Pilot-Based Matched Filter (DPBMF) receiver, which is similar to the Matched Filtering receiver that has been used in narrowband communications for many years [10]. A preamble in every data frame contains a set of pilot pulses. These pilot pulses are detected by the receiver and combined to form a digitized version of the expected received pulse, which is stored in the FPGA’s BRAM memory. The stored pulse is then used as the template waveform in a matched filter operation. The DPBMF is able to track distortions in the received pulse so that even in non-line of sight scenarios the averaging template should compensate for any pulse distortion in the received data pulses. The primary drawback to DPBMF is the noisy template formed from the pilot pulse waveforms. The extraneous energy causes the BER performance of the receiver to degrade due to the lack of perfect correlation between the pilot-based template and the received signal [11].

Matched filtering is performed by multiplying and integrating the received pulse with the template waveform, and then comparing the result to the receiver decision statistic threshold [10]. Mathematically, the operation is given by:

Z = ∑ i=0

79

x i y i (1)

Where x represents the ADC sample values and y represents the template waveform sample values. In the case of binary signal transmission, Z > 0 means that a “1” was transmitted and Z < 0 means that a “0” was transmitted.

To correct the effects of a one or two sample random timing jitter—as well as to maintain synchronization between Users—an early-late algorithm is implemented. The receiver performs matched filter coefficient with three template waveforms generated as follows:1. One template advanced in time by one sample2. One template with ideal timing3. One template delayed in time by one sample

The template waveform registers are connected in the form of circular shift register chains, and in case the late or early templates give a stronger correlation, the shift registers are advanced or delayed by one to correct the timing error. The correlation results are

then compared to the decision statistic threshold and the demodulated data bit(s) are stored in a BRAM. One of the embedded PowerPC processors can then transmit the data–via a UWB 2.0 interface–to a host computer.

5. Initial Performance ResultsSuccessful implementation of the UWB SDR

receiver requires very precise control over the ADC gain, offset, and–in particular– the timing mismatches [9]. Calibration and the use of a pilot-based matched filter receiver can mitigate the effects of static or slowly varying mismatches, but, in practice, mismatches could potentially fluctuate rapidly with time. To investigate the temporal nature of the mismatches, a prototype receiver based on a 2-ADC TI sampling array was constructed. The prototype receiver is essentially a scaled-down version of the full receiver discussed in Section II. The goal of the prototype receiver was (i) to demonstrate the feasibility of implementing a TI sampling ADC array using COTS components, and (ii) to determine the validity of the assumption that ADC mismatches are static.

To evaluate the prototype receiver, a 2 nanosecond UWB monocycle was generated using a Picosecond Labs 10,070A pulse generator. The individual ADC clocks were set to a frequency of 1 GHz, yielding a 2 GHz effective sampling frequency for the receiver. For comparison purposes, the same UWB monocycle was also digitized using a Tektronix TDS580D oscilloscope at a 2 GHz sampling frequency, and the voltage recorded by the oscilloscope was converted into an equivalent

Figure 8: A comparison of UWB monocycle samples recorded by a 2-

ADC TI array and a Tektronix TDS580D Oscilloscope. The effective sampling

rate in both cases was set to 2 Gsps. The voltage recorded by the oscilloscope was normalized to the maximum amplitude of

an 8-bit ADC.

References[1 ] C. R. Anderson, A. Annamalai, A. M. Attiya, N. August, R. M.

Buehrer, W. A. Davis, M. X. Gong, S. Griggs, D. Ha, S. Licul, S. F. Midkiff, S. Muthuswamy, J. A. Neel, J. H. Reed, S. Riad, B. M. Sadler, A. Safaai-Jazi, D. G. Sweeney, W. Tranter, An Introduction to Ultra Wideband Communications, New Jersey: Prentice Hall, 2005.

[2 ] J. H. Reed, Software radio: a modern approach to radio engineering. New Jersey: Prentice Hall PTR, 2002.

[3 ] J. S. Lee, C. Nguyen, and T. Scullion, “New uniplanar subnanosecond monocycle pulse generator and transformer for time-domain microwave applications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 49, No. 6, pp. 1126-1129, June 2001.

[4 ] C. Schiller and P. Byrne, “An 4 GHz 8b ADC system,” IEEE Journal on Solid-State Circuits, vol. 26, pp. 1781-1789, Dec. 1991.

[5 ] M. McTigue and P. J. Byrne, “An 8-gigasample-per-second 8-bit data acquisition system for a sampling digital oscilloscope,” Hewlett-Packard Journal, pp. 11-13, 1993.

[6 ] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEE Transactions on Circuits and Systems I, vol. 48, No. 3, pp. 261-271, March 2001.

[7 ] –, “Virtex-II Pro platform FPGA handbook v2.0,” product datasheet, Xilinx, Inc., October 2002.

[8 ] C. R. Anderson, A. M. Orndorff, R. M. Buehrer, and J. H. Reed, “An Introduction and Overview of Ultra Wideband Communications,” tech. rep., May 2004. MPRG Technical Report, Virginia Polytechnic Institute and State University.

Christopher R. Anderson 7

ADC output code level. These signals are shown in Figure 8. Note that the two pulses are nearly identical in both shape and time duration. The root mean square error between the two signals was computed to be 9.5% of the maximum pulse amplitude. Additionally, this experiment was performed for a large number of pulses over a duration of several hours. It was found that the ADC mismatches did not vary significantly over this time duration, implying that the proposed approaches are likely to be successful in mitigating the effects of ADC mismatches.

6. ConclusionThis paper presented an overview of the design

of the software-defined UWB communication system. This communication system was designed to be used as a powerful, general-purpose radio testbed, so that future students and researchers could use it for the evaluation of the impact of pulse shaping, channel coding, error control, and network algorithms on UWB communication. The testbed is highly reconfigurable; in addition to communications, the receiver can be used for propagation research, for RADAR or imaging, or for more traditional narrowband/broadband communications.

References[1 ] C. R. Anderson, A. Annamalai, A. M. Attiya, N. August, R. M.

Buehrer, W. A. Davis, M. X. Gong, S. Griggs, D. Ha, S. Licul, S. F. Midkiff, S. Muthuswamy, J. A. Neel, J. H. Reed, S. Riad, B. M. Sadler, A. Safaai-Jazi, D. G. Sweeney, W. Tranter, An Introduction to Ultra Wideband Communications, New Jersey: Prentice Hall, 2005.

[2 ] J. H. Reed, Software radio: a modern approach to radio engineering. New Jersey: Prentice Hall PTR, 2002.

[3 ] J. S. Lee, C. Nguyen, and T. Scullion, “New uniplanar subnanosecond monocycle pulse generator and transformer for time-domain microwave applications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 49, No. 6, pp. 1126-1129, June 2001.

[4 ] C. Schiller and P. Byrne, “An 4 GHz 8b ADC system,” IEEE Journal on Solid-State Circuits, vol. 26, pp. 1781-1789, Dec. 1991.

[5 ] M. McTigue and P. J. Byrne, “An 8-gigasample-per-second 8-bit data acquisition system for a sampling digital oscilloscope,” Hewlett-Packard Journal, pp. 11-13, 1993.

[6 ] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEE Transactions on Circuits and Systems I, vol. 48, No. 3, pp. 261-271, March 2001.

[7 ] –, “Virtex-II Pro platform FPGA handbook v2.0,” product datasheet, Xilinx, Inc., October 2002.

[8 ] C. R. Anderson, A. M. Orndorff, R. M. Buehrer, and J. H. Reed, “An Introduction and Overview of Ultra Wideband Communications,” tech. rep., May 2004. MPRG Technical Report, Virginia Polytechnic Institute and State University.

[9 ] C. R. Anderson, “A software defined ultra wideband transceiver for communications, ranging, or imaging,” tech. rep., October 2005. MPRG Technical Report, Virginia Polytechnic Institute and State University.

[10 ] J. G. Proakis, Digital Communications. New York: McGraw Hill, 1989.

[11 ] J. Ibrahim, “Notes on Ultra Wideband Receiver Design,” MPRG Technical Report, Virginia Polytechnic Institute and State University, April 14, 2004.