A Screen Tour Tutorial

Part I : What is onTAP?

Why Boundary Scan? / Why onTAP?

onTAP requirements

onTAP’s Features

Part II : Working with onTAP

onTAP Project Development

onTAP Installation

3

4

5-9

10

11,12

onTAP Screen Views 13-18

Part III : Starting an onTAP Project

Starting the Project 19

Development Screen Procedures 20-43

Test Screen Procedures 44-48

Manufacturing Test Screen Procedures 49

ProScan Screen Procedures 50-51

Part IV : Other Items

Sample DTS Cluster Test Model & Testing 52-54

Merge Netlists / What If I Don’t Have a Netlist? 55-56

onTAP’s DLL 57

User-Defined Tests 58-60

Troubleshooting

61-62Board Netlist Formats and Translators

Part V: Appendix

onTAP Menu Selections 63-64

65-66

Table of Contents

Why Boundary Scan?In 1985, the Joint Test Action Group developed the concept of incorporating hardware into standard components for digital electronic test and debug. Following the JTAG consortium, IEEE created the 1149.1 standard — the framework for boundary scan test. Over the past two decades the IEEE 1149.1 standard has gained immense popularity with design and manufacturing engineers due to its flexibility and low cost, and has grown to include new test methods that expand the reach of boundary scan tools beyond exclusive boundary scan devices.

Design engineers find IEEE-1149.1 tools to be particularly helpful in testing and clearing faults from prototype boards. The same tests are equally valuable when applied in manufacturing from PCs and in-circuit test equipment. Sharing test development costs in this manner amortizes and protects investments.

Why onTAP?onTAP meets the demands and challenges of full boundary scan test with a robust ATG and feature-rich palette.

‣ User-friendly GUI

‣ Automatic Test Generation for both scan and non-scan circuits

‣ Logical step-by-step process

‣ Graphical and interactive debugging

‣ Capability to run multiple chains simultaneously with multiple onTAP USB cables

‣ Online tips and help for each screen

‣ Unparalleled responsive technical support to help get your project up-and-running

onTAP Boundary Scan Requirements

• BSDL files for the device to be tested

• Board Level Netlist files:

‣ If you do not have a Netlist, see page 60

‣ For accepted Netlist formats and translations, see page 65• Cable/JTAG Controller:

‣ For USB access, onTAP USB Dual Channel HighSpeed 30MHz

or Standard USB cable only

‣For parallel port, any industry-standard parallel port cable

onTAP System Requirements

• onTAP Boundary Scan Test Software is run with MS Windows 2000, XP, Vista, or Windows 7• 500 MB of RAM, 30 MB of Disk space• 2.0 USB Port access if using onTAP’s USB Cable or HighSpeed USB Cable•Parallel Port access if using parallel port programming cable

onTAP’s Features• Test Development Environment:

‣ Includes over a dozen netlist readers; BSDL file syntax check; BSDL-circuit

location match-up; jumper and transparent device management; static

constraints (guards) for each pin; selection of multiple cables automatically

adapted to application; customizable tests; pin-level diagnostics; testability

warnings and reports

‣ Automatic Test Generation for both scan and non-scan circuits

• Critical Circuit and Testability Analysis:

‣ Identifies JTAG chains; jumpers “transparent” devices between boundary

scan pins; guards interfering buffers on boundary scan nets; dynamically

controls direction and enables pins on bus transceivers between boundary

scan pins

onTAP’s Features (cont.)

• Essential Test and Programming Capabilities:

‣ Tap Integrity tests; interconnect tests (opens, shorts); pull-up and pull-down

resistor tests; bus-wire tests; multiple, simultaneous chains; ICT translators;

SVF output files

‣Mid-state shorts testing for resistive or soft shorts

‣ Cluster and Memory Testing; project independent reusable models;

powerful, flexible C-like modeling language; multiple devices per scan

‣ FLASH programming

‣Automatic Test Generation works through non-scan components including

bus buffers and transceivers.

‣ ISP programming

‣CPLD and FPGA Programming ISP programming• User-Defined Tests

‣ User-defined tests (BIST, read/write internal registers)

‣ User-defined scans to set static values

‣ Custom GUI dialogue controls to suit user’s application requirements

onTAP’s Features (cont.)

• Run-time Test Environment

‣ Go/No-go testing; pin-level diagnostic messages; burn-in mode;

debug controls allow looping and user breakpoints; retry on fail;

program cable self-tests; ProScan Graphical Debug environment

• ProScan Graphical Debugging

‣ Go/No-go testing; graphical display of test vectors and pass/fails; pin-

level diagnostic messages; burn-in mode; debug controls allow looping

and user breakpoints; retry on fail; program cable self-tests; set pin

attributes; re-compile and re-run tests (development systems only);

toggle (wiggle) pins; view vector values; access and edit the netlist via

netlist browser

onTAP Features (cont.)

• Essential Utilities and Tools:

‣ Netlist merge; IDCODE selection and edit; differential pair identification;

input/output file organizer and viewer links; netlist composer

‣ SVF file parser shows drive/sense/fail information at each pin and net for

each SVF scan

‣ Viewer linked to essential files

‣ Vector display screens in ProScan

‣ User-defined tests tailored for BIST applications

‣ DLL

• Netlist Browser and Pin Wiggling:

‣ Easily select nets, devices and pins to inspect boundary scan properties and

check paths through circuits

‣ Set boundary scan signal values on selected pins and read back on other net

pins

‣ SAMPLE application system signal values on all pins

‣ Run script files

onTAP Features (cont.)

• Essential Utilities and Tools (cont’d.):

‣Netlist merge; IDCODE selection and edit; differential pair identification;

input/output file organizer and viewer links; netlist composer

‣SVF file parser shows drive/sense/fail information at each pin and net for

each SVF scan

‣Viewer linked to essential files

‣Wave-form display screens

‣User-defined tests

• On-line Help:

‣Context-related help is available on most screens

• Testability and Fault-Scoring Reports

• Demo board and sample programs with tutorial

FPGA Vendor

Generated

SVF

programming

file.

onTAP Project Development

onTAP reads boundary scan description files, board netlists, cluster test models, and flashprogramming files to produce SVF test files and reports. SVF files run directly through USB and parallel port programming cables.

xyz.bsd

Board Netlist

onTAP

Development

screen

Flash programming files,

logic and memory cluster

test files

Svf test file

(Serial Vector

Format) and

Reports

BSDL Files

Test Screen

onTAP Installation

• Download the software from www.flynn.com

• Self extracting program

• Once the software is installed, you may register onTAP and obtain an onTAP program unlock code by e-mailing the file \onTAP\ProgramFiles\license.txt to license@flynn.com. Please include the requested user information

• When Flynn Systems returns an activated license_xxxxxxx.txt file to you with activation codes, please place it back in the \Program Files\onTAP folder

• onTAP is ready to run and may be found in the Start Menu/All Programs.

• The Help system should provide answers to most questions. If you have questions not answered by Help, please contact us at support@flynn.com

(See Online Help Index: Installation)

onTAP Additional Information

Screen Views

onTAP has five screens, or views, that are used to organize information and tasks for the major aspects of boundary scan test development and test.

Screen Views:

• Load selected projects, including netlists, BSDL files, test files, and settings

• Inspect BSDL files and match them to devices on target project board.

• Identify GND/PWR nets and non-JTAG devices

• Establish JTAG chains, chain order, and transparency, merge netlists

• Add guards

• Select test procedures for interconnect and cluster testing

• Automatically generate tests and create reports

Test Development

Screen Views:

• Use the Browse button to select and load SVF files

• The GO button is used to run SVF files

• The Scan Sequencer list may be used to select one or more SVF files and run them in a designated order

Test

Screen Views:

• Select devices, pins, and nets to browse through an application circuit

• Pop back along a browse path

• Set boundary scan pin values and read back pin values

• Sample application mode signal activity

• Set guards in conjunction with Development screen’s Guards page

• Run script files to set and test pin values

Netlist Browser and Pin Wiggler

Screen Views:

•Restricts access to test development screen functions

• Provides manufacturing-related features such as burn-in, and inclusion of board and test operator information in test reports

• Loads and runs one or more SVF files just as they are run on the Test screen

•Provides access to ProScan graphical debugging environment

Manufacturing Test

Screen Views

• Views drive and capture signal activity at each BS I/O pin for each test step of a selected test

• Views and debugs test programs, including cluster test models, setting breakpoints, single stepping, examination of variables and pin values

• Running tests

ProScan Graphical Interactive Debugging

Starting an onTAP project

• Identify the location of a suitable text viewer. There are many situations during test project development in onTAP when a viewer is helpful. The Textpad viewer, at www.textpad.com, works very well. The menu item onTAP/View/Specify Editor/Viewer Program may be used to browse to select your viewer.

• When starting an onTAP project, place the essential source files, including BSDL files and a board level netlist, in a project folder, not within the onTAP folder. Please do not include period characters in folder path names.

• BSDLs are essential boundary scan input files and are required for all aspects of onTAP. The files must conform with IEEE Std 1149.1b-1994 or IEEE Std 1149.1-2001. However, onTAP will report instances in the files that are not in compliance with the specification, and, where possible, will attempt to create a test solution. onTAP accepts BSDL files with the following file name extensions:

‣ BSD

‣ BSDL

‣BSM

Verify and Organize Project Files

Board Netlist

U4 U5

U6 U7

•Verify BSDL File Syntax vs. IEEE

1149.1

•BSDL Matches Page associates

BSDL files with circuit locations

•Translate CAD netlists

•Build Boundary Scan model

xyz.bsd

BSDL Files

Test Development Screen and Notebook Pages

• The Test Development screen has 10 property pages which organize essential development tasks: assigning BSDL names

to circuit locations, selecting jumpers, checking guards and constraints, setting test options, selecting test procedures,

and running ATG.

• Generally, proceed from left to right to use the help provided on the pages themselves and also the help available from

the Help menu.

(See Online Help Index: Screens, Test Development)

Projects Page:

• To begin a project, place BSDL and netlist files in a project folder. Locate project folders outside of the onTAP path to avoid issues with product updates. (Make sure folder names do not contain period characters)

• Browse to select a project folder and then click OK. (See Online Help Index: Projects)

• Multiple tests can be developed within a project. Each test can have its own specific settings (jumpers, guards, etc.).

Selecting a Project Folder and Test Name

Projects Page Procedure

• Existing projects may be selected from the history list for loading.

• Select or specify a test name in Boundary Scan Tests

• Larger projects may require a considerable time to load and while they are loading, the Project tab light will flash yellow, indicating that onTAP is busy. If you wish to stop the loading procedure, click Cancel. Similar delays may be encountered at the Scan, Non-Scan, Jumpers, and TestGen pages as onTAP builds internal project models.

• A green light will replace the flashing yellow light if the load is successful, and onTAP will automatically move the focus to the next page, Scan.

• To close a project, return to the Projects page and click Close.

• onTAP automatically saves all settings, based on the selected test name, when a test is created on the TestGen page. Click on File, Save Project to save settings at an intermediate point in development.

• (CAD netlists are preferred, but if a board netlist is not available, onTAP’s Netlist Composer tool can create a “shell” netlist based on the BSDL files and their assigned circuit locations. This is helpful to get started with basic interconnect tests and to use the pin wiggler and sampling features on the Netlist Browserscreen.)

Scan Page

• Provides a means to match any BSDL files that have not been automatically matched to PC board device types. Consistency warnings are provided when attempting to match incompatible devices and BSDLs. In addition, a syntax check is performed on each BSDL file and the results may be viewed by clicking in the syntax column. (See Online Help Index: BSDL)

• Use Drag-and-Drop procedure to match TDO-to-TDI entries and AutoDetect to define boundary scan chains.

Associate BSDL Files and Devices on PCB & Define Scan Chains

Select a BSDL name in the lower left column.- - - - - - - - - - - - - - - - - - - - - - - - - - -Drag and drop the BSDL File, or right click on the device reference designator to matchBSDL to board device types.

onTAP will automatically detect and order your JTAG chains if youare unsure of devices and order.

onTAP Manages non-JTAG Circuits Between Boundary Scan I/O Pins

Boundary Scan I/O

Boundary Scan I/O

Boundary Scan I/O

Boundary Scan I/O

Boundary Scan I/O

Boundary Scan I/O

Boundary Scan I/O

• Facilitates connecting through transparent devices such as resistors

• Provides dynamic control of transceiver direction and enables pins during test

IEEE 1149.1 TAP bus

Resistor

Non-Scan

•Identify Power, Ground, nets connecting to JTAG pins, cluster and memory test devices and

differential signal pairs. (See Online Help Index: Identify)

The pin-to-pin pass through associations of many devices are listed in the LogicPinMaps.txt file in the onTAP folder. Project-specific pin mappings may be added ina similar manner to the ProjectPinMaps.txt file in a user’s project folder. Models for logic elements such as and gates are in the Logics.txt file in the onTAP folder.

Often the name of a device type does not exactly match that in LogicPinMaps.txt. In this case alias names may be assigned as shown in the file. Alias names may also be entered into the ProjectPinMaps.txt file.

Some CAD tools or settings produce netlists that use package names as part numbers or device-type names. As a result, the devices types available may representmore devices than just the devices that you wish to associate with an existing pin-map model. This may be easily dealt with on the non-JTAG page of theDevelopment screen. Select a model in the non-JTAG Library Models list and then select the corresponding components in the User’s non-JTAGs list. Circuitlocation replacements and associations are saved in the ReplaceLogicTypes_<test name>.txt file in a project’s project_settings subdirectory.

Right click on nets to identify Power and Ground

Identify non-JTAG devices, such as memoryAnd flash, that will be ‘cluster’ tested.

Also identify resistor packs or other non-Scandevices

Jumpers Page

• Identify Transparent Devices and Connect Through Transparent Devices add jumpers as required to

connect ISS I/O pins.

•Enables jumpers to be directly entered into onTAP using a pin-to-pin format.

(See Online Help Index: Jumpers)

Join Related Nets

List of jumpers will populate when jumpers

between pins are selected in the

“Manually Add Jumpers” dialog box.

Manually add jumpers

when necessary by selecting

the device, then pin.

Guards Page

• Helps disable interference from non-boundary scan devices. Constraint conditions, such as

setting and holding boundary scan output pins at logic low, high, and high-impedance may be

accomplished here. A direct means is provided to constrain or ignore pin values.

(See Online Help Index: Guards)

• The Guards Wizard can be used as follows:

1. Set guards as required to achieve a passing test.

2. Sequentially remove guards and run test. Restore guards if test fails.

Setting Static Pin Constraints

Right click on pin for guards menu.

Select and de-select by Clicking on

the selection.

A check mark indicates your selection

Select device for pin list.

Add comments to guards by

selecting and right clicking in the

Add Comment Column

onTAP Guards

Boundary Scan I/O

Boundary Scan I/O Boundary Scan I/O

U1 U2

Apply guard disable value

IEEE 1149.1 TAP bus

• Static guard constraints prevent unwanted interference from non-JTAG devices

U3Boundary Scan I/O

Output Enable

Cluster Page

The Cluster page is where devices and cluster test models are selected for cluster test and flash programming of non-scan devices. In addition, assignment of boundary scan to cluster device pins, based on Digital Test Syntax (DTS) cluster models, can be validated as well as changed. This page may be ignored for tests such as interconnect that are unrelated to cluster testing.

Assign any Cluster (Memory, Flash, CPLD,

FPGAs) Models on this page

Select a target location and a cluster

test/programming model.

Testability Page

• Alerts user in the event of significant testability issues, such as TAP pins connected to power and ground signals, TAP pins connected to boundary register pins, or cluster test pin requirements that cannot be satisfied. (See Online Help Index: Screen, Testability)

Check Blocking Test Issues

Click OK to stop the

flashing light and proceed

Select Summary Messages to

dismiss items that have been

reconciled.

Settings Page

• Select test options such as BUS-WIRE, PULL UP and PULL DOWN when initially developing tests. Then add MID-STATE SHORTS to detect faults where a shorted net results in mid-state, vs. hard one-or-zero level.

• Select SVF Test File Control Option to configure tests as required to control pins when entering and exiting tests in special circumstances. An example would be to establish as BSDL COMPLIANCE condition controlled by a BS I/O pin.

(See Online Help Index: Screen, Settings)

Select Test Options

Select any special test configurationsto expand test coverage.

Make sure to select an adaptor cable.This indicates to onTAP which JTAG Controlleryou will use for testing.

Settings Page / Differential Pairs Dialogue

(Access from Identify Differential Pairs button on Settings Page)

• When Differential Pair signals are not declared in BSDL files, this screen may be used to identify differential signals and associate positive/negative pairs.

Settings Page / Edit IDCODES

(Access from Edit IDCODES button on the Settings page)

• IDCODES may be edited due to differences from second source vendors. Edits may be made based on the diagnostic messages. A new test name should be assigned.

Select device for menu

Edit on this line

TestGen Page

• Test file generation is controlled from the TestGen page. Significant issues include:

‣ The interconnect test procedure produces a TAP test, shorts and opens tests

‣ Additional Interconnect test options are controlled by the selections on the Settings page

‣ Test procedures may be changed by right-clicking on selected devices for a menu

‣ All settings are saved and restored based on the designated Test Program Name

‣ Use Setup Cluster Test to test and program non-JTAG devices such as flash and other memory

‣ Tests are saved in Serial Vector Format (SVF) files

Select Test Procedures, Cluster Tests, Create Tests

IEEE 1149.1 TAP bus

TAP Integrity Test

Tests:

‣Instruction capture

‣ Instruction register length

‣ Bypass register

‣ IDCODES

U1 U2 U3TDO

TCKTMS

TDI TDI

TMS

TDO

TCK

TDI

TMS

TDO

TCK

Step-by-Step Test Strategy: Bringing a Project Up Simplifies Debug

1) Form Chain and bring up interconnect test which includes a TAP integrity test and bus-wire tests. Select Test Only Safe Circuits on the TestGen Page. Get this test running first, then:

‣ Include non-JTAG circuits between boundary scan pins to increase pin interaction. (See non-JTAG page)

‣ Adjust Guards as required to control non-JTAG devices that onTAP does not automatically manage. (See help on Guardspage)

‣ Add Pull-up/Pull-down resistor tests

‣ Add loopback jumpers on connector pins to improve pin-to-pin opens testing as well as shorts testing. (Avoid placing jumpers on adjacent pins so that shorts coverage will not be lost)

‣ Add memory and logic cluster tests to test non-JTAG devices and to check connections between devices

‣ Add Mid-State Shorts coverage

Bus Wire Test

IEEE 1149.1 TAP bus

• Each pin is allowed to drive high and low while other pins capture values

Boundary Scan

In/out

Boundary Scan

In/out

Boundary Scan

In/out

IEEE 1149.1 TAP bus

Interconnect Test

U1

• Includes TAP test

• Interconnect test - opens, pull-ups, pull-downs, bus wire, shorts, mid-state shorts

• Bus wire test - checks each driver on bus

• Boundary register length

• Multiple chains - simultaneous operation

FPGA

R1

U2 U3

CPU R2

FLASH DDR

Cluster Test

IEEE 1149.1 TAP bus

• Apply independent, reusable DTS programs through JTAG devices to logic, memory and flash devices

• onTAP automatically builds scans to position test vectors at the shift positions associated with each pin

• Flexible ATE programming language allows program to be adapted to specific applications as required

JTAG

Device

JTAG

Device

Flash

Memory

Logic

Reports and Files

• Reports, tests, and related files may be viewed by selecting the file name

Various reports and files may be viewed by searching through the tree and selecting the group of reports you wish to view. once you have selected a group, double click on the name of the report in the right hand window.

The reports will open using the browser you selected. If you do not have a viewer selected, pleaseestablish a browser.

PC Port JTAG Controllers/Cable Drivers

Establish your JTAG controllers by selecting cables from the menu bar, and selecting “Test and Programming Cables” the dialog box that opens will prompt you to load a project folder and select the cable/controller you want to use for test. You may also make additional test settings in this screen. Use the slider to select the test TCK rate. Test cables, update or ‘add and remove’ cables, and set Loopback Tests if desired.

(Access from PC Port menu)

Right click for menu to clear settings

Select a Cable name and then the associated chain, above

Select test file

Click “Create Adaptor File” after cables are assigned

Test Screen Controls

The onTAP Test Environment:

This tool is built into onTAP, and comes as a part of your active onTAP license. To use this tool you must have an onTAP created .SVF file, your application, a cable and a proper adapter file made for the application. Open the test screen by selecting You will have access to reports and be able to view test results and diagnostic messages.

Browse Button: Use to select an SVF test program file

Parallel Port Cable Check Box: Select to run test through a programming cable rather than the Boundary Scan Simulator

Test and Programming Cable Button: In the Tool Selection box in the lower right hand corner, enables you to select your USB cable.

Go Button: Select to begin a test

Stop Button: Stop a test while it is running

Loop Test: Repeat a test until “Loop Test” is clicked again or “Stop” is clicked

Run-Time Options: Click to review and select Burn-In options

SVF Test Files List: Click to select one or more files to run together. A drag-and-drop procedure may be used to reorder the SVF files. The order and selections are saved and restored when closing and reopening onTAP. Right click on a file for a menu andto view diagnostic messages

Test Screen

• Use the Test screen to run onTAP’s SVF file or imported SVF files for ISP. SVF files may also be run on the Manufacturing Test screen and on the Waveform Display screen.

‣ If a driver hasn’t been selected, select one from the menu PC Port / PC Port Driver Options...

‣ A TAP test is run on each device in the selected test file and the results are shown in the Message window

‣One or more SVF test files may be selected from the SVF file list. Use drag-and-drop to reorder the files

‣ Click Go to run the tests

Loading a Test Program

Test Screen

• Click the Go button to run selected SVF files. A list of the tests run is shown in the Message window and appear when a test passes is as shown

•In the event of a failure, diagnostic results are shown in the Message window. In addition, results are written to a .fail file, which may be viewed with the View Fails button

• Also, right click on an SVF files in the SVF File list for a menu to view the current test results for the selected file

Test Fail

You will see onTAP’s test sequence appear in the left hand column. Any failures will appear in this column.

This is the selection of tests available for this application.

Upon completion, this message will become either PASS or FAIL.The FAIL will produce diagnostic messages that can be viewed in the left hand column. Example of a Test Failure.

Netlist Browser

•When a project is open on the Development screen, the Netlist Browser may be selected via the yellow on the toolbar. The Browser may be used to browse through a project netlist, wiggle and observe pins, capture application mode signal activity, set guards, and run simple script files

• To browse, select a device or net, and then a pin from the Device Pins list. The Net Pins list then shows the pins from other devices on the selected pin’s net. Select a pin on the net to browse to that device, and so on. The Pop Net button can be used to back up along the browse path

• To wiggle pins, select a pin and then select a low or high waveform graphic shown below Device Pins. The selected pin should be set at the indicated value, and capture values are shown as up/down arrows next to pins having input cells

Open a project on the Development screen prior to selecting the Net Browser

Browse Application Circuits, Wiggle Pins, & Set Guards

Manufacturing Test Screen

The onTAP Manufacturing Test Only enables you run pre-developed onTAP JTAG tests for your application, while also providing access to ProScan, allowing you to view your tests, pin-level diagnostics, and toggle pins. The Manufacturing Test Only can be accessed by selecting the yellow

• The Manufacturing Test screen is similar to the Test screen but includes manufacturing-related features such as:

‣ Licensing to prevent access to the Development screen

‣ Operator and board information that can be included with test and failure reports

‣ Test Options controls include burn-in functions as well as ease-of-use tools such as presetting a starting test folder

Run Tests in Manufacturing

Test Options Burn-In

• A start folder may be prescribed for test projects and burn-in test procedures may be controlled from the Manufacturing screen’s Test Options dialogue

ProScan Graphical Debug Environment

•When tests are run using ProScan and an SVF file is loaded, expected sense/drive and capture signal activity is shown for each pin. When the Go button is clicked, a test is run and resulting test messages are shown in the Message box, upper left panel.

Run Tests

ProScan Graphical Debug Environment

View and Debug Test Programs

• When the test is run, diagnostics and tests may be single-stepped while observing signal activity and variable values from the DTS model. To set a breakpoint, select a line in the test model and then right click for a pop-up menu. Click the Go button to start the test. When the breakpoint is reached, scroll through the test to review test results.

Sample DTS Cluster Test Model Instructions

// The following excerpts show representative test instructions and are not an actual test model.

// DTS Test Program models focus on a device to be tested and are project-independent.

// That is they do not in general have to take into account their target JTAG test environment.

// However, EXTERNAL pin statements may be added to any model, to control project

// specific pins during test.

// Each pin control statement terminating in a semicolon represents on JTAG scan.

// Pins declared as PIO pins in the adaptors.txt file are driven directly by the test cable and are not scanned.

// Declare Signal Pins

.HEAD; // begin header with pin declarations for INPUT,BIDIR_TRI, and OUTPUT pins.

..INPUT( B7=A12,D6=A11,C6=A10, A6=A9, B6=A8, A3=A7, C3=A6,D3=A5,B2=A4,A2=A3,C2=A2,D2=A1,E2=A0,F2=CE#,G2=OE#,G4=CLK);

.BIDIR_TRI(G4=DQ11, F4=DQ10,G3=DQ9,F3=DQ8,E6=DQ7,H6=DQ6,E5=DQ5,H5=DQ4,H4=DQ3,E4=DQ2,H3=DQ1,E3=DQ0);

.OUTPUT(A4=RY_BY#);

.EXTERNAL(U37.AB6); // application-specific pin may be declared to control items such as bus transceiver direction.

.END HEAD;

// Declare Pin Groups

.DECLARE GROUP DATA( DQ10, DQ9, DQ8, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0);

.DECLARE GROUP ADDR( A10,A9,A8, A7, A6, A5, A4, A3, A2, A1, A0);

int a,x; // variables declaration

// Begin Test Program

.MAIN;

IL(U37.AB6); // Set EXTERNAL pin at a low value.

IH(CE#,OE#,WE#,WP#,RESET#); // Set input pins high

IL(BYTE#,CE#); // Set input pin low

IG(ADDR=X'000555',DATA=X'00AA'); // Set input group pin values

Continued on next page….

Sample DTS Cluster Test Model Instructions(cont.)

// Write data to addresses

ADDR = 1;

for ( x = 1; x < 5; ++x )

{

IG(DATA=X’5555’) IG(ADDR); // Input Group sets ADDR and DATA pin values

IL(CLK); // toggle clock, low to high

IH(CLK);

ADDR <<= 1; // shift ADDR one left

}

ID(DATA); // Input Disconnect disables drive of BS I/O pins onto DATA bus.

// Read data from addresses

ADDR = 1;

IL(OE#); // enable DATA outputs

for ( x = 1; x < 5; ++x )

{

IG(ADDR); // Input Group sets ADDR and DATA pin values

OG(DATA=X’5555’); // Output Group instruction tests pin group value

if ( FAIL ) // FAIL flag can be used after test

{

MESSAGE(“Fails. DATA = %%X”,DATA); // report failures

}

ADDR <<= 1; // shift ADDR one left

}

.END MAIN;

DTS Models and Cluster Testing

• DTS models are used to provide test instructions for a wide range of non-JTAG device types, for example, DDR2, SDRAM and

Flash memory, and serve as an input for cluster test generation from the TestGen page, where the Setup Cluster Test dialogue

matches the models to specific circuit reference designators

• In addition to pin and pin-group declarations, instructions provide for driving and sensing pins and pin-groups, program

control-flow, messages, and reading data from files for Flash memory programming

• The DTS Test Program Format document in on-line help provides a description of all of the instructions plus code examples.

The instructions, in particular the control flow expressions, are similar to those in the C programming language. A complete

DTS Manual is available from Flynn Systems, upon request.

Merge Netlists

• Netlists may be merged as follows:

1.Place one or more netlists in a folder by themselves

2. From the Tools menu, select Merge Netlists

3. Browse to the folder, select and load the netlists

4. Select one netlist in each of the Netlist Names lists, left and right. The netlists will be merged from right to left

• Right click on a netlist name for a dialogue to prescribe a prefix. A NULL prefix is recommended for one of the netlists. The prefixes appear before the nets and reference designators in the merged netlist so that common reference designators are distinguished and the source of the signal names is evident

• Select corresponding connectors on the two netlists

• Click the Join Netlists button

• Repeat steps 4-7 for each pair of connectors to be merged

• The merged netlist will have the name merged_netlist.xnf, and it should be moved into the project folder, where it must be the only netlist present

(Access from: Tools Merge Netlist Menu)

Combine Two Netlists

What If I Don’t Have a Netlist?

(Access from the Tools menu Merge Netlist)

• In general, a CAD board netlist should always be used for complete and reliable boundary scan test development, but when a

netlist is not available, onTAP can compose a skeleton netlist based on BSDL files

(See Online Help Index: Input Files)

onTAP’s DLL

Third party test executives may run the onTAP.dll dynamic link library module, which provides run-time control of tests and diagnostics. The procedure is as follows:

• Download the DLL and Example Program

‣ The onTAP DLL and a program example, call_ontap_dll.cpp, may be downloaded from http://www.flynn.com/products/downloads/call_ontap_dll.zip

‣ The ZIP files call_ontap_dll.zip includes all of the files required to link the DLL. A License file is required

• Link to the onTAP.DLL

‣ Link the onTAP.dll into your program. A sample code implementation for Microsoft Visual C++ is shown below

‣ Place the onTAP.dll file and onTAP’s license.txt file in the same folder as your executable that is linked to onTAP.dll

• Run the onTAP.DLL

‣ .SVF and .SVX files must be available in your project folder. The .SVF file is a test file and the .SVX file contains diagnostic messages

‣ After a teset runs, .FAIL and .TEST files contain test results and diagnostic messages

(See Online Help for additional information)

User-Defined Tests

• onTAP allows user-defined tests for purposes such as reading and writing to private registers, BIST and control of path-linking

transceivers for JTAG systems test. Following specified rules, user commands are entered into a program file which may be

compiled on the fly and executed with batch file commands or from within onTAP

• A simple example may be found in the onTAP/examples/UserDefinedTests folder. The basic idea is to control a file where

input and output scan data may be defined for each device. The control file may also direct JTAG TAPs to go to a specified

state. It provides for a variety of commands required to apply and capture data. The control file may be specified as an

argument in a standard batch file when calling and executing onTAP. onTAP compiles the scan-in, scan-out and state control

instructions into an SVF file on-the-fly and then executes it.

• Scan-in and scan-out data may be logged in a file called scandata.txt

• Simple dialogue-based GUI programs can facilitate the requirements of many user-defined test applications, such as loading

the scan-in data in the form of BIST instructions or register addresses and data

(See Online Help Index: User-Defined Tests)

Running User-Defined Tests

• First, a control file with user-defined commands (BIST, register control, system test, etc.) is created

• A batch program is created to call onTAP with the control file as an argument

• When the batch file runs, onTAP compiles the user-defined instructions into an SVF file and runs it. Scan-in and scan-out data

is captured in the file scandata.txt

• An optional GUI dialogue may be used to interactively change the contents of the control file, execute the batch file and

present data from the scandata.txt file

(See Online Help Index: User-Defined Tests)

Programs and Files for User-Defined Boundary Scan Tests

User’s Control

FileSVF File onTAP

Scandata.txt

File

Custom GUI

Control

Batch File

(.bat)

(See Online Help Index: User-Defined Tests)

CAD Source Files / File Extension

ACCEL EDIF .edf

Agilent .board or board x/y

BOARD STATION .net and .pkg

Cadence Allegro .net

Cadstar .net and .frs

FabMaster nets.asc + material.asc

GenCad .net

GenRad ckt

Isis .sdf

Mentor Neutral .neu

Mentor Veribest EDIF .edf (or rename .ASC ->EDF)

Orcad .net

PCAD .net

PADS PowerPCB .asc or .net

PC Easy .net

Cadence PST three pst files

(Continued Åc)

Board Netlist Formats and TranslatorsonTAP supports a wide variety of industry netlist formats. Currently supported formats are listed below. For examples of these

formats, see on-line Help Index: Board Netlist Files. Check here for updates

CAD Source Files / File Extension

Protel2 .net

Teradyne Ipl.dat

Teradyne Victory .cds

ViewLogic Allegro .net

ViewLogic Generic .net &..pkg

Zuken Vistula .rep + .lst

Other - EDIF .edif format

Board Netlist Translators (cont.)

Test and Programming Cables Select JTAG Controller/Test and Programming CablesLoad SVF files and adaptor files

Cables

onTAP Menu Selections

Tools

BSDL Syntax Check

DTS Syntax Check

Compose Board Netlist

Performs a Syntax and semantics check of BSDL files

Test Probe Requirements Report

Create a shell netlist for your application

Examine SVF

Merge Netlists

Compose SVF File

Creates examine_svf debug and analysis file

Merge multiple netlists into one

Compose SVF file from user-defined script file

Viewer

Set DefaultsRestore Default Test OptionsAccess Only Test Screen on Start Up

Select viewer/editor

Make the current settings the default settings

Restore previously saved settings

Select Manufacturing Test screen at start-up

onTAP

Run-time Test Options Select test options, such as Burn-In Mode

Summarize and ViewTest Reports

Summarize and View Test Reports

Test Reports Tester Probe Requirements Report

Extract from BOM Extract board information from the application BOM

List of all the Test Development Tabs Go straight to the desired development tab

Develop

onTAP Menu Selections (cont.)

ProScan Go to ProScan environment

Trace DTS InstructionsWrites each DTS instruction to a specified file while processing HEX Flash programming data

Examine SVF

Log TDO HEX data

Learn Test Results

Lock Test Options

Parses an SVF file, showing drive/sense pin values for each pin at scan

Captures raw TDI, TDO, measures scan data to a file

Learns test response and replaces predicted response

Locks the SVF file selections and the Cable driver and clock speed options

Debug

Net Browser Go to the Net Browser

Troubleshooting

Test Development Symptoms

• Circuit devices don’t appear on BSDL Matches page

‣ onTAP does not have a netlist translator for your netlist

• Difficulty getting test programs running

‣ The path, folder, or file names contain ‘.’ periods characters

‣ The project folder or files in it are write-protected, possibly because the user does not have

administrative privileges on the PC

Symptoms Running Tests

• TAP test fails, indicating INSTRUCTION CAPTURE failures

• Check the following:

‣ The correct cable has not been selected on the Adaptors page during test development

‣ The correct driver needs to be selected from the PC Port / PC Port Driver Options menu

‣ The cable is properly attached and runs the loopback cable tests

‣ Any TRST pins are pulled up and properly accounted for

‣ Any COMPLIANCE pins declared in the BSDL files are held at the correct values

‣ JTAG chains are correctly identified and configured. Chains and device order are shown at the

top of BSDL files

Troubleshooting (cont.)

• Interconnect tests or cluster tests fail

• Check that guards are properly applied. This is the most common reason for failures after the TAP

tests are running. Things to look for include:

‣Buffer or memory device enable pins that need to be turned off. For example, the data bus

output enable on an SRAM

‣ BSDL COMPLIANCE pins connected to BS I/O pins

‣ Signals that come onto the board from a connected assembly. This could be data or control

signals such as a power reset

• Check I/O voltage references. Devices such as FPGAs can have programmable threshold voltages

after configuration. A device may need to be programmed in order to communicate with another

device in a test, e.g., a memory device

• Fails to detect a shorts fault

• Enable the mid-state shorts option on the Settings page and regenerate the test. The short may

result in mid-state voltage level, undetectable with standard boundary scan.

• Check the Netlist Browser that BS I/O pins are on both shorted nets and that the nets are not

PWR/GND nets