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A review of the IEEE P1801:Standard for the Design and Verification of

Low Power Integrated CircuitsDesignCon 2009 Low Power Workshop

Dr. Gary Delp [email protected]

Distinguished Engineer, LSIVP & Technical Director, The SPIRIT Consortium

Vice Chair, IEEE P1801Past architect, Si2 Low Power Coalition

mailto:[email protected]

2February 2009

P1801 Outline• Motivation

– Key Messages– The Standards Environment – Interoperability Panel

• Modifying the abstraction – the presence of power-based corruption– Power Domains

• What they are• Combining Domains

– Protecting the boundaries• Electrically – level-shifting strategies• Logically – isolation strategies

– Preserving the State• Retention strategies

– Component/System Based design• Precedence based specification

• Simulating and Implementing same the Design• What changed and why you will like it!

3February 2009

Key Messages• For decades designers have worked with the digital abstraction, signals are

either logical true or logical false.• As with all good abstractions, this one had great utility

– it allowed optimizations in analysis,– separated two areas of difficult analysis, – making the design task achievable.

• This simple abstraction breaks as parts of digital circuits will be turned off relative to other parts– parts will enjoy low-power slow-down modes– parts will scream with performance and energy.

• The good news is that there is a simple way to express the relationships, boundaries, activities, and side effects of many power domains without having to give up most of the simplifications that the digital abstraction allow us.– The bad news is that there are currently two ways to do it.

Strategy• Using examples from a number of design flows and design problems

– Both UPF/P1801 and CPF to express the power constraints and characteristics of designs.

– The current state of interoperability is greater than last year.

4February 2009

Power Management Source & Flow• The traditional Synthesis flow

– Is augmented with Power

• Power source files are part of the design source. – Combined with the RTL, the power files

are used to describe the intent of the designer.

– This collection of source files is the input to several tools, e.g., simulation tools, synthesis tools, and formal verification tools.

• Multiple source files may be prepared specifically to enable reuse.

• The details of the “What” and the “How” are often produced by different parties.– Design refinement

Power SourceFile(s)

Power SourceFile(s)

Power SourceFile(s)

Power SourceFile(s)

Power SourceFile(s)

Power SourceFile(s)

Sim

ulat

ion,

Log

ical

Equ

ival

ence

Che

ckin

g, …

Verilog(Netlist) Verilog

(Netlist)

Synthesis

Verilog(Netlist) Verilog

(Netlist)

P&R

HDL/RTL

HDL/RTL

5February 2009

Attributes Specifiable in HDLHDL attribute Value UPF command

UPF_clamp_value <“0” | “1” | “Z” | “latch” | “any” | “value”>

set_isolation –clamp_value

set_port_attributes –clamp_value

UPF_sink_off_clamp_value ditto set_isolation –sink_off_clamp_value

set_port_attributes –sink_off_clamp_value

UPF_source_off_clamp_value ditto set_isolation –source_off_clamp_value

set_port_attributes –source_off_clamp_value

UPF_pg_type pg_type_value set_port_attributes –pg_type

UPF_related_power_pin port_name set_pin_related_supply –related_power_pin

set_port_attributes –related_power_port

UPF_related_ground_pin port_name set_pin_related_supply –related_ground_pin

set_port_attributes –related_ground_port

UPF_related_bias_pin port_name set_port_attributes –related_bias_port

UPF_retention <“required” | “optional”> set_retention_elements –retention

UPF_simstate_behavior <“ENABLE” | “DISABLE”> set_simstate_behavior

UPF_is_leaf_cell <“TRUE” | “FALSE”> set_design_attributes –is_leaf_cell

6February 2009

Outline• Motivation








7February 2009

Power management Structures: The Data Objects• Power Domain

– The collection of design objects that share common power attributes

• Power States– Controlled by Switches– Memories may require

Retention– States may require

sequencing info– States will effect simulation

• Relations & Connections between Domains– Level shifters– Isolation logic– “Gas Stations”

alternate supply• Identify elements• Manage• Implement• Analyze• Reuse

8February 2009

Simulation in Power Aware design flows• Simulation is used in design flows to check the functional characteristics of a

design to ensure that the design as recorded will perform to the purpose of the design

• Many simplifications are used in simulation to allow for running time efficiencies

• There is now a current “standard” for modeling supply nets and supply sets in an efficient design flow, P1801 speaks to it and provides an excellent framework.

• Simulation in a power aware flow should provide for indication of logical errors• Injecting X’s into a simulation in the design flow is a well understood and

efficient way to model that “something is amiss” and to propagate the effect of that “amiss” nature to the relevant portions of a design in the simulation.

• Power conditions can cause the corruption of logic and memory• The goal should be for a conservative simulation semantic, that is, the

simulation may corrupt more often than the implementation (an X always has some value in an instance of the implementation), but should never maintain a state or legal logic level if the implementation would not.

• Validation (static timing analysis, rail checking, design rule checks, etc) are performed to ensure that the conditions that are checked in simulation are supported in the implementation.

9February 2009

Full on

Full on

1 1 10 0 0X X X

The concept of corruption – supply Off (or Partially On)• Supply Nets

– Net_State• Full_on• Partial_on• Off

– Voltage• May be specified for

Analysis andTime based corruption 1 1 10 0 0X X X1 X X

Partial On or off

Partial On or off

10February 2009

Full on, ground

Full on, V2

Protection from corruption Electrical – Level Shifting• Supply Net

– Net_State• Full_on• Partial_on• Off

– Voltage• May be specified for

Analysis andTime based corruption

1 1 ?

Full on, V1

1 1 XXLevel

Shifter

1 1 110 0 00

11February 2009

Full on, ground

Full on, V2

Protection from corruption Logically – Isolation / Clamps• set_isolation

Full on, V1Partial On or off

12February 2009

Simulation Model matching – requires refinement of definition

• Default model for Level shifting– Any difference in the current values of the supply set will cause corruption– Modification: A range may be declared legal– Modification: A level shifter may be inserted

• Dual supply – corruption caused when either supply is not full on• Default model for Clamps (isolation)

– Level shifter model applies– X’s may be eliminated with logic if the X has the same supply– Modification: ordering may be useful in the boundary specification

• Default Model for Retention– Memory is powered by retention supply, save saves current value, restore

restores the saved value, the saved value is corrupted when the retention supply is corrupted.

– Modification: other models may be introduced, they replace the default– Note that implementation may have time dependencies, these must be

specified so that corruption can be introduced in simulation.

13February 2009

Power state detection and analysis• VHDL, Verilog, System C packages to specify the interface for active

power state detection and triggering on defined symbol names to be added.

• Adding these symbols to the sensitivity list of modules important in verification. (Includes “Logic Analyzer” type tracing based on power states.

14February 2009

Supply sets –• Because a single supply net has no meaning in isolation to the power

being supplied to any design element, it would be helpful to have the object type “supply set” which does have meaning. For a domain, the following supply set handles are used:primary, default_retention, and default_isolation.

• Supply sets collect supply nets together so that they can be treated as a unified (and progressively defined) bundle.

• This is done for efficiency, clarity, simulation, and brevity.

• Pg pins may be associated with supply set functions to support automatic connection.

• Completion of supply set specification determines the “equity” of the verification runs.

15February 2009

Design

Design/Component Hierarchy

Component

Component

Component

Component (hierarchicalRef)

16February 2009

Design

Design/Component Hierarchy

ComponentHRef

ComponentHRef

ComponentHRef

17February 2009

Packaged Electronic Design IP in the flow• When designing IP (a component), the assumed context must be

able to be defined.– set_port_attribute – supply_set– The context is a rich one, with the potential of multiple domains and

control signals• When the IP (component) is incorporated into a design, the

elements of the component will be incorporated into extent of the design.

• The domains of the component may also be usefully be incorporated into the domains of the “parent” design

18February 2009

Create Component in an environment/Context

Supply sets and set_port_attributes

19February 2009

Use Component in an Design

20February 2009

Use Components in an Design

21February 2009

Use Components in an Design

create_composite_domain

22February 2009

A

B C D

E F G H I J

(Active scope)

-elements {A A/C/H} -exclude_elements {A/C A/D}

Precedence based specification

23February 2009

A

B C D

E F G H I J

(Active scope)

-elements {A A/C/H} -exclude_elements {A/C A/D}


24February 2009

A

B C D

E F G H I J

(Active scope)

-elements {A A/C/H} -exclude_elements {A/C A/D}-transitive TRUE


25February 2009

Halfway: Key Takeaways• Power Intent Goals

– Scalable & transportable methodology for describing and reasoning from:• Power Domains• Power Supplies• Switches• Acceptable and forbidden Power Modes or States• Isolation, Level shifting, Retention

– Retention – preserving the state• Richness of descriptive capability

– Support Reuse and transport of design equity• Identification and Constraints – The Platinum Source• Refinement and Configuration – The Golden Source• Implementation and analysis – The Silicon Source

– Key Goal – all about equity preservationImproving productivity Through Higher Abstraction

26February 2009

Outline• Motivation








27February 2009

Outline• Motivation• Modifying the abstraction – the presence of power-based corruption


– Supply sets & supply network– Power states and simstates– Power domains– Power constraints and attributes– Power domain interface design– Retention specification

UPF 2.0Why We Did What We Did

And Why You’ll Like It!

With Thanks to:

Stephen BaileyChair, IEEE P1801

Director of Product Marketing, DVT

29February 2009

Agenda• Supply sets & supply network

• Power states and simstates

• Power domains

• Power constraints and attributes

• Power domain interface design

• Retention specification

30February 2009

How is a Memory Powered?

Data

Addr

CK

AS

Data

Power

Ground

• Single supply of power and ground• For both read/write logic and the memory core?

• Single supply of power and ground with bias control• Supporting low power memory retention mode?

N-Well bias

• Dual supply• One for the read/write logic• Another for the memory core with 3 modes

Core pwr

Core gnd

Core bias

31February 2009

UPF 2.0 Supply Sets• A supply set defines a complete power source

– The supply set is named and the name is defined in the current scope that the create_supply_set command is executed within

• May contain any number of supply set functions– Each net provides a function for the set– 6 functions are predefined

• Power• Ground• Pwell• Nwell• Deeppwell• Deepnwell

– Users may define their own functions for a set– May specify a reference ground

• Default is “earth ground” – 0 volts

• Supply nets are associated with each defined function of the set

32February 2009

Supply Set Refinement• Supply set may be created without defining any functions

– Simulators may assume power and ground functions exist by default to support early simulation with a partial supply network specification

• Users may add new functions to a supply set– E.g., add bias net(s) to a set with only power and ground

• Supply nets may be associated with the function when the function is defined or later– Supports early simulation/analysis before complete supply network is

specified

• Reference ground can be specified at or after the supply set is created

33February 2009

Supply Set Connection Basics• The supply nets of a set are connected based on the association of the

function of the net and pg_type for a port

• pg_type– In an implementation context -- .lib (Liberty)

• Library attribute identifying pins on the cell as being power, ground, etc.– In a verification context -- HDL model

• An HDL- or UPF-specified attribute on a port with the name pg_type and a string valued attribute identifying the port as power, ground, etc.

• The connection is made from function => pg_type– By default, the names must match– User may specify a non-default mapping

34February 2009

Associating a Supply Set• Certain supply sets are assumed to exist

– Power domains:• primary, default isolation and retention supplies

(The default isolation & retention supplies are optional but predefined)– Isolation strategy, retention strategy and power switches

• Default supply for the functionality– Level shifter strategy

• Input and output supply sets

• Each of these assumed supply sets can be referenced by a handle– primary, default_retention, default_isolation– supply (for switch, isolation and retention strategy)– input and output (for level shifter strategy)– These handles are predefined

• Users may define other supply set handles for a power domain• A supply set handle is “empty” until an actual supply set is associated with it

– But the handle can be referenced anywhere that the supply set or functions within the supply set need to be referenced• Often, only the context is known while the specifics of which supply set is used in that context is not• Supply set handles allow deferring details• Supply set handles hide the details allowing easier maintenance and separation of responsibility

35February 2009

Implicit & Automatic Supply Set Connections

• Implicit connections occur when:– Primary supply to all elements in a domain not explicitly or automatically

connected to a supply set– Isolation supplies to isolation logic inferred from set_isolation– Retention supply to the retention register logic inferred from set_retention– Level shifter input and output supplies to level shifters inferred from

set_level_shifter

• Automatic connections are limited to a power domain context– Applies to a supply set handle for a domain (domain reference)– The –elements list is limited to elements within extent of the domain

• If –elements is not specified, then all elements in the domain– Only those elements with ports attributed with matching pg_types are

automatically connected

36February 2009



• Power domains




37February 2009

Power States Overview• UPF 1.0 supported system power state specification in a table

format

• UPF 1.0 PSTs are useful– Provide information necessary to identify where level shifting is

required– Help verification tools to identify illegal/undefined states

• But also limiting– Flat, non-hierarchical– No information hiding– Did not ensure simulation behavior accurately reflected the hardware

to be implemented• For example: If power & ground are both on, is that sufficient to know if the

logic has sufficient power to support switching?Doesn’t voltage matter?

38February 2009

UPF 2.0 Power States

• Objects which can be attributed with power states:– Supply sets

• Defined in terms of the state of the supply nets of the set– Power domains

• Defined in terms of the state of supply sets, supply nets and the power state(s) of other domain(s)

• What is included in definition is relevant to the state of the domain and reducible to the state of supply nets

• This provides the ability to hierarchically specify power state relationships

• Can also specify state transitions

39February 2009

Defining a Power State• Same command for both supply sets and domains– add_power_state object_name

-state state_name-supply_expr {boolean_expr}-logic_expr {boolean_expr}[-simstate simstate]-legal | -illegal-update

• Can be refined (-update) over time as design evolves– -supply_expr is the golden specification of the power state – used by synthesis and LEC– -logic_expr initial, approximation of the power state definition (in the absence of a –

supply_expr)• -logic_expr becomes an assertion check when –supply_expr is specified• -supply_expr and –logic_expr state definitions can be refined

– supply_expr’ = old_supply_expr && new_supply_subexpr

• Legality– The default for a user-defined power state is legal

• Specify –illegal to override default; -legal to be explicit

– By default, undefined power states are illegal• Override default legality of undefined power states for an object:add_power_state my_power_domain -legal

40February 2009

Power States of a Supply Set

• The operational capability of logic powered by the supply

• Predefined supply set power states:– DEFAULT_NORMAL

• All nets of the set are FULL_ON• The net may be at any voltage level

– DEFAULT_CORRUPT• When the supply set is in a state that does not match a defined state or

the DEFAULT_NORMAL state

– With only the predefined power states• Supply set semantics are identical to UPF 1.0 semantics for power/ground

pairs

41February 2009

Simulation States (simstates) Provide Semantic Behavior

Simstate Combinatorial Logic

Sequential Logic

Corruption Semantics

NORMAL

CORRUPT

CORRUPT_ON_ACTIVITY

CORRUPT_SEQ_ON_CHANGE

CORRUPT_SEQ_ON_ACTIVITY

NOT_NORMAL

Fully functional Fully functional None

Non-functional Non-functional Wires driven by logic and regs powered by the supply corrupted immediately on entering state

Non-functional Non-functional Wires driven by logic and regs powered by the supply corrupted when any input to the logic is active

Fully functional Non-functional Regs powered by the supply corrupted when the value of the register is changed

Fully functional Non-functional Regs powered by the supply corrupted when any input to the reg is active

Deferred Deferred By default, same as CORRUPT.Tool may provide an override

BiasModes

42February 2009

Power States of a Power Domain• The –supply_expr is defined in terms of:

– State(s) of supply set(s) – e.g., the primary supply for the domain– State(s) of other power domain(s)

• Allows specification of a dependency between one domain’s power state and another domain’s state – useful for subsystem and system level power state specification

– States of supply nets

• Ultimately, the power state of a domain is defined in terms of supply net states

• Can be refined– -logic_expr can be used as an early approximation of the state definition– -supply_expr must be defined for implementation– Logic and supply expressions can be refined with && of new expressions with

previously specified expressions

43February 2009



• Power domains




44February 2009

Key Terms with Power Domains• Power domain: A collection of design elements that share a primary

supply set

• Composite domain: A container comprising a set of power domains called subdomains.

– Composite domains are meant to replace merged domains– merge_power_domains command carried forward for backward

compatibility

45February 2009

Example Power Domain & Logic Hierarchy

• Colors represent power domains (5 power domains)• The association of a domain with a scope in logic design

provides a pseudo-hierarchy of domains– The domain hierarchy has no semantic meaning in UPF– But is convenient for constructing hierarchical power states

toptop

PMBPMB B1 B2B2 B3B3

B1M1 B2B2B2B2

B2

46February 2009



• Power Domains




47February 2009

Power Constraints & Attributes• UPF 2.0 achieves greater success in separating low power design constraints

from implementation– Better meets the needs of soft IP providers– Specify relevant information if the IP is to be implemented in a low power context– Does not over-specify the low power implementation– Facilitating reuse of the IP in any low power implementation

• Commands– set_port_attributes– set_retention_elements

• Attributes– Allow many constraints to be specified as HDL attributes– Should allow IP providers to deliver only HDL source

48February 2009

set_port_attributes• Specifies attributes of a port that may be relevant to the low power

implementation of the element– Can be applied to an instance or a model (all instances of a model)– Generally relevant only if port is on the interface of a domain

• Attributes– General: attribute-name : value pair– Isolation related for logic ports:

• Clamp value• Sink off clamp value• Source off clamp value

– Supply-related constraints for logic ports:• Related power, ground and bias ports

– Why isn’t it a relatedy supply set?

• Receiver supply• Driver supply• Repeater supply

– Supply port attribute• pg_type (power-ground type as per Liberty or implementation library conventions)

49February 2009

Attributes Specifiable in HDLHDL attribute Value UPF command

UPF_clamp_value <“0” | “1” | “Z” | “latch” | “any” | “value”>

set_isolation –clamp_value

set_port_attributes –clamp_value

UPF_sink_off_clamp_value ditto set_isolation –sink_off_clamp_value

set_port_attributes –sink_off_clamp_value

UPF_source_off_clamp_value ditto set_isolation –source_off_clamp_value

set_port_attributes –source_off_clamp_value

UPF_pg_type pg_type_value set_port_attributes –pg_type

UPF_related_power_pin port_name set_pin_related_supply –related_power_pin

set_port_attributes –related_power_port

UPF_related_ground_pin port_name set_pin_related_supply –related_ground_pin

set_port_attributes –related_ground_port

UPF_related_bias_pin port_name set_port_attributes –related_bias_port

UPF_retention <“required” | “optional”> set_retention_elements –retention

UPF_simstate_behavior <“ENABLE” | “DISABLE”> set_simstate_behavior

UPF_is_leaf_cell <“TRUE” | “FALSE”> set_design_attributes –is_leaf_cell

50February 2009

General Purpose Attributing• set_design_attributes provides a general attributing capability:

– set_design_attributes –attribute name value– Only the predefined attributes covered in the 1801 standard, have defined

semantics– Any other attributes have no standard semantics definition

• Various tools and design policies can use the general attributing capability with non-standard semantics

• Allows for future addition of new attributes

51February 2009



• Power Domains




52February 2009

Domain Interface Design• Major considerations for power domain interfaces

– Isolation– Level shifting

• Both were supported in UPF 1.0; What’s new in 2.0?

53February 2009

Defining Isolation Strategies• UPF 2.0 eliminates the need for set_isolation_control

– All isolation information specifiable in set_isolation– Can be called multiple times to add more information to the same isolation strategy,

e.g.,• Clamping value specified first• Isolation enable signal specified next• Isolation supply specified last

• Isolation can be specified relative to a port– Use with bottom-up implementation

• Or specified relative to connectivity from a domain to another domain– Use in contexts where the connectivity information is known

• Ports or domain connections can be specified as no_isolation

• Can specify that isolation is not to be applied if the driver and reader of the port have the same supply– Backward compatibility with 1.0 requires isolation in this case– Added ability for user to allow tools to optimize away isolation in this case

54February 2009

-diff_supply_only implications

• B2 and B3 are siblings and both roots at the top of the Purple power domain• The wire W connecting B2 to B3 will be isolated unless

–diff_supply_only is specified

toptop

PMBPMB B1 B2B2 B3B3

B1M1 B2B2B2B2

B2

W

55February 2009

More Isolation Enhancements• Clamping:

– Reason for clamping can be associated with source or sink supplies (relative to the port) being CORRUPT

• Multi-enabled isolation support– Can specify an ordered list of:

• Clamp value• isolation enable signal• isolation supply

– The ordering of isolation/enable/supply is applied– Defined defaults for all when list size is one for some but more than one for other(s)

• Additional –location options– fanin, faninout– other (place in the other domain)

• -instance provides the name of an isolator instance in the HDL source and the port that it is isolating– Allows isolation supply information to be added in UPF

56February 2009

Multi-Enbled, Multi-Supplied Isolation

// Connect the retmem_supply to an instance of a retention memoryset_isolation multi_enable_strategy

-domain purple-elements {portA}-isolation_signal {iso_en1, iso_en2}-isolation_sense low-isolation_supply_set {iso_supply1, iso_supply2}-clamp_value {‘0’} // NOTE: clamp value is same for both

A

iso_en2iso_en1

<source>

is_supply1 is_supply2

57February 2009

Level Shifting• UPF 2.0 clearly specifies that set_level_shifter should not be required when all

power states are exhaustively specified– Command is continued for backward compatibility with 1.0– Allows partial power state specification + set_level_shifter commands to fill in gaps

• This is not the recommended usage

• Enhancements include– Ability to specify a complete threshold specification– Same –location additions as isolation (fanin, faninout and other)– Supply specification – input, output and internal– -instance allows level shifters to be instanced in HDL while using UPF to provide

supply information– -force_shift to prevent tools from optimization removal

58February 2009

Mapping Isolators and Shifters• UPF 1.0 map_level_shifter_cell and map_isolation_cell provide

backward compatibility– Recommend these commands not be used

• UPF 2.0 provides the use_interface_cell command– Supports mapping isolators, level shifters and combined cells (enable level

shifters)– For isolation cells, allows very late specification of clamp value – when any

is specified clamp value– -force_function informs verification tools to use the behavior of the used cell

and not the set_isolation and set_level_shifter specified behavior– Optional specification of an inverter supply set

• If an inverter must be applied to an input or output to ensure correct functionality –e.g., isolation enable polarity

59February 2009



• Power Domains




60February 2009

Retention Enhancements Overview• set_retention_control is now unnecessary

– Supported for backward compatibility with 1.0– All retention information can be specified in set_retention

• Command can be invoked multiple times for the same retention strategy• Subsequent calls cannot provide conflicting information• Subsequent calls can provide additional information

• Retention register may be instanced in HDL with UPF providing supply information– -instance argument to the command

• Improved functional specification in set_retention

• Enhanced mapping capabilities with map_retention_cell

61February 2009

Retention Register Functional Specification• Can specify 3 relevant conditions

– -save_condition: Condition must hold for save to occur when save signal is active• Register is corrupted if save signal is unknown or save signal is active and save condition is unknown

– -restore_condition: Condition must hold for restore to occur when restore signal is active• Register is corrupted if restore signal is unknown or restore signal is active and restore condition is

unknown– -retention_condition: Condition must hold when the primary supply is not NORMAL

• Retained value is corrupted otherwise

• 0-pin (no save or restore) retention register now supported– -use_retention_as_primary– NOTE: No level shifting will be inserted. Retention supply must be level compatible with

primary• More functional parameters

– RET_SUP_COR – register value is corrupted based on simstate of retention & primary supplies

– NO_RET_SUP_COR – register value is corrupted only based on simstate of primary supply– SAV_RES_COR – register is corrupted if save and restore are active simultaneously (both

conditions must also hold)– NO_SAV_RES_COR – save and restore can be active simultaneously

62February 2009

Mapping Retention Register Cells

• map_retention_cell command is enhanced– retains compatibility with UPF 1.0

• -lib_model_name port mapping enhanced– Canonical register interface defined

• CLOCK - signal whose rising edge triggers register to load data• DATA - signal whose value is the next state of the register• ASYNC_LOAD - signal which causes register load data when its value is one• OUTPUT - signal that propagates the register output

– Port mapping connects cell ports to signals via the following symbolic references• retention_ref.function_name – the supply nets that compose the retention supply• primary_ref.function_name – the supply nets that compose the primary supply• save_signal• restore_signal• UPF_GENERIC_CLOCK – the canonical CLOCK signal• UPF_GENERIC_DATA – the canonical DATA signal• UPF_GENERIC_ASYNC_LOAD – the canonical ASYNC_LOAD signal• UPF_GENERIC_OUTPUT – the canonical OUTPUT• All logic signals can be inverted by using Verilog bit-wise negation operator (~)

– Retention supply powers inverters for save and restore– Primary supply powers inverters for any other signal

63February 2009

Mapping for Implementation and Verification

• Retention registers can be mapped for implementation or implementation and verification use

-lib_cell -lib_cell_type -lib_model_name

Verification Semantic Implementation constrained to

N N N ERROR ERROR

N N Y model_name model_name

N Y N RTL with retention lib_cell_type

N Y Y model_name lib_cell_type

Y N N RTL with retention lib_cell_list

Y N Y model_name lib_cell_list

Y Y N RTL with retention a cell from lib_cell_list that also has lib_cell_type

Y Y Y model_name a cell from lib_cell_list that also has lib_cell_type

Thank You!

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