A proposal of novel resistive switching devices using … Master thesis A proposal of novel...

2013 Master thesis

A proposal of novel resistive switching devices

using CeOx with NiSi2 electrodes

Department of Electronics and Applied Physics

Interdisciplinary Graduate School of Science and Engineering

Tokyo Institute of Technology

11M36106

Shinichi Kano

Supervisor

Professor Hiroshi Iwai

Associate Professor Kuniyuki Kakushima

ReRAM have been considered as promising candidates to replace conventional charge based

memories due to its process compatibility with complementary metal-oxide-semiconductor

(CMOS) fabrication and its simple metal-insulator-metal (MIM) structure, besides low voltage

and fast operation with excellent retention properties. Although many reports deal with transition

oxides for filament-based switching behaviors, on and off resistance ratio is still small. Based on

the conductive-filament switching model, HRS and LRS are operated by the annihilation and

creation of the oxygen vacancies at the tip of filament within the oxide, which is commonly

created during initial forming process. The HRS/LRS ratio is strongly dependent on the forming

process, and is sensitive to the compliance current as it determines the size of the filament. In

this thesis, resistive switching properties of Ce oxides have been characterized and the impact of

metal electrode materials has been clarified. Ce oxides are known to present valence number

fluctuation and to have high oxygen ion conductivity, therefore they are expected to have

potentials for resistive switching devices. A large on and off resistance ratio over 106 with

forming-free characteristics has been achieved with W/CeOx/NiSi2 structure ReRAM. This

novel forming-free resistive RAM with large resistance ratio, high endurance and fast switching

is proposed using a laminated structure of thin SiO2 formed in CeOx/NiSi2 interface and CeOx

for active resistive switching and buffer high-k layers, respectively. For set-process, high electric

field induces a breakdown to the SiO2 to change the state to LRS, as the dielectric constant is

low (k~4). For reset-process, oxygen ions from the buffer high-k layer induce local anodic

oxidation of the breakdown spot to create SiO2 and change the state to HRS. Besides, reaction of

SiO2 formation and dissociation exist in reset process were confirmed by measurement of

transient response. SiO2 formation is due to oxygen ions come from CeOx. And SiO2

dissociation is due to electron impacts to break the created Si-O bondings. Moreover, guideline

of selection for buffer layer was proposed. The requirements for buffer high-k layer include high

dielectric constant and high breakdown field so as not to form filaments in the buffer high-k

layer. In addition to that, the requirement for buffer high-k layer is high oxygen ionic

conductivity in room temperature.

Contents

Chapter 1 Introduction...................................................................................................4

1.1 Background of this work .....................................................................................5

1.2 Introduction of emerging research non-volatile memory ..................................7

1.3 Introduction of Resistive random access memory (ReRAM)...........................9

1.3.1 General introduction of ReRAM device ......................................................9

1.3.2 Structures and operation of ReRAM device ..............................................10

1.3.3 Resistive switching mechanism in ReRAM ..............................................12

1.4 Introduction of Ce oxide as buffer layer for ReRAM......................................15

1.5 Purpose of this study..........................................................................................15

1.6 Configuration of this thesis................................................................................15

Reference ..................................................................................................................17

Chapter 2 Fabrication and characterization..................................20

2.1 Device fabrication process.................................................................................21

2.2 Detailed process .................................................................................................23

2.2.1 Si surface cleaning .......................................................................................23

2.2.2 Thermal Oxidation Process .........................................................................23

2.2.3 Photolithograph............................................................................................24

2.2.4 Etching process ............................................................................................25

2.2.5 E-beam evaporation.....................................................................................26

2.2.6 RF magnetron sputtering.............................................................................27

2.2.7 Rapid Thermal Annealing ...........................................................................28

2.2.8 Thermal evaporation....................................................................................29

2.3 Characterization..................................................................................................30

2.3.1 Current-voltage measurement.....................................................................30

2.3.2 Pulse measurement ......................................................................................30

Chapter 3 Influence of bottom electrode for ReRAM..............31

3.1 Operation of CeOx based ReRAM with W, Ti and Ni bottom electrode........32

3.2 Operation of CeOx ReRAM with TiN bottom electrode.................................35

3.3 Operation of CeOx ReRAM with p+-Si bottom electrode ...............................37

3.3.1 Characteristics of W/CeOx/ p+-Si ReRAM ................................................37

3.3.2 Control of SiO2 formed between CeOx/p+-Si interface .............................38

3.4 Operation of CeOx ReRAM with NiSi2 bottom electrode...............................40

3.4.1 Characteristics of W/CeOx/NiSi2 ReRAM.................................................40

3.4.2 Control of SiO2 formed between CeOx/NiSi2 interface.............................43

3.4.3 Temperature resistance of W/CeOx/NiSi2 ReRAM...................................45

3.5 Conclusion..........................................................................................................48

Reference ..................................................................................................................49

Chapter 4 Operation mechanism for W/CeOx/NiSi2

structure ReRAM and guideline of selection

for buffer layer..........................................................................50

4.1 Set process for W/CeOx/NiSi2 structure ReRAM............................................51

4.2 Reset process for W/CeOx/NiSi2 structure ReRAM........................................52

4.3 Dependence of CeOx thicknesses......................................................................53

4.4 Guideline of selection for buffer layer ..............................................................56

4.5 Conclusion..........................................................................................................60

Reference ..................................................................................................................61

Chapter 5 Transient response for reset process............................62

5.1 Transient response characteristics for reset process .........................................63

5.2 Model of local anodic oxidation SiO2 breakdown spot in reset process.........66

5.3 Conclusion..........................................................................................................67

Chapter 6 Conclusion...................................................................................68

Acknowledgement...........................................................................................70

-Chapter 1 Introduction-

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Chapter 1

Introduction

1.1 Background of this work

1.2 Introduction of emerging research no-volatile memory

1.3 Introduction of resistive random access memory (ReRAM)

1.3.1 General introduction of ReRAM device

1.3.2 Structures and operation of ReRAM device

1.3.3 Resistive switching mechanism in ReRAM

1.4 Introduction of Ce oxide as buffer layer for ReRAM

1.5 Purpose of this study

1.6 Configuration of this thesis

Reference


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1.1 Background of this work Now, memory technology plays a significant role in the market of electronics products. It is

widely used in personal computer, mobile phone, portal storage devices and so on. These

electronic devices become widely used in world. Because of this, increment of power

consumption becomes a problem. This problem is caused by Dynamic Random Access

Memory (DRAM) and Static Random Access Memory (SRAM). These are volatile memory, so

they cost power on a continuous basis. Therefore, non-volatile memory is needed to research

actively for replacing with volatile memory. Flash memory dominates the market of non-volatile

memories, whose share of the market is above 90%. It gained high-capacity storage by

integration. However, flash memory have mortiferous demerit for replacement to volatile

memory. Comparison on several parameters of DRAM, SRAM and flash memory are shown in

Table 1.1.

Table 1.1 Comparison of DRAM, SRAM and Flash memory on speed, endurance and voltage[1]

1.811.8Read Operation Voltage (V)

1212.5Write Operation Voltage (V)

104>1016>1016Endurance

10 yearsVoltage dependent64 msRetention Time

0.1 ms0.2 ns<10 nsRead Time

0.1 ms0.2 ns<10 nsErase Time

1 ms0.2 ns<10 nsWrite Time

Flash memorySRAMDRAM

1.811.8Read Operation Voltage (V)

1212.5Write Operation Voltage (V)

104>1016>1016Endurance

10 yearsVoltage dependent64 msRetention Time

0.1 ms0.2 ns<10 nsRead Time

0.1 ms0.2 ns<10 nsErase Time

1 ms0.2 ns<10 nsWrite Time

Flash memorySRAMDRAM

Operation speed and cycle of flash memory is inferior in comparison with those of DRAM,

SRAM. It is caused by operation mechanism of flash memory. Flash memory is based on the

traditional floating gate concept, has encountered serious technical challenges due to its floating

gate structure. Schematically of principle for Flash memory is shown in Fig. 1.2.


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Figure 1.2 Flash memory and its floating gate structure

By storage different amount of electrons into the floating gate, the MOSFET devices shows

different threshold voltage, which can represents different states. The problem of this structure

comes from trade-offs between the high speed, low power operation and long time retention:

high speed and low power requires a small capacitance between the floating gate and the

channel, which long retention time requires a large capacitance. And low operation cycle is

caused by dielectric breakdown come from inducing of electron to floating gate. Therefore,

emerging non-volatile memories have to been researched additionally.


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1.2 Introduction of emerging research non-volatile memory Under this circumstance, several non-volatile memories based on different concepts have

aroused extensive attention from both of industry field and academic field, such as Ferroelectric

Random Access Memory (FeRAM), Magnetoresistive Random Access Memory (MRAM),

Phase change RAM (PCRAM) and Resistive RAM (ReRAM).

·FeRAM

FeRAM use polarization to check on-off state. Dielectric capacitor was applied voltage for

polarization. After that, on-off state was checked by changing of current caused by polarization

inversion with applied pulse voltage. Structure of PCRAM is structure of DRAM whose

paraelectrics change to ferroelectric.

·MRAM

MRAM use changing of magnetization to check on-off state. MRAM is constructed by two

ferromagnetic layers and insulator in halfway between two layers. This structure named

magnetic tunnel junction (MTJ). Magnetization of fellow ferromagnetic layer is fixation, and

magnetization of another ferromagnetic layer is variability. Resistance is high when two

magnetization face same direction, and resistance is low when two magnetization face different

direction (giant magneto resistive effect or tunnel magneto resistance effect). Therefore,

changing of current is happened when magnetization is inverted. On-off state was checked by

changing of current. Structure of FeRAM is structure of DRAM whose paraelectrics change to

MTJ. MRAM that resistance changing caused by induced spin-electron is eagerly researched

recently.


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·PCRAM

PCRAM use difference of resistance between crystal phase and amorphous phase. Crystal phase

shows high resistance and amorphous phase shows low resistance. Crystal changes to

amorphous when it is heated and quench. In contrast, amorphous changes to crystal when it is

heated and cold removal. On-off state was checked by changing of current. Structure of

PCRAM is structure of DRAM whose paraelectrics change to phase change layer.

·ReRAM

ReRAM use changes of resistance with insulator. Resistance of insulator changes high and low

when device was applied voltage. On-off state was checked by changing of current. Structure of

ReRAM is simple capacitor.

The comparison on several parameters of FeRAM, MRAM, PCRAM, and ReRAM are shown

in Table 1.3. Compared with other types, ReRAM shows relatively high speed, simple structure

and high resistance ratio.

Table 1.3 Comparison of FeRAM, MRAM, PCRAM and ReRAM on speed, endurance,

resistance ratio and operation voltage[2-8]

0.531.81.3-3.3Erase Operation Voltage (V)

1.431.81.3-3.3Write Operation Voltage (V)

10510310104Resistance ratio

106109>10121014Endurance

301003565Erase Time (ns)

101003565Write Time (ns)

ReRAMPCRAMMRAMFeRAM

0.531.81.3-3.3Erase Operation Voltage (V)

1.431.81.3-3.3Write Operation Voltage (V)

10510310104Resistance ratio

106109>10121014Endurance

301003565Erase Time (ns)

101003565Write Time (ns)

ReRAMPCRAMMRAMFeRAM


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1.3 Introduction of Resistive random access memory

(ReRAM)

1.3.1 General introduction of ReRAM device

Resistive switching Random Access Memory (ReRAM) is a kind of memory that utilizing

electric field induced resistance change in certain kinds of materials. It was proposed by Prof.

Ignatiev from University of Houston in 2000, they developed a new method technology by

utilizing the changeable resistance of PrXCa1-XMnO3 under pulses with different polarity[9]. The

basic working principle of ReRAM is shown in Fig. 1.4. The device is able to be abruptly

switched between high resistance state (HRS) and low resistance state (LRS) by applying write

voltage or ease voltage. HRS represents off state while LRS represents on state. In additional,

the write voltage and the erase voltage do not need to continually turn on to keep the HRS or

LRS. In other words, resistive switching is a kind of non-volatile memory effect.

ON StateOFF State

MetalMetal

HighResistance

HighResistance

MetalMetal

MetalMetal

LowResistance

LowResistance

MetalMetal

Write voltageSet process

Erase voltageReset process

Figure 1.4 The basic principle of ReRAM


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Nowadays, ReRAM aroused more and more attention as a promising candidate for next

generation of non-volatile memory. Here, we summary main advantages of ReRAM:

·ReRAM is completely compatible with current CMOS technology, which indicates that it is not

necessary of great investment of new processes.

·ReRAM can be operated under very small power consumption. In the 0.18um process, the

operation current can be controlled at the orders of 10-6A.

·ReRAM can high speeds operate to changing resistance state.

·ReRAM has simple capacitor structure with two terminals, which is easy to be integrated to

VLSI circuits.

Although numbers of switching behaviors are reported, resistive switching

mechanism has not been clarified yet. Moreover, ReRAM still facing challenge to

practical application. The key problem is resistance ratio. Sneak current happed in circuits and

make bungle for operation when ReRAM is high integrated[10]. Therefore, additional research

and large resistance ratio are need for development of electronics and practical realization.

1.3.2 Structures and operation of ReRAM device

The structure of single cell and arrays of ReRAM are shown in Fig. 1.5.

(a) (b)

Figure 1.4 The structure of single cell and arrays of ReRAM[11]


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Fig. 1.4 (a) shows the structure of a single ReRAM cells. It has a very simple capacitor-like

structure, in which an insulating or semiconducting oxide is sandwiched between two metal

electrodes. Fig. 1.4 (b) shows a possible “cross-point” array for organizing ReRAM cells. Word

and bit lines are used for selecting a memory cell and writing or reading data, respectively.

Cross-point array is a two dimensional structure, which is relatively simple and requires less

fabricating process. What’s more, cross-point array is able to achieve a very high storage density.

The storage density is determined by the pinch of fabricating process. The definition of pinch of

cross-points array is shown in Fig. 1.6.

Fig. 1.6 The definition of Pinch in cross-points array

The resistance switching behaviors of ReRAM devices can be divided to two basic types

according to their I-V characteristics under sweeping voltage. It should be note that these two

I-V curves just show typical characteristics of the two different types, it can varies according to

specific system. Besides, the dashed lines in the figure show the compliance current (C.C.),

which results in the difference between control voltage and real voltage in system. Fig. 1.7 (a)

shows unipolar switching behaviors, in which the reset and set voltage is not dependent on the


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polarity of voltage. The set voltage is always higher than the reset voltage, and the reset current

is always higher than the CC during set operation. Fig. 1.7 (b) shows bipolar switching behavior,

in which the set and reset processes happen in the opposite voltage polarity. In some bipolar

systems, CC is even not necessary.

Figure 1.7 Resistance switching behaviors of unipolar and bipolar[12]

1.3.3 Resistive switching mechanism in ReRAM

Although resistance switching behaviors have been found in a wide range of materials, and lots

of models are proposed to explain those phenomenons, there are still lots of unclear places in the

switching mechanisms. Generally, the resistance switching mechanism can be divided to two

types in terms of position. They are interface effect, bulk effect.

·Interface effect

It has been certificated that in some ReRAM system, such as the contact of Pt electrode and

SrTiO3[13], the change of schottky barrier should be responsible for the resistance switching

phenomenon. The elimination and generation of oxygen vacancies leads to the change of

schottky barrier and thus change the tunneling current. For example, in the case shown in Fig.


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1.8, under the effect of negative voltage, the electrons combine with the oxygen vacancies at the

interface. This process results in a wider schottky barrier and thus a smaller tunneling current,

which corresponds to the HRS. On the contrary, when the positive voltage is applied, opposite

process happens and leads to the LRS.

Figure 1.8 The schematic illustration of resistance switching caused by Schottky effect

·Bulk effect

Bulk effect also play significant role in many kinds of oxides. Among several bulk mechanisms,

conductive filaments (CF) are the most existed bulk effect that is responsible for resistive

switching. Schematic illustration of resistive switching based on the motion of oxygen vacancies

is shown in Fig.1.9. Oxygen ion migrates to cathode and makes oxygen vacancy in insulator

when device was applied plus voltage. Finally, the dendrites made by vacancies oxygen grow to

filaments that connect the electrodes, which set the device to ON state. Upon reversal of polarity

of the applied voltage, and electrochemical dissolution of the filaments takes place, resetting the

system into the OFF state.


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Figure 1.9 Schematic illustration of resistive switching based on the motion of

oxygen vacancies and the formation of conduct filament

Recently reports of ReRAM are shown in Fig. 1.10.

1T-1R1T-1R1T-1R1R1T-1R1S-1R1R1T-1R1T-1R1RStructure

Oxigenmigration

Oxigenmigration

Oxygenvacanciesfilaments


Frenkel-Poole

emission

Metalfirament

spacechargelimitedcurrent

Oxigenmigration

-Schottkycurrent

transport

Resistanceswitching

mechanism

----free---freefreeForming

>102>102->10102103101050>103Resistance ratio

>1012105-104105106>1061061010-Endurance

710

2.510

-410

-105×107

-0.8-4100

-1.250

-2.510

-1.540

1.5Reset Voltage(V)speed (ns)

-4.510

3.610

310

155×107

2.24100

1.850

2.510

1.440

2.5Set Voltage(V)Speed (ns)

bipolarunipolarbipolarbipolarbipolarbipolarbipolarbipolarbipolarunipolar/bipolar

Type

400×Πnm236nm21μm21600nm2-1300nm27850μm2Cell area

Pt/PtRu/RuTiN/TiNCNT/CNTAl/-Ni/PtTiN/WTiN/-Ti/-Ni/p+-SiTE/BE

Ta2O3/TaOx

Ta2O5/TiO2

(10)

TiO2/Al2O3

AlOxNitrogen-

Doped AlOx (15)

HfO2

(80)WOxTa/

Ta2O3

HfOx

(3)HfOx

(4)Insulator

(nm)

Samsung(Korea)

Renesas(Japan)

Hynix(Korea)

Stanford(USA)

Stanford(USA)

NCTU(Taiwan)

Macronix(Taiwan)

Samsung(Korea)

ITRI(Taiwan)

NTU(Singapore)

1T-1R1T-1R1T-1R1R1T-1R1S-1R1R1T-1R1T-1R1RStructure

Oxigenmigration

Oxigenmigration



Frenkel-Poole

emission

Metalfirament

spacechargelimitedcurrent

Oxigenmigration

-Schottkycurrent

transport

Resistanceswitching

mechanism

----free---freefreeForming

>102>102->10102103101050>103Resistance ratio

>1012105-104105106>1061061010-Endurance

710

2.510

-410

-105×107

-0.8-4100

-1.250

-2.510

-1.540

1.5Reset Voltage(V)speed (ns)

-4.510

3.610

310

155×107

2.24100

1.850

2.510

1.440

2.5Set Voltage(V)Speed (ns)

bipolarunipolarbipolarbipolarbipolarbipolarbipolarbipolarbipolarunipolar/bipolar

Type

400×Πnm236nm21μm21600nm2-1300nm27850μm2Cell area

Pt/PtRu/RuTiN/TiNCNT/CNTAl/-Ni/PtTiN/WTiN/-Ti/-Ni/p+-SiTE/BE

Ta2O3/TaOx

Ta2O5/TiO2

(10)

TiO2/Al2O3

AlOxNitrogen-

Doped AlOx (15)

HfO2

(80)WOxTa/

Ta2O3

HfOx

(3)HfOx

(4)Insulator

(nm)

Samsung(Korea)

Renesas(Japan)

Hynix(Korea)

Stanford(USA)

Stanford(USA)

NCTU(Taiwan)

Macronix(Taiwan)

Samsung(Korea)

ITRI(Taiwan)

NTU(Singapore)

Figure 1.10 Examples of metal oxide ReRAM device characteristics[14-23].


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1.4 Introduction of Ce oxide as buffer layer for ReRAM Although many reports deal with transition oxides for filament-based switching behaviors, the

resistance change between on- and off-states is typically 100 or below and is dependent on the

initial soft dielectric breakdown, referred as forming process[24]. Among reported transition oxides,

Ce oxides are known to present valence number fluctuation and to have high oxygen ion

conductivity, therefore they are expected to have potentials for resistive switching devices[25, 26].

1.5 Purpose of this study Purpose of this study is ascertaining of operation mechanism and achieving large resistance ratio

for ReRAM. Whence, Ce oxide was used as insulator by its attribute. Moreover, guideline of

choice for bringing out potential of ReRAM is indicated.

1.6 Configuration of this thesis In chapter 3, influence of bottom electrode for ReRAM was researched. Whence, bottom

electrode with Si shows large resistance ratio was confirmed.

In chapter 4, resistance switching mechanism of W/CeOx/NiSi2 structure ReRAM was

explained. Moreover, guideline of choice for insulator is indicated.

In chapter 5, reset process of W/CeOx/NiSi2 structure ReRAM was explained. Whence, two

reactions existing in local anodic oxidation is investigated.

Finally, chapter 6 summarizes this study.

Fig. 1.11 shows the contents of this thesis. This thesis is consisted of 6 parts.


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Chapter 1Introduction

Chapter 2Fabrication and characterization

Chapter 3Influence of bottom electrode for ReRAM

Chapter 6Conclusion

Chapter 4Operation mechanism

for W/CeOx/NiSi2 structure ReRAMand guideline of selection

for buffer layer

Chapter 5Transient responsefor reset process

Figure 1.11 Configuration of this thesis


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Reference

[1] 2011 ITRS

[2] K. Takahashi, K. Aizawa, B. Park, H. Ishihara, “Thirty-Day-Long Data Retention in

Ferroelectric-Gate Field-Effect Transistors with HfO2 Buffer Layers”, J. J. Appl. Phys., 44, 8, pp.

6218 (2005).

[3] D. Takashima, H. Shiga, D. Hashimoto, T. Miyakawa, S. Shirataka, K. Hoya, R. Ogiwara, R.

Takizawa, S. Doumae, R. Fukuda, Y. Watanabe, S. Fujii, T. Ozaki, H. Kanaya, S. Shuto, K.

Yamakawa, I. Kunishima, T. Hamamoto, A. Nitayama, “A Scalable Shield-Bitline-Overdrive

Technique for Sub-1.5 V Chain FeRAMs”, IEEE J. Solid-State Circuits, 46, 9 (2011).

[4] Y. Wang, S. Huang, D. Wang, K. Shen, C. Chien, K. kuo, S. Yang, D. Deng, “Impact of Stray

Field on the Switching Properties of Perpendicular MTJ for Scaled MRAM”, IEDM, pp. 672

(2012).

[5] T. Kawahara, “Challenges toward gigabit-scale spin-transfer torque random access memory

and beyond for normally off, green information technology infrastructure (invited)”, J. Appl.

Phys., 109, 07D325 (2011).

[6] A. L. Lacaita, A. Redaelli, D. Lelmini, F. Pellizzer, A. Pirovano, A. Benvenuti, R. Bez,

“Electrothermal and phase-change dynamics in chalcogenide-based memories”, IEDM, pp. 914

(2004).

[7] G. D. Sandre, L. Bettini, A. Pirola, L. Marmonier, M. Pasotti, M. Borghi, P. Gastaldi, G.

Mastracchio, “A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm

Standard CMOS Technology ”, J. J. Appl. Phys., 46, 1 (2011).

[8] X. A. Tran, B. Gao, J. F. Kang, L. Wu, Z. R. Wang, Z. Fang, K. L. Pey, Y. C. Du, B. Y.

Nuguyen, M. F. Li, H. Y. Yu, “High Performance Unipolar AlOy/HfOx/Ni based RRAM

Compatible with Si Diodes for 3D Application”, VLSI, 44 (2011).


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[9] S.Q. Liu, N. J. Wu, A. Ignatiev, “Electric-pulse-induced reversible resistance change effect in

magnetoresistive films”, Appl. Phys. Lett., 76, pp. 2749 (2000).

[10] E. Linn, R. Rosezin, C. Kugeler, R. Waser, “Complementary resistive switches for passive

nanocrossbar mem”, Nat. Mater., 9, pp. 406 (2010).

[11] R.Waser, M. Aono, “Nanoionics-based resistive switching memories”, Nat. Mater., 6, pp.

833 (2007).

[12] A. Sawa, “Resistive switching in transition metal oxides”, materialstoday, 11, pp. 6 (2008).

[13] A. Sawa, T. Fuji, M. Kawasaki, Y. Tokure, “Hysteretic current-voltage characteristics and

resistance switching at a rectifying Ti/Pr0.7Ca0.3MnO3 interface”. Appl. Phys. Lett., 85, pp.

4073 (2004).

[14] X. A. Tran, B. Gao, J. F. Kang, X. Wu1 , L. Wu, Z. Fang, Z. R. Wang, K. L. Pey, Y. C.

Yeo, A. Y. Du, M. Liu, B. Y. Nguyen, M. F. Li, H. Y. Yu, “Self-Rectifying and Forming-Free

Unipolar HfOx based-High Performance RRAM Built by Fab-Avaialbe Materials”, IEDM, pp.

713 (2011).

[15] Y. S. Chen, H. Y. Lee, P. S. Chen, C. H. Tsai, P. Y. Gu, T. Y. Wu, K. H. Tsai, S. S. Sheu,

W. P. Lin, C. H. Lin, P. F. Chiu, W. S. Chen, F. T. Chen, C. Lien, M. J. Tsai, “Challenges and

Opportunities for HfOX Based Resistive Random Access Memory”, IEDM, pp. 717 (2011).

[16] I. G. Baek, C. J. Park, H. Ju, D. J. Seong, H. S. Ahn, J. H. Kim, M. K. Yang, S. H. Song, E.

M. Kim, S. O. Park, C. H. Park, C. W. Song, G. T. Jeong, S. Choi, H. K. Kang, C. Chung,

“Realization of Vertical Resistive Memory (VRRAM) using cost effective 3D Process”, IEDM,

pp. 737 (2011).

[17] W. Chien, M. Lee, F. Lee, Y. Lin, H. Lung, K. Hsieh, C. Lu, “A Multi-Level 40nm WOX

Resistive Memory with Excellent Reliability”, IEDM, pp. 728 (2011).

[18] J. Huang, Y. Tseng, W. Luo, C. Hsu, T. Hou, “One Selector-One Resistor (1S1R) Crossbar

Array for High-density Flexible Memory Applications”, IEDM, pp. 733 (2011).


-19-

[19] W. Kim, S. Il Park, Z. Zhang, Y. Yang-Liauw, D. Sekar, H. P. Wong, S. S. Wong,

“Forming-Free Nitrogen-Doped AlOX RRAM with Sub-mA Programming Current”, VlSI, pp.

22 (2011).

[20] Y. Wu, Y. Chai, H. Chen, S. Yu, H. P. Wong, “Resistive Switching AlOx-Based Memory

with CNT Electrode for Ultra-Low Switching Current and High Density Memory Application”,

VlSI, pp. 26 (2011).

[21] J. Yi, H. Choi, S. Lee, J. Lee, D. Son, S. Lee, S. Hwang, S. Song, J. Park, S. Kim, W. Kim,

J. Kim, S. Lee, J. Moon, J. You, M. Joo, J. Roh, S. Park, S. Chung, J. Lee, S. Hong, “Highly

Reliable and Fast Nonvolatile Hybrid Switching ReRAM Memory Using Thin Al2O3

Demonstrated at 54nm memory Array”, VlSI, pp. 48 (2011).

[22] M. Terai, M. Saitoh, T. Nagumo, Y. Sakotsubo, Y. Yabe, K. Takeda, T. Hase, “High Thermal

Robust ReRAM with a New Method for Suppressing Read Disturb”, VlSI, pp. 50 (2011).

[23] Y. Kim, S. Lee, D. Lee, C. Lee, M. Chang, J. Hur, M., Lee, G. Park, C. Kim, U. Chung, I.

Yoo, K. Kim, “Bi-layered RRAM with Unlimited Endurance and Extremely Uniform

Switching”, VlSI, pp. 52 (2011).

[24] Q. Liu, S. long, W. Wang, Q. Zuo, S. Zhang, J. Chen, M. Liu, “Improvement of Resistive

Switching Properties in ZrO2-Based ReRAM With Implanted Ti Ions”, IEEE Electron Device

Lett., 30, pp. 12, (2009).

[25] D. J. M. Bevan, J. Kordis, J. Inorg. Nucl. Chem,“ MIXED OXIDES OF THE TYPE MO2

(FLUORITE)-M203--I OXYGEN DISSOCIATION PRESSURES AND PHASE

RELATIONSHIPS IN THE SYSTEM CeO2-Ce2Oa AT HIGH TEMPERATURES“, 26, pp.

1509-1523 (1964).

[26] M. Mogensen, N. M. Sammes, G. A. Tompsett, “Physical, chemical and electrochemical

properties of pure and doped ceria”, Solid State Ionics, 129, pp. 63 (2000).

-Chapter 2 Fabrication and Characterization-

-20-

Chapter 2

Fabrication and Characterization

2.1 Device fabrication process

2.2 Detailed process

2.2.1 Si surface cleaning

2.2.2 Thermal oxidation process

2.2.3 Photolithograph

2.2.4 Etching process

2.2.5 E-beam evaporation

2.2.6 RF magnetron sputtering

2.2.7 Rapid thermal annealing

2.2.8 Thermal evaporation

2.3 Characterization

2.3.1 Current-voltage measurement

2.3.2 Pulse measurement

In this chapter, all of the fabricating and characterization methods that have been utilized in

studies are introduced. The principles of processes and equipments are simply discussed and the

experiment conditions are also listed.


-21-

2.1 Device fabrication process A 200nm SiO2 was formed on p+-Si Substrate by thermal oxidation. The substrate impurity

concentration is 1018cm-3. The SiO2 layer was lithographically patterned by wet etching to

electrically contact the bottom metal electrodes to the substrate. Either W, Ti, Ni, TiN or NiSi2

layer with a thickness of 15nm was deposited on the SiO2 layer as bottom electrode by RF

sputtering. The TiN film in this work was produced by reactive sputtering: N2 gas was also

introduced into the chamber in this case and reacts with Ti target to form Nitride films. Besides,

NiSi2 was formed by stack of Ni (0.5nm) and Si (1.9nm). 14.4nm-thickn NiSi2 was gained by

rolling 6cycle of Ni/Si stack.(Fig. 2.1) And for NiSi2 formation, the sample was annealed in

nitrogen ambience for 1 minute at 500ºC to promote the reaction of Ni and Si atoms and

guttering Ar.(Fig. 2.2) Then, a CeOx layer was deposited by e-beam evaporation at 300ºC,

followed by in situ 50nm-thick tungsten deposition by RF sputtering as a top electrode. The top

electrode was then patterned by reactive ion etching (RIE) with SF6 chemistry. The areas of the

electrodes were designed to be 20×20m2. Finally, an Al layer was deposited for backside

contact. Fabrication process and the device structure are summarized in Fig. 2.3.

SiNi

SiNi

1.9 nm0.5 nm

6 cycle

Figure 2.1 Ni/Si stacked-structure


-22-

Figure 2.2 Formation of NiSi2 by 500oC annealing

AlP+-Si sub

SiO2

NiSi2…..etc

CeOx

W

20μm

Metal etching

Backside contact formation (Al)

SiO2 etching

Annealing at 500ºC for 1min (N2)

p+-Si substrate (Impurity concentration:1018)

Measurement

SPM&HF Cleaning

Oxidation

Metal (W, Ti, Ni, TN or NiSi2) deposition

CeOx evaporation at 300ºC

Metal (W) deposition

Figure 2.3 Fabrication process of CeOx based ReRAM


-23-

2.2 Detailed process

2.2.1 Si surface cleaning

Si wafer cleaning is critically important in the era of VLSI and ULSI technology. Over 50% of

yield losses in integrated circuit fabrication are generally accepted to be due to micro

contamination, such as metal contamination, organic contamination, ionic contamination, and

etc. The cleaning process for wafers used in this studies starts from rinsing Si wafers with

running DI (de-ionized) water. The DI water used in this work, incidentally, has a resistance high

than 18.2Mcm, while the theoretical resistance of pure water is 18.25Mcm at 25oC. Then the

samples were treated by sulfuric-peroxide mixture (SPM), which is composed by H2O2 and

H2SO4 (H2O2: H2SO4 = 1:4), for 10min at 120oC. During this process, existed organic and

metallic contamination was separated from surfaces of Si wafers because of chemical oxidation

of the surfaces. After that, Si wafers was rinsed with running DI water again. In order to remove

the chemical oxide formed in SPM process, the wafers are further treat by diluted HF (1%HF)

for 1min. Finally, wafers are cleaned again by running DI wafer before next fabrication process.

2.2.2 Thermal Oxidation Process

Thermal oxidation is one of key processes in VLSI technology. In the case of silicon dioxide, it

can be classified to two types: wet oxidation (Si + 2H2O = SiO2 + 2H2, 800oC-1100oC) and dry

oxidation ( Si + O2 = 2SiO2, 800oC-1100oC). Wet oxidation is suitable for growth of thick silicon

dioxide because of its relatively high growth rate, while dry oxidation is rather slow but easily

controllable. In this work, a layer of SiO2 (about 200nm) is grown on a Si wafer by dry

oxidation in an oxidation furnace, whose structure is shown in Fig.2.4. One of critical challenges

in thermal oxidation is creation a gas ambient with precise, constant and uniform temperature.

By utilizing three heaters in different part of the quartz tube, the temperature becomes more


-24-

uniform in the whole tube. In addition, only a small localized region in the middle of tube is used

for thermal oxidation, which further improves the uniformity of the temperature and the mass

flow. The samples are set on a small quartz boat and slowly send into the middle of the tube by a

quartz rod. The mass flow of O2 is controlled to be 1L/min and the oxidation is continued for

2hours at 1000oC.

Fig. 2.4 Schematic illustration of the oxidation furnace

2.2.3 Photolithograph

In order to fabricate desired device used for this study, the photolithograph process is utilized for

two times: One time for patterning the window between the bottom electrode and the substrate,

and the other for pattering the top electrode layer to square-shape with different area. First of all,

a uniform thin layer of positive photoresist was formed by high speed spin coating. Then the

wafer was heated to 115oC to drive off excess moisture in the photoresist, which is so called

pre-baking prcess. Next, the wafer coated by photoresist was aligned and exposed through

e-beam patterned hard-mask with high-intensity ultraviolet (UV) light at 405nm wave length.

MJB3 of Karl Suss contact-type mask aligner was used in this process. The exposure duration

was set to 4.8s. After that, developing process is performed by a specified developer called


-25-

NMD-3 (Tokyo Ohka Co. Ltd.) for 2min. Finally, the resulting sample was treated by

post-baking process to solidify the remaining photoresist for the following wet chemical etching

and plasma etching.

2.2.4 Etching process

Reactive ion etching (RIE) and buffered HF (BHF) etching are both adopted for etching process

in this work. RIE is a widely used dry etching technology, whose basic working principle is

shown in Fig. 2.5. Etching gas is introduced into a low pressure chamber and then plasma is

produce by a strong RF (radio frequency) electromagnetic field. In each cycle of the filed,

electrons are accelerated to high velocity by the electric field because of its neglectable mass,

while the velocity of positive ions are very slow as their far larger mass. As a result, by applying

a RF electric field, electrons strike both of the upper plate and the bottom plate of the chamber,

while the positive ions are concentrated between the plates. The upper plated is grounded and

stroked electrons flow away. However, electrons build up negative charges on the wafers

because of their insulating characteristic. Consequently, a strong local electric filed is established

between the positive etching ions and the negative wafers. The ions bombard the sample and

chemically react with certain kind of material, which results in etching selected part of the

sample. Furthermore, physical sputtering of the sample surface also happens during this process.

Because of the vertical electric field, RIE shows anisotropic etching profile. In this work, SF6

was used to etching the W electrode layer and O2 was used to remove the photoresist from the

etched wafer. On the other hand, BHF is also adopted for wet etching of silicon dioxide over

silicon wafers, which is an isotropic etching process. BHF is composed by HF, NH4F and H2O,

and it can etching silicon dioxide in a controlled speed (100nm/min for BHF used in this work).


-26-

～ Plasma

Substrate

～～～ Plasma

Substrate

Fig. 2.6 Schematic illustration of Reactive ion etching

2.2.5 E-beam evaporation

E-beam evaporation is used extensively in the semiconductor industry to deposit thin films of a

large amount of materials in VLSI technology whose basic working principle is shown in Fig.

2.6. E-beam evaporation is employed for depositing CeOx thin film in this work. Evaporation is

carried out at chamber in ultra high vacuum state (10-7~10-8Torr). The sample is heated to 300oC

and rotated at a constant speed in advance. Electron beam, which is accelerated by a 5KV

electric field, is generated and bombard to the source under the control of a magnetic sweep

controller. Consequently, electrons flow though the source and the molecules evaporate because

of Joule heat. The growth of the thin film is observed by a thickness monitor and the growth rate

in this work is controlled at 0.002- 0.006A/s to ensure a relatively high film quality.


-27-

Fig. 2.6 Schematically illustration of E-beam Chamber

2.2.6 RF magnetron sputtering

RF magnetron sputtering is also adopted for depositing the electrode (W, Ti, Ni, TiN and NiSi2)

whose basic working principle is shown in Fig. 2.7. An RF with 13.56MHz at a power of 150W

is applied between substrate side and target side. Because of the difference of mass, Ar ions and

electrons are separated. A magnet is set underneath the target, so that the plasma damage is

minimized. Electrons run through the circuit from substrate side to target side, because substrate

side is subjected to be conductive and target side is subjected to be insulated. Then, target side is

negatively biased and Ar ions hit the target.

shutter

W

substrate

PlasmaAr+Ar+

W

WWW

Figure 2.7 Schematic illustration of RF magnetron sputtering.


-28-

2.2.7 Rapid Thermal Annealing

Rapid thermal annealing (RTA) stands for a kind of thermal treatment that heats samples to high

temperatures in a short time, which in the orders of seconds. And usually, a slow cooling down

process is followed for protect the sample from break due to abrupt temperature change. It can

be used for re-crystallization, activation of dopants, diffusion of ions between different film,

recovery of damage and defects, and formation of new chemical substance. Besides, the high

temperature ramp rate is usually achieved by lamp or laser, and the annealing ambient is usually

N2 or O2. The equipment of QHC-P610CP (ULVAC RIKO Co. Ltd) is utilized, whose structure

is shown in Fig. 2.8. Samples are heated by an infrared lamp system and cooling down by

flowing water.

Fig. 2.8 Schematic illustration of the infrared annealing furnace


-29-

2.2.8 Thermal evaporation

Aluminum (Al) is evaporated to the backside of the samples in this work for the better contact of

the substrates and the ground during measurement, which is achieved by using bell-jar type

thermal evaporation as illustrates in Fig. 2.9. This system utilized a turbo molecular pump

(TMP) to achieve background pressure up to 1.0×10-5Pa prior to Al evaporation .Filament which

used to hold Al wires is made of tungsten (W). Purity of W filament and Al source is 99.999%.

Methanol and acetone were used to clean the W filament and Al wires prior to every evaporation

process. Chamber pressure during evaporation is 2.0-5.0×10-5Pa. A DC current about 60A was

used to evaporate Al.

Fig. 2.9 Schematic illustration of the structure of Bell Jar


-30-

2.3 Characterization

2.3.1 Current-voltage measurement

I-V measurements were done on HP4156A semiconductor parameter analyzer. In order to

tracing the resistance switching behaviors, a sweep voltage ranging for -10V to 10V, whose step

is 0.05 V, is used. Besides, different compliance current ranging from 10A to 5mA is also set to

protect the device from break down. In addition, in order to investigate the conduction

mechanism of different conduction state, I-V measurement in different temperature is also

carried out.

2.3.2 Pulse measurement

Measurement method is show at Fig. 2.10. Current is measured at measurement point when

device is applied pulse. Operation cycle and detailed of reset process was used by applied pulse

measurement.

Fig. 2.10 Measurement method of applied pulse

-Chapter 3 Influence of bottom electrode for ReRAM-

-31-

Chapter 3

Influence of bottom electrode for ReRAM

3.1 Operation of CeOx ReRAM with W, Ti and Ni bottom electrode

3.2 Operation of CeOx ReRAM with TiN bottom electrode

3.3 Operation of CeOx ReRAM with p+-Si bottom electrode

3.3.1 Characteristics of W/CeOx/p+-Si ReRAM

3.3.2 Control of SiO2 formed between CeOx/p+-Si interface

3.4 Operation of CeOx ReRAM with NiSi2 bottom electrode

3.4.1 Characteristics of W/CeOx/NiSi2 ReRAM

3.4.2 Control of SiO2 formed between CeOx/NiSi2 interface

3.4.3 Temperature resistance of W/CeOx/NiSi2 ReRAM

3.5 Conclusion

Reference

Although numbers of switching behaviors are reported for ReRAM, resistive switching

mechanism has not been clarified yet. And, characteristics of ReRAM dependents on materials

that were combined. In this chapter, the influence of bottom electrode materials on the switching

characteristics of CeOx was investigated[1-2].


-32-

3.1 Operation of CeOx based ReRAM with W, Ti and Ni

bottom electrode The resistive switching characteristics with W, Ti and Ni bottom electrodes are shown in Fig. 3.1.

CeOx thickness was set 13nm. After the first voltage sweep, referred as initial, the voltage was

swept to different polarity to achieve a reset process, then again the voltage was swept back to

obtain set process. The switching behavior exhibited a bipolar type behavior in each case, and

was in good agreement with previous reports, however, different current voltage characteristics

were obtained for the different electrode materials. Resistance switching characteristics with Ni

bottom electrode showed a switching behavior with a symmetric shape and the current followed

the initial characteristics, achieving a forming-free resistive switching device. On the contrary,

the resistance switching characteristics with W or Ti bottom electrode showed asymmetric

properties. Resistance change only could be look at the reset process, although set process was

also essential. Resistance switching characteristics with W, Ti and Ni showed stability behavior.

However, their on and off ratio are almost or below 102. This is because their switching

properties weren’t caused by changing of Ce oxide but by changing oxide depended on bottom

electrode that formed between CeOx/bottom electrode interfaces. It formed when evaporation of

CeOx.


-33-

Cu

rren

t(A

)Compliance Current:1mA

● Initial◆ Reset

Process▲ Set

Process10-12

10-10

10-8

10-6

10-4

10-2

0-5 5-10Voltage (V)

10

W

CeOx

W

(a)

10-12

10-10

10-8

10-6

10-4

10-2Compliance Current:0.75mA


Process▲ Set

Process0-5 5-10

Voltage (V)10

Cu

rren

t(A

)

W

CeOx

Ti

(b)


-34-

10-12

10-10

10-8

10-6

10-4

10-2

Cu

rren

t(A

)

0-5 5-10Voltage (V)

10


Process▲ Set

Process

W

CeOx

Ni

(c)

Figure 3.1 Bipolar resistance switching characteristics of (a)W/CeOx/W (b)W/CeOx/Ti

(c)W/CeOx/Ni structure ReRAM

Resistance switching mechanism of W/CeOx/W, Ti and Ni structure ReRAM is caused by

change of state of oxide depended on bottom electrode. When device was applied plus voltage,

oxygen migration and generation of oxygen vacancy is happen. And it make to formation of

conductive filament in metal oxide film. For this, resistance changes small. After that,

conductive filament disappears by applied reverse voltage to device, and resistance changes

large.(Fig. 3.2) Oxide film formed between CeOx/bottom electrode is thin and low quality.

Therefore, it is considered that low resistance ratio was gained.

W

CeOx

MetalOxide

Metal

Resistanceswitching

layer

Conductive filament

Figure 3.2 Resistance switching mechanism of W/CeOx/W, Ti, and Ni structure ReRAM[3-6]


-35-

3.2 Operation of CeOx ReRAM with TiN bottom electrode The resistive switching characteristics with TiN bottom electrode is shown in Fig. 3.3. CeOx

thickness was set 13nm. After the first voltage sweep, referred as initial, the voltage was swept to

different polarity to achieve a reset process, it same with ReRAM which using W, Ti and Ni as a

bottom electrode. And, operation voltage is about 2.5V that lower than ReRAM which using W,

Ti and Ni as a bottom electrode. Moreover resistance ratio (<103) is larger than those values. But

ReRAM with TiN bottom electrode need large voltage in initial sweep as compared set process.

And I-V sweep shape considerably different compared with using W, Ti and Ni bottom

electrode. It was considered that resistance switching differ with using W, Ti and Ni bottom

electrode.

10-8

10-6

10-4

10-2

Cu

rren

t(A

)

0-3 6Voltage (V)

3

TiN

CeOx

W● Initial◆ Reset

Process▲ Set

Process

Compliance Current:2mA

Figure 3.3 Bipolar resistance switching characteristics of W/CeOx/TiN structure ReRAM

Therefore, W/CeOx/TiN structure ReRAM has been conduct researched for studying to clear the

reason using Transmission Electron Microscope (TEM). TEM image of W/CeOx/TiN structure

ReRAM was showed in Fig. 3.4.


-36-

SiO2

TiN

CeOx

W

TiO2

Figure 3.4 TEM image of W/CeOx/TiN structure ReRAM

Interface layer has been confirmed between CeOx and TiN by TEM measurement. The interface

layer is high quality TiO2 film as compared with using Ti as a bottom electrode by nitrogen

effect. It formed when evaporation of CeOx. Nitrogen enhances oxidation to TIO2 by oxygen in

CeOx. Dielectric constant of TiO2 is larger than that of CeOx. For, this, conductive filament don’t

form in TiO2 but in CeOx because electric field applied nearly CeOx when device was applied

voltage. Therefore, resistance changes small. After that, conductive filament disappears by

applied reverse voltage to device, and resistance changes large.(Fig. 3.5) Difference of resistance

switching behave is caused by difference of position of conductive filament form.

TiN

TiO2

W

CeOx

Vo2+

:Oxygen vacancy

Conductive filament

HRSLRS

Rupture：Oxygen ions

migrate toCeOx

Recouping：Oxygen ions

migrate toMetal

Figure 3.5 Resistance switching mechanism of W/CeOx/TiN structure ReRAM


-37-

3.3 Operation of CeOx ReRAM with p+-Si bottom electrode

3.3.1 Characteristics of W/CeOx/ p+-Si ReRAM

p+-Si impurity concentration is about 1018. Therefore, it degeneracy and can be used as a bottom

electrode. The resistive switching characteristics with p+-Si bottom electrode is shown in Fig. 3.6.

CeOx thickness was set 13nm. It obtained bipolar type resistive switching. After initial voltage

sweep, precipitous decreasing of current has occurred at reset process. Resistance ratio is over

103 at applied voltage of -0.1V.

10-8

10-6

10-4

10-2

Cu

rren

t(A

)

0 5Voltage (V)

-5

10-10

10-12

10



Process▲ Set

Process

WCeOxp+-Si

Figure 3.6 Bipolar resistance switching characteristics of W/CeOx/p+-Si structure ReRAM

This characteristics isn’t caused by change of resistance on CeOx but on interface oxide layer

between CeOx and p+-Si. The interface oxide layer is SiO2 because bottom electrode is p+-Si. It

formed when CeOx was evaporated. SiO2 shows larger resistance than ionically-bonded oxide,

because it is covalently-bonded oxide. Large resistance ratio was obtained by resistance

changing of SiO2.(Fig. 3.7) However, ReRAM with p+-Si bottom electrode need large voltage in


-38-

forming process that mean initial sweep because SiO2 thickness was thick. And resistance ratio

becomes small as compare with initial sweep.

SiO2

W

CeOx

p+-Si

Buffer layer

Resistive Switching layer

Figure 3.7 Resistance switching mechanism of W/CeOx/ p+-Si structure ReRAM

3.3.2 Control of SiO2 formed between CeOx/p+-Si interface

Operation mechanism of W/CeOx/p+-Si ReRAM is caused by change of SiO2 film. Therefore,

change of SiO2 thickness can change characteristics about operation voltage, resistance ratio etc.

p+-Si was annealed for 5 minute at 850ºC (ambience N2:O2=95%:5%) before CeOx evaporation

for forming thicker SiO2 than when p+-Si wasn’t annealed. The resistive switching

characteristics of ReRAM with annealed p+-Si bottom electrode is shown in Fig. 3.8.

10-8

10-6

10-4

10-2

Cu

rren

t(A

)

0 5Voltage (V)

-5

10-10

10-12

10

Compliance Current:0.1mA


Process▲ Set

Process

W

p+-SiSiO2

CeOx

W

p+-SiSiO2

CeOx

(a)


-39-

10-8

10-6

10-4

10-2

10-10

10-12

0 2Voltage (V)

4 6 8

● W/CeOx/p+-Si

◆ W/CeOx/annealed p+-Si

(b)

Figure 3.8 (a)Bipolar resistance switching characteristics of W/CeOx/SiO2/p+-Si structure

ReRAM (b)Compare with p+-Si annealing

Initial resistance change to high value compare with no annealing. And Compliance current can

suppress at 100A. Moreover, operation voltage of initial sweep doesn’t change compare with

no annealing. It is caused by not only SiO2 film grow but also SiO2 film become high quality

compare with no annealing. However, it needs high voltage in forming process yet.


-40-

3.4 Operation of CeOx ReRAM with NiSi2 bottom electrode 3.4.1 Characteristics of W/CeOx/NiSi2 ReRAM

The resistive switching characteristics with NiSi2 bottom electrode is shown in Fig. 3.9. Finally,

device was annealed in nitrogen ambience for 1 minute at 500ºC. CeOx thickness was set

3.25nm. A large decrease in the current during the reset process by 103 is a characteristic of the

sample and, therefore, a large on and off ratio over 104 at applied voltage of -0.1V can be

obtained. Although a relatively high set voltage of 5V is needed to switch the resistance, the

current showed comparable values for the initial and set processes (forming-free) with this

electrode material.

10-11

10-9

10-7

10-5

10-3

10-1

Cu

rren

t(A

)



Process▲ Set

Process

0-3 5Voltage (V)

-2 -1 1 2 3 4 610-13

W

CeOx

NiSi2

Figure 3.8 Bipolar resistance switching characteristics of W/CeOx /NiSi2 structure ReRAM

It is anticipated that the existence of reaction between the Ce oxide and the NiSi2 layers, where

Si atoms act to enhance the resistive switching. TEM image of W/CeOx/NiSi2 structure ReRAM

was showed in Fig. 3.9. Interface layer has been confirmed between CeOx and NiSi2 by TEM

measurement. Pure SiO2 has been formed on NiSi2 by oxidation has been reported[7].


-41-

W

CeOx

NiSi2SiO2

Figure 3.9 TEM image of W/CeOx/NiSi2 structure ReRAM

Set process and reset process are caused by happen of SiO2 breakdown from electric field

concentration and re-oxidation by oxygen from CeOx.(Fig. 3.10) Forming free characteristics is

caused by confinement of SiO2 from using NiSi2 as a bottom electrode, because NiSi2 can

confine supply quantity of Si for form SiO2.

WCeOx

SiO2

NiSi2

O2-

(+)

(-)

O2-

WCeOx

SiO2

NiSi2

O2-

O2-

(+)

(-)

Set process

Reset process

Figure 3.10 Resistance switching mechanism of W/CeOx/ NiSi2 structure ReRAM


-42-

Pulse measurement was shown in Fig. 3.11. Pulse length and voltage were set 5s and 3.9V in

set process. And pulse length and voltage were set 80s and -3.25V in reset process. Resistance

ratio keeps over 104 greater than 102 cycles. It is considered that electric field was vanishingly

impressed at CeOx when soft dielectric breakdown has occurred at SiO2. Therefore, it is

speculated that W/CeOx/NiSi2 structure ReRAM obtained good stability.

102

104

106

108

0 100Cycle

Res

ista

nce

（）

Read Voltage:-0.1V1010

100

80604020

ON/OFF～104

5s

Vset=3.9V

80s

Vreset=-3.25V

Figure 3.11 Operation cycle of W/CeOx/ NiSi2 structure ReRAM

Dependence of operation speed is showed in Fig. 3.12. Pulse voltage of set process and reset

process were set 4.25V and -3.5V in set process. Resistance ratio keeps over 104 up until speed

of operation is faster than 200ns.


-43-

10-1 100 101 102 103

Operation speed (s)

ON/OFF～104

Vset=4.25V

Vreset=-3.5V

102

104

106

108

Res

ista

nce

（）

1010

100

Read Voltage:-0.1V

Figure 3.12 Dependence of operation speed of W/CeOx/ NiSi2 structure ReRAM

3.4.2 Control of SiO2 formed between CeOx/NiSi2 interface

Operation mechanism of ReRAM with NiSi2 bottom electrode is caused by change of SiO2 film

same as using p+-Si bottom electrode. Moreover, ReRAM with NiSi2 bottom electrode can gain

high resistance ratio with keeping low operation voltage because it can confine thickness of SiO2

by confinement of supply quantity of Si for form SiO2. The resistive switching characteristics of

ReRAM with annealed NiSi2 bottom electrode before CeOx evaporation is shown in Fig. 3.13.

Fig. 3.13 is (a) not annealed (b)annealed in nitrogen ambience for 1 minute at 500ºC (c)

annealed in N2:O2=95%:5% ambience for 1 minute at 500ºC (d) annealed in N2:O2=95%:5%

ambience for 1 minute at 650ºC. Initial resistance change to high value in the sequence that

(a),(b),(c) and resistance ratio show over 105. And operation voltage of initial sweep vanishingly

change in (a),(b),(c). It is considered that these characteristics aren’t caused by growth of SiO2

film but quality of SiO2 become high depending on bottom electrode annealing. ReRAM with

annealed in N2:O2=95%:5% ambience for 1 minute at 650ºC(d) show large operation voltage,


-44-

resistance ratio show over 106 and compliance current can suppress at 100A. Moreover, that

doesn’t show forming-free same as using p+-Si bottom electrode. Therefore, it is considered that

annealing at 650ºC induce growth of overmuch SiO2.

10-11

10-9

10-7

10-5

10-3

10-1

Cu

rren

t(A

)

Voltage (V)

10-13


(a)

0-3 5-2 -1 1 2 3 4 6


Process▲ Set

Process

10-11

10-9

10-7

10-5

10-3

10-1

Cu

rren

t(A

)



Process▲ Set

Process

0-3 5Voltage (V)

-2 -1 1 2 3 4 610-13

(b)

10-11

10-9

10-7

10-5

10-3

10-1

Cu

rren

t(A

)

0-3 5Voltage (V)

-2 -1 1 2 3 4 610-13


(c)


Process▲ Set

Process

10-11

10-9

10-7

10-5

10-3

10-1

Cu

rren

t(A

)

Compliance Current:100A


Process▲ Set

Process

Voltage (V)

10-13(d)

0-3 5-2 -1 1 2 3 4 6

Figure 3.13 Bipolar resistance switching characteristics of W/CeOx/NiSi2 structure ReRAM

with (a) no annealing, (b) 500oC, 1min (ambience:N2) annealing,

(c) 500oC, 1min (ambience N2:O2=95%:5%) annealing and

(d) 650oC, 1min (ambience N2:O2=95%:5%) annealing bottom annealing


-45-

Dependence of annealing ambience and temperature for bottom electrode is shown in Fig. 3.14.

It is confirmed that possibility of control resistance ratio by changing annealing temperature and

ambience. Annealing temperature of 500oC is best temperature of gaining large resistance ratio

because annealing at 650oC induce degradation.

0

0.5

1.0

1.5

2.0(×106)

Re

sist

anc

era

tio

200 400 600 800

● No annealing▲ 500oC annealing (N2)▲ 500oC annealing (O2)◆ 650oC annealing (O2)

Annealing temperature (oC)

Read Voltage:-0.1V

Figure 3.14 Dependence of annealing ambience and temperature for bottom electrode

3.4.3 Temperature resistance of W/CeOx/NiSi2 ReRAM

Characteristics of W/CeOx/NiSi2 ReRAM with annealing in nitrogen at 700,800oC are shown in

Fig. 3.15. Resistance ratio over 106 was gained at 700oC annealing outside ReRAM with bottom

electrode annealing in N2:O2=95%:5% ambience at 650oC. And compliance current set lower

10-4 same as effect of bottom electrode annealing. In contrast, resistance ratio at 800oC annealing

became reduced to 103. It is considered that this isn’t caused by growth of SiO2 but mix of metal

and insulator.


-46-

10-11

10-9

10-7

10-5

10-3

10-1C

urr

ent

(A)


Process▲ Set

Process10-13


0-3 5Voltage (V)

-2 -1 1 2 3 4 6

(a)

10-11

10-9

10-7

10-5

10-3

10-1

Cu

rren

t(A

)


Process▲ Set

Process10-13


0-3 5Voltage (V)

-2 -1 1 2 3 4 6

(b)

10-11

10-9

10-7

10-5

10-3

10-1

Cu

rren

t(A

)


Process▲ Set

Process

0-3 5Voltage (V)

-2 -1 1 2 3 4 610-13


(c)

10-11

10-9

10-7

10-5

10-3

10-1

Cu

rren

t(A

)Compliance Current:10A


Process▲ Set

Process

0-3 5Voltage (V)

-2 -1 1 2 3 4 610-13

(d)

10-11

10-9

10-7

10-5

10-3

10-1

Cu

rren

t(A

)


Process▲ Set

Process

0-3 5Voltage (V)

-2 -1 1 2 3 4 610-13


(e)

Figure 3.15 Bipolar resistance switching characteristics of W/CeOx/NiSi2 structure ReRAM

annealed (a) 700oC, 1min (b) 800oC, 1min with no bottom electrode annealing,

(c) 700oC, 1min (d) 800oC, 1min with 500oC (ambiance:N2) bottom electrode annealing and

(e) 700oC, 1min with 500oC (ambience N2:O2=95%:5%) bottom electrode annealing


-47-

Dependence of annealing temperature for W/CeOx/NiSi2 structure ReRAM is shown in 3.16.

ReRAM with annealing bottom electrode in N2:O2=95%:5% ambience at 650oC don’t show

resistance switching characteristics over 700oC annealing and with annealing bottom electrode

in N2:O2=95%:5% ambience at 500oC don’t show resistance switching characteristics over

700oC annealing. Therefore, temperature resistance of W/CeOx/NiSi2 ReRAM is 700oC with

annealing bottom electrode in nitrogen ambience at 500oC.

103

104

105

106

107

Re

sist

anc

era

tio

200 400 600 800

● No annealing▲ 500oC annealing (N2)▲ 500oC annealing (O2)◆ 650oC annealing (O2)

0Annealing temperature (oC)

Read Voltage:-0.1V

Figure 3.16 Dependence of annealing temperature for W/CeOx/NiSi2 structure ReRAM


-48-

3.5 Conclusion The influence of the metal electrodes on the resistive switching behavior of CeOx films has been

investigated. Resistance switching properties using W, Ti and Ni as bottom electrode were

caused by changing resistance of W, Ti and Ni Oxide formed between CeOx/bottom electrode

interface. Resistance switching of W/CeOx/TiN structure ReRAM is caused by changing

resistance of Ce oxide. Their resistance ratio is lower than 103. Because W, Ti and Ni oxide is

very thin and resistance-change in insulator having ionic bond hardly obtain a large on and off

resistance ratio. However, resistance switching characteristics in samples with p+-Si electrode

shows a large on and off window over 104. It is caused by resistance switching of SiO2 formed

between CeOx/bottom electrode interface. SiO2 show high resistance because it is

covalently-bonded oxide. However, W/CeOx/p+-Si structure ReRAM needs large voltage in

forming process because formed SiO2 is thick. ReRAM with NiSi2 bottom electrode can show

forming free because it can confine of supply quantify of Si for forming SiO2. Moreover,

W/CeOx/NiSi2 structure ReRAM show resistance ratio over 106 by annealing.


-49-

Reference [1] L. F. Liu, X. Sun, B. Sun, J. F. Kang, Y. Wang, X. Y. Liu, R. Q. Han, G. C. Xiong, “Current

compliance-free resistive switching in nonstoichiometric CeOx films for nonvolatile memory

application”, IEEE International, pp. 1 (2009).

[2] C. Dou, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori,

H. Iwai, “Resistive switching behavior of a CeO2 based ReRAM cell incorporated with Si

buffer layer”, Microelectron. Reliab., 52, pp. 688 (2012).

[3] W. C. Chien, Y. R. Chen, Y. C. Chen, A. T. H. Chuang, F. M. Lee, Y. Y. Lin, E. K. Lai, Y.

H. Shih, K. Y. Hsieh, “A Forming-free WOX Resistive Memory Using a Novel Self-aligned

Field Enhancement Feature with Excellent Reliability and Scalability”, C. Lu, IEDM, pp. 440

(2010).

[4] Y.Y.Chen, G.Pourtois, X.P.Wang, C. Adelmann, L. Goux , B. Govoreanu, L. Pantisano, S.

Kubicek, L. Altimime, M. Jurczak, J. A. Kittl, G. Groeseneken, and D. J. Wouters, “Switching

by Ni filaments in a HfO2 matrix: a new pathway to improved unipolar switching RRAM”,

IEEE International (2011).

[5] Q. Lv, S. Wu, J. Lu, M. Yang, P. Hu S. Li, “Conducting nanofilaments formed by oxygen

vacancy migration in Ti/TiO2/TiN/MgO memristive device”, J. Appl. Phys., 110, 104511

(2011).

[6] E. Miranda, D. Jimenez, J. Sune, “From Post-Breakdown Conduction to Resistive

Switching Effect in Thin Dielectric Films”, IEEE, pp. GD.5.1 (2012).

[7] W. Strydom, J. C. Lombaard, R. Pretorius, “Low temperature formation of insulating layers

on silicides by anodic oxidation”, Solid-State Electron. 9, pp. 947, (1987).

-Chapter 4 Operation mechanism for W/CeOx/NiSi2 structure ReRAM and guideline of selection for buffer layer-

-50-

Chapter 4

Operation mechanismfor W/CeOx/NiSi2

structure ReRAMand guideline

of selection for buffer layer

4.1 Set process for W/CeOx/NiSi2 structure ReRAM

4.2 Reset process for W/CeOx/NiSi2 structure ReRAM

4.3 Dependence of CeOx thicknesses

4.4 Guideline of selection for buffer layer

4.5 Conclusion

Reference

Resistance switching characteristics in samples with NiSi2 electrode shows a large on and off

window over 106. Interface layer was confirmed at CeOx/NiSi2 interface by TEM image. And

pure SiO2 was formed on NiSi2 surface by oxidation. Therefore, Resistance switching

mechanism of W/CeOx/NiSi2 structure ReRAM is caused by resistance switching of SiO2

formed between CeOx/bottom electrode interface. In this chapter, the resistance switching

behavior of W/CeOx/NiSi2 structure has been investigated.


-51-

4.1 Set process for W/CeOx/NiSi2 structure ReRAM SiO2 is low dielectric constant distinctly as compared with other covalently-bonded oxide about

B2O3, Al2O3, GeO2, As2O3 etc. Therefore, if SiO2 contact with high dielectric constant about

CeOx, electric field concentration has occurred at only SiO2. Dielectric breakdown has occurred

at SiO2 by electric field concentration, and resistance change low state. Resistance switching

beaver is shown in Fig. 4.1. Set process results from this dielectric breakdown of SiO2.

2SiOε

WCeOx

SiO2

NiSi2

Small E

Large E

O2-

O2-xCeOε( :28)

Vo2+

:Oxygen vacancy

Breakdown spot

(+)

(-)

Figure 4.1 Set process for W/CeOx/NiSi2 structure ReRAM


-52-

4.2 Reset process for W/CeOx/NiSi2 structure ReRAM Reset process results from re-oxidation of defects by CeOx that happened at dielectric

breakdown of SiO2. After dielectric breakdown had happened at SiO2, electric field was almost

impressed at CeOx. Ion is easy of migration over CeOx, because of CeOx is solid electrolyte.

Therefore, it was considered that oxygen ions from the CeOx layer was migration to induce local

anodic oxidation of the breakdown spot to create SiO2 and change the state to HRS while

impressing electric field[1]. Resistance switching beaver is shown in Fig. 4.2. It is considered that

ReRAM with NiSi2 bottom electrode gain forming-free characteristics is caused by CeOx could

re-oxidation all defect in SiO2 when it comes in dielectric breakdown. Because of NiSi2 can

confine growth of SiO2 thickness.

WCeOx

SiO2

NiSi2

O2-

(+)

(-)Oxygen

ions migration

Re-oxidationbreakdown spot

O2-

Figure 4.2 Reset process for W/CeOx/NiSi2 structure ReRAM


-53-

4.3 Dependence of CeOx thicknesses Alternatively, it can be considered that operating voltage depend on distribution of SiO2 and

CeOx thickness. Equation 1. shows relation of applied voltage and voltage distribution of SiO2

and CeOx.

xx CeOCeOSiOSiO EdEdV 22

(1)

Where V is applied voltage; 2SiOd ,

xCeOd are film thickness of SiO2 and CeOx;1SiOE ,

xCeOE are electric field are impressed at SiO2 and CeOx. Film thickness of SiO2 is 1.5nm that

was checked by Transmission Electron Microscope (TEM) measurement. Additionally,

dielectric constant of CeOx is about septuple dielectric constant of SiO2. Therefore, equation. 1

changes to 2.

22 7

15.1 SiOCeOSiO EdEV

x

27

15.1 SiOCeO Ed

x

(2)

Equation 2. shows that operating voltage depend on film thickness of CeOx. Therefore, it can be

inferred that scaling film thickness can accomplish low operation voltage. Characteristics of

ReRAM changing CeOx are shown in Fig. 4.3. As noted previously, operation voltages of set,

reset process become lower with decreasing of CeOx thickness. However, resistance ratio

becomes lower with decreasing of CeOx thickness too. It is caused by decreasing of SiO2

thickness. It is caused by oxidizability of CeOx decrease with decreasing of CeOx thickness.


-54-

0 4 8-410-12

10-10

10-8

10-6

10-4

10-2

Voltage (V)



Process▲ Set

Process

106-6 2-2

Cu

rren

t(A

)

(a)

Cu

rren

t(A

)


Process▲ Set

Process


0-3 5Voltage (V)

-2 -1 1 2 3 4

(b)10-12

10-10

10-8

10-6

10-4

10-2

10-12

10-10

10-8

10-6

10-4

10-2

Cu

rren

t(A

)

0-3 5Voltage (V)

-2 -1 1 2 3 4



Process▲ Set

Process(c)

10-12

10-10

10-8

10-6

10-4

10-2

Cu

rren

t(A

)

0Voltage (V)

-2 -1 1 2 3 4



Process▲ Set

Process(d)

Figure 4.2 Resistance switching characteristics of W/(a)CeOx(13nm),

(b)CeOx(6.5nm), (c)CeOx(3.25nm)and (d)CeOx(2nm)/NiSi2 structure ReRAM

CeOx thickness dependence of operation voltage in set process is shown in Fig. 4.3. It is shown

that set voltage can be reduced nearly down to 3 V. This figure shows the set voltage as a

function of CeOx thickness, which can be well fitted by calculated result when the breakdown

electric field of SiO2 was set to 16MV/cm. This indicates that the set process is triggered by the

electric field. This breakdown electric field of SiO2 was matched to reported data about

15MV/cm, which further demonstrates the mechanism.


-55-

0 5 1510

8

6

4

2

Thickness (nm)

Vo

ltag

e(V

)

2SiOT

2SiOE=1.5 (nm)=16 (MV/cm)

Se

t vo

lta

ge

(V

)

Figure 4.3 CeOx thickness dependence of operation voltage in set process


-56-

4.4 Guideline of selection for buffer layer For set-process, high electric field induces a breakdown to the SiO2 to change the state to LRS,

as the dielectric constant is low (k~4). The requirements for buffer high-k layer include high

dielectric constant and high breakdown field so as not to form filaments in the buffer high-k

layer. As LRS is mainly limited by the electron conduction of buffer high-k layer, narrow

bandgap is preferable to lower the resistance, which is usually the case for higher-k material.

Resistance switching characteristics ReRAM with HfO2 and TiO2 as an insulator are showed in

Fig.4.4. Their show large resistance ratio although need large voltage in forming process. It is

coursed by their oxygen ionic conductivity is low. Therefore, local anodic oxidation is not

enough to return resistance to initial state in reset process.

10-12

10-10

10-8

10-6

10-4

10-2

Cu

rren

t(A

)

0 4 8-4Voltage (V)

10-14

62 10-2-6-8-10



Process▲ Set

Process

W

HfO2

NiSi2

(a)


-57-

10-10

10-8

10-6

10-4

10-2

Cu

rren

t(A

)

10-12

10-14


0-4Voltage (V)

-2 6 82 4 10


Process▲ Set

Process

TiN

NiSi2

TiO2

(b)

Figure 4.4 Resistance switching characteristics of (a) W/HfO2(2nm)/NiSi2,

(b) W/TiO2 (13nm)/NiSi2

For reset-process, oxygen ions from the buffer high-k layer induce local anodic oxidation of the

breakdown spot to create SiO2 and change the state to HRS, so that the requirement for buffer

high-k layer is high oxygen ionic conductivity in room temperature. Temperature dependence of

ionic conductivity is shown in Fig. 4.5.


-58-

10-4

100

10-4

10-12

10-16Ioni

c co

nduc

tivity

(S

/cm

)

10-8

1000/T (K-1)1.0 1.5 2.0 2.5 3.0 3.5

500 200 100 27300Temperature (oC)

poly-YSZ**

poly-CeO2*[2]

[3]

Figure 4.5 Temperature dependence of ionic conductivity

Furthermore, electron conducts fast in grain boundary and conducts slow in lattice. In contrast,

oxygen ion conducts fast in lattice and conducts slow in grain boundary has been reported[2].

This lead lowering grain boundary in insulator depending on addition trivalent dopants to CeOx

assists high ion conductivity[3.4]. Model of gaining forming-free characteristics is shown in Fig.

4.6. For gaining forming-free characteristics, the requirement for buffer high-k layer is high

oxygen ionic conductivity. Moreover, control SiO2 thickness with high oxygen ionic

conductivity buffer layer can gain large resistance ratio remaining forming-free.


-59-

0 1 2 3 4 5

10-6

10-8

10-10

10-12

10-14

10-16

Thickness of SiO2 (nm)

Ion

ic c

ond

uctiv

ity (

S/c

m)

poly-YSZ@RTYSZ=1.1x10-16 S/cm

poly-CeO2@RTCeO2=2.4x10-10 S/cm

Forming-free region

forming

ON

OFF

Figure 4.6 Model of gaining forming-free characteristics


-60-

4.5 Conclusion The resistance switching behavior of W/CeOx/NiSi2 structure has been investigated. Resistance

switching mechanism is caused by soft dielectric breakdown hinge on electric field

concentration and reparation by CeOx. Large resistance ratio, forming-free and high switching

speed have obtained as characteristics of W/CeOx/NiSi2 structure ReRAM. Large resistance

ratio was caused by resistance switching depend SiO2 formed between CeOx and NiSi2.

Forming-free was caused by CeOx restored SiO2 to its former state. High switching speed was

caused by CeOx is solid electrolyte that show high ionically-conductive. The requirements for

buffer high-k layer include high dielectric constant and high breakdown field so as not to form

filaments in the buffer high-k layer and high oxygen ionic conductivity.


-61-

Reference [1] Y. R. ma, C. Yu, Y. Yao, Y. Liou, S. Lee, “Tip induced local anodic oxidation the native SiO2

layer of Si(111) using an atomic force microscope” , Phys. Rev. B, 64, 195324, (2001).

[2] R. G. Anderson, S. Nowick, “Grain-Boundary Effect in Ceria Doped with Ttivalent Cation: I,

Electrical Measurements”, J. Am. Ceram. Soc., 69, pp. 641 (1986).

[3] R. G. Anderson, S. Nowick, “Ionic conductivity of CeO2 with trivalent dopant ionic radii”,

Solid State Ionics, 5, 547-550 (1981).

[4] S. Thevuthasan, S. Azad, O. A. Marina, V. Shutthanandan, D. E. McCready, L. Saraf, C. M.

Wang, I. Lyubinetsky, C. H. F. Peden, “Influence of Multiple Interfaces on Oxygen Ionic

Conductivity in Gadolinia-Doped Single Crystal Oxide Electrolyte Multi-Layer Nano Films”,

3rd IEEE-NANO, pp. 550-552 (2003).

-Chapter 5 Transient response for reset process-

-62-

Chapter 5

Transient response for reset process

5.1 Transient response characteristics for reset process

5.2 Model of local anodic oxidation SiO2 breakdown spot in reset process

5.3 Conclusion

Reference

The higher the dielectric constant of the buffer layer is, the lower operation voltage in set

process can be. However, for reset process, the voltage required to change the state to HRS is

dependent on stress time.


-63-

5.1 Transient response characteristics for reset process Time dependence of operation voltage in reset process is shown in Fig.5.1. The gradual decrease

in current under constant voltage (Vstress) application indicates a gradual decrease in the size of

the breakdown spot and once SiO2 is grown enough the current drops to HRS.

0

1

2

3

4

5

│Cu

rren

t(m

A)

│

6

10-1 100 101 102 103 104

Time (ms)

■ -2.2V ◆ -1.9V▲ -2.1V ● -1.8V◆ -2.0V

Figure 5.1 Time dependence of operation voltage in reset process

It is worth noting that at Vstress of -1.8V, discrete values were observed. Extended figure of Vstress

set -1.8V is shown in Fig. 5.2. It is considered that SiO2 was re-oxidized each single layer in

breakdown spot by local anodic oxidation. And this is reason of current show discrete values.


-64-

2.0

│Cu

rren

t(m

A)

│

2.1

2.2

2.3

2.4

2.5

Voltage:-1.8V

Time (ks)2.5 3.0 3.5 4.0 4.5

Figure 5.2 Extended figure of time dependence when reset voltage set -1.8V

Resistance steeply changes to next resistance state when SiO2 single layer in breakdown spot

was formed. Histogram of conductance when steady voltage was applied to device is shown in

Fig. 5.3. Steady voltages set at -1.65 ~ -1.2V. 4 peaks are confirmed in histogram. SiO2 thickness

is confirmed as 1.5 ~ 2.0nm by TEM image. Therefore, 4 layers SiO2 exist at CeOx/NiSi2

interface. And this produces discrete values of current.


-65-

0.5 1.0 1.5 3.02.0 2.5

50

100

150

200

250N

um

ber

of

tim

es

Conductance (m/)

Figure 5.3 Histogram of conductance in re-oxidation process

Fluctuations of current exist in local anodic oxidation in Fig.5.2.It is considered that fluctuations

come about reparation and breaking of SiO2 existing in reset process.


-66-

5.2 Model of local anodic oxidation SiO2 breakdown spot in

reset process Two reactions coinstantaneously happen in reset process. Reparation faces competition with

breaking. Time of resistance back in initial state is depend on the balance of oxygen ion

migration to oxidize Si atoms[1] and electron impacts to break the created Si-O bondings[2],

which is advantageous for large read-out margin. The model of local anodic oxidation SiO2

breakdown spot is shown in Fig. 5.3. Fluctuations of current exist in Fig. 5.2 are caused by

competition of SiO2 formation and dissociation.

Breakdown spot after set

SiO2

SiO2

CeOX

NiSi2

e O2

E

2. SiO2 dissociation by electron bombard

2. 1a

1a. SiO2 formation by anodic oxidation1b. Passivation of oxygen vacancies at breakdown spot

SiO

1b

Oxygen vacancies

Figure 5.2 Model of local anodic oxidation SiO2 breakdown spot


-67-

5.3 Conclusion SiO2 breakdown spot was re-oxidized each single layer by local anodic oxidation. It is

confirmed by discrete value of current. Moreover, reaction of SiO2 formation and dissociation

exist in reset process. Fluctuations of current are caused by two reactions. SiO2 formation is

dominant in high reset voltage. However, SiO2 dissociation by electron impacts to break the

created Si-O bondings isn’t negligible in low reset voltage.

Reference [1] T. Nagata, M. Haemori, Y. Yamashita, H. Yoshikawa, Y. Iwashita, “Oxygen migration at

Pt/HfO2/Pt interface under bias operation”, Appl. Phys. Lett., 97, pp. 082902 (2010).

[2] C. H. Tung, K. Pey, L. Tang, M. K. Radhakrishnan, W. Lin, “Percolation path and

dielectric-breakdown-induced-epitaxy evolution during ultrathin gate dielectric breakdown

transient”, Appl. Phys. Lett., 83, p.2223 (2003).

-Chapter 6 Conclusion-

-68-

Chapter 6

Conclusion

Through of this thesis, characteristics of ReRAM with CeOx as insulator was researched. Ce

oxides are known to present valence number fluctuation and to have high oxygen ion

conductivity which are expected to have potentials for resistive switching.

In the chapter 3, influence of bottom electrode for CeOx based ReRAM was researched.

Therefore, two resistance switching mechanism existed in CeOx based ReRAM was confirmed.

One of switching mechanism is resistance changing happens in CeOx. In this case, resistance

ratio is below 103 because resistance switching needs forming process and CeOx shows

ionically-bonded oxide. Resistance changing of ReRAM with forming process shows low

resistance ratio because resistance can’t back in initial state. And Insulator of ionically-bonded is

low resistance density. Another is resistance changing happens in CeOx/bottom electrode

interface. CeOx oxidation bottom electrode and oxide depended on bottom electrode was formed

in interface when CeOx was deposited. In this case, resistance switching beaver depend on oxide

in CeOx/bottom electrode interface. Besides, resistance ratio is below 103 too, because resistance

changing layer is thin. However, ReRAM with bottom electrode containing Si shows large

resistance ratio over 105. The reason of achieve large resistance ratio is SiO2 is covalently-bound

oxide which shows large resistance density. Among bottom electrodes containing Si, NiSi2

shows good characteristics because it can adjust SiO2 to optimal thickness.

-Chapter 6 Conclusion-

-69-

In the chapter 4, resistance switching mechanism of ReRAM with NiSi2 bottom electrode was

explained. Set process is due to breakdown of SiO2 formed in CeOx/NiSi2 interface. And, reset

process is due to re-oxidation of breakdown spot by oxygen from CeOx.

In the chapter 5, transient response characteristics for reset process was researched. Therefore,

SiO2 is re-oxidation each single layer by local anodic oxidation in breakdown. Moreover,

reaction of SiO2 formation and dissociation exist in reset process. SiO2 formation is due to

oxygen ions come from CeOx. And SiO2 dissociation is due to electron impacts to break the

created Si-O bondings.

Acknowledgement

First of all, I would like to express my gratitude to my supervisor Prof. Hiroshi Iwai for his

continuous encouragement and advices for my study. He also gave me many chances to attend

conferences. The experiences are precious for my present and future life.I deeply thank to Prof.

Takeo Hattori, Prof. Kenji Natori, Prof. Nobuyuki Sugii, Prof, Akira Nishiyama, Prof. Kazuo

Tsutsui, Prof. Yoshinori Kataoka, Associate Prof. Parhat Ahmet, and Associate Prof. Kuniyuki

Kakushima for useful advice and great help whenever I met difficult problem. Especially,

advance of ReRAM can't be achieved without help of Mr. Kakushima.I also thank research

colleagues of Iwai Lab. for their friendship, active many discussions and many of encouraging

words. I would like to appreciate the support of secretaries, Ms. Nishizawa and Ms. Matsumoto.

In addition, I appreciate to my mother, father, little bro and Miho. If I didn’t have their anchorage,

I couldn’t keep researching. And I became like K. Matsumoto when he turn to the dark side.

Finally, I give special thanks to syoujyo jidai.

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