802 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5, MAY 2002

A Novel Nonvolatile Memory Cell Suitable for BothFlash and Byte-Writable Applications

John M. Caywood, Senior Member, IEEE, Chih-Jen Huang, and Y. J. Chang

Abstract—The structure, operation, and fabrication of a novelEEPROM/Flash cell and array architecture are described. The cellis about half the size of the traditional floating gate tunnel oxide(FLOTOX) electrically erasable programmable read only memory(EEPROM) cell when laid out with the same design rules. This ap-proach has a simple fabrication sequence and requires minimumoverhead circuitry rendering it especially suitable for embeddedapplications. Characterization shows this approach has good re-tention and has million cycle endurance. Both read and write dis-turbs are characterized. There are large margins for both types ofdisturbs. In fact, the data on write disturbs show the disturb mar-gins to be so large that disturb margin can be safely traded off forreduced stress on select transistors.

Index Terms—Disturbs, EPROM, EEPROM, endurance, Flashmemory, retention.

I. INTRODUCTION

F LASH memories have become very common over the lastdecade. Despite this, they have a number of drawbacks. All

of the approaches in common use depend on electron tunnelingfrom the floating gate to discharge, i.e., erase, the floating gate.In those cells that lack a select gate and for which erase is a blockclear mechanism, there is a tendency to over-erase that must beovercome with one of several techniques that add complexityto the device operation [1]–[3]. The over-erase condition leadsto unwanted conduction of unselected cells in subsequent reador programming operations. Cells that erase from a reverse bi-ased junction are subject to band-to-band tunneling during eraseoperation, resulting in hot hole injection that degrades cell re-liability [4], [5]. There are a number of applications in whicha block clear is undesirable because it leads to the use of addi-tional temporary volatile storage or complicated data file struc-tures.

An E PROM memory avoids the disadvantages noted abovefor Flash memories by providing a select transistor in each cellthat prevents disturbs by shielding unselected cells from writevoltages. This transistor also allows the cell to be cleared intodepletion without penalty by blocking current through unse-lected cells.

Unfortunately, the well-known FLOTOX EPROM cell suf-fers from disadvantages of its own that outweigh the drawbacksthat it avoids. The principal disadvantage is the number of litho-graphic elements in series along the channel, which results in

Manuscript received July 23, 2001; revised January 21, 2002. The review ofthis paper was arranged by Editor R. Singh.

J. M. Caywood is associated with SubMicron Circuits, San Jose, CA 95134USA (e-mail: jcaywood@si-soln.com).

C. J. Huang and Y. J. Chang are with UMC, Hsinchu, Taiwan, R.O.C.Publisher Item Identifier S 0018-9383(02)03651-1.

these memories being relatively large and hence, expensive [6].A second limitation occurs during the selective erase that oper-ates by applying a high positive voltage to the bit line while thecontrol gate is biased at ground. The voltage that passes from thebit line to the diffusion under the tunneling window is limited bythe bias on the word line unless the word line bias is greater thanthe bit line bias by at least a threshold. Because of the sourcebias of the select transistor in this operation, the threshold istypically V, which significantly increases the voltage thatthe word line decoder must route. This higher voltage adds tothe process constraints, especially as processes are scaled intothe deep submicron region.

This paper describes an EEPROM cell and architecturethat has select gates to avoid over-erase and disturb problems,but which is applicable to moderate density embedded flashapplications because of its relatively small cell size and simpleprocess [7]. For example, when added to an 0.25m CMOSlogic process, the cell occupies m and adds fivemasking operations to a standard logic process, with mostof the extra operations employed to form the high voltageperipheral transistors not available in a standard 0.25m scaleCMOS logic process. Because both programming and eraseoccur via Fowler-Nordheim tunneling, it is possible to writeto large numbers of words in parallel and thus achieve datawrite rates comparable to flash memories in common use thatemploy channel hot electrons for programming.

In the sections that follow, the cell and its operation are de-scribed, followed by presentation of data on the retention andendurance of the cell as well as data on its resistance to disturbsin a array environment. Finally, extensions of this technologydeeper into the submicron regime are discussed.

II. DESCRIPTION OFCELL, ITS OPERATION, AND FABRICATION

A. Cell Description

Drawings of top view and cross-section views of the cell areshown in Fig. 1. The active region, which has a heavy outline,has the form of the letter “” in the top view. A first layer ofpolysilicon is used to form a floating gate memory transistor. Asecond layer of polysilicon, called the control gate, covers thefloating gate and extends beyond the floating gate on all sides.This second layer of poly forms a select transistor on each sideof the floating gate. The function of these transistors are dis-cussed below. The control gate also has strong capacitive cou-pling to the floating gate because the floating gate is opposed bythe second layer of poly on five of its six sides and thus couplesbias onto the floating gate for write and read operations.

0018-9383/02$17.00 © 2002 IEEE

CAYWOOD et al.: NOVEL NONVOLATILE MEMORY CELL 803

Fig. 1. Top and cross-section drawings of the cell described in this paper.

TABLE IOPERATIONAL BIASES FOR ACELL

B. Cell Operation

Application of a high positive voltage – V to the con-trol gate of a cell in a grounded n-well causes electrons to tunnelfrom the accumulated well to floating gate. This charges thefloating gate negative and turns on the floating gate transistorsince it is a p-channel device. Following IEEE Std. 1005, thisis called programming. The cell is erased by biasing the n-welland bit line at a high positive voltage, typically 14–15 V, andgrounding the control gate. Under these conditions, the selecttransistors and the floating gate transistor are all biased into con-duction which allows bit line potential to be established in the in-verted channel. This causes electrons to tunnel from the floatinggate to the inverted channel leaving the floating gate chargedpositive, inhibiting conduction of the floating gate transistor.In read mode, the n-well and source are biased to, as iscommon for p-channel transistors. The control gate is groundedand the bit line is biased to create a drain-source potential differ-ence of V. If the floating gate is programmed, there is con-duction between drain and source; if the floating gate is erased,no current flows. These operations are summarized in Table I.

C. Array Operation

Largely because of the select gates, the cell described here canbe operated in an array without complicated control circuitry toavoid overerase or overprogam. Fig. 2 is a schematic drawingof the cell in an EPROM array. Table II contains the array op-erating biases.

In Table II, the selected rows replicate the rows in Table Ias would be expected. The selected word is first cleared to acommon state and then selected bits within the word are writtento the complementary state to store an arbitrary pattern in theselected word, as is done in most word writable EPROMs. Forthe array shown in Fig. 2, the common state is program. In the

Fig. 2. Circuit schematic drawing of the cell imbedded in an array.

TABLE IIOPERATING CONDITIONS FORWORD REWRITABLE ARRAY

common FLOTOX array, the word to be cleared within a row isselected with a word select transistor which is laid out in whatis often referred to as the “ninth row” and which commonly en-larges the array by %. In the array depicted in Fig. 2, theselection is provided by placing each column of words in a sep-arate n-well; the n-wells of the unselected columns are biasedto inhibit programming. Thus in Fig. 2, the cells denoted as 00and 10 represent the cells in one well. Only one cell is shownon each word line in the wells for simplicity, but, actually, thenumber of cells in each well in the word line direction would beequal to the size of the word, e.g., 8 for a byte sized word. Thewell separation typically enlarges the array by about 15% in thecase of bytes.

In the clear operation, there are three different classes of uns-elected cells: those on a selected row, but in an unselected well;those on unselected rows, but in a selected well; and those onunselected rows and in unselected wells. The cells in unselectedwells on a selected row, in Fig. 2, have both control gateand well at which places no bias between the well and thefloating gate. The select transistors are nonconducting, blockingbias on the bit lines from affecting the floating gates. The unse-lected rows on the selected well, in Fig. 2, have controlgate, well and bit line all at ground. The unselected rows on theunselected wells, in Fig. 2, are at ground which turns onthe select transistors. This allows the bit lines, which are biasedat , to establish the channel potential at , the select tran-sistor threshold voltage. Thus, there is only a small potentialbetween the floating gates and the underlying channels whichinhibits tunneling on all unselected words.

804 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5, MAY 2002

In the write operation, all wells are biased at the same po-tential, . The select transistors on the unselected rows arenonconducting, whereas those on the selected row are all con-ducting as a result of the biases shown in Table II. One conse-quence of these conducting transistors is that the floating sourcelines are all biased near the potential of the associated bit linesso that punch-through of the select transistors during erase is in-hibited. On the selected row, the unselected bit lines, i.e., thosebits in the selected word that are to remain programmed plus allbit lines on the “unselected” words, are biased at ground. Thisresults in the floating gate channel potentials on the unselectedbit lines being , so that there is a small voltage differencebetween the floating gates and the channel potential, inFig. 2. On the unselected rows, 1 in Fig. 2, the controlgates and wells are at the same potential, . Therefore, thefields across the floating gate dielectrics are low.

The read mode is similar to most NV memories. Unselectedbit lines are allowed to float to reduce power consumption. Theselect transistors on the unselected word lines block current flowso that the floating gates can be allowed to program into deple-tion mode without interfering with proper sensing.

One important consequence of the low voltage differencemaintained between source and drain of the cell is that thechannel length of the series select transistors can be made quiteshort. This both reduces the cell area and increases the readcurrent.

Operation of the cell as a flash memory is easily accom-plished by merging the n-wells together. This saves approxi-mately 15% on the array area and causes all cells on a commonrow to program together to provide a block clear function.

D. Fabrication of Devices for Characterization

The memory cell was implemented in a 0.35m CMOS tech-nology for characterization. The gate length and width of thefloating gate transistor are 0.35m and 0.5 m, respectively.The control gate transistors are 0.3m in length.

The process used to fabricate these cells for characterizationwas designed for simplicity and to minimize the process devel-opment effort, not to optimize the performance of the memory.To begin this process, standard twin well formation and LOCOSisolation processes were performed. To avoid the complexity oftriple well formation, the cells were formed in the naturally iso-lated n-wells in the p-type substrate. This choice dictated theuse of a p-channel cell. After a sacrificial oxide was grown andstripped, the tunnel oxide was grown in dry oxygen.

A layer of polysilicon 200 nm thick was deposited and dopedwith a phosphorus implantation. The floating gates were definedin the poly silicon and the exposed tunnel oxide subsequentlyremoved. Then an ONO layer was formed by a combinationof thermal oxidation and chemical vapor deposition. The ONOwas removed from the regions in which the peripheral transis-tors were to be formed and a thermal oxide grown for the gatedielectric of these transistors. A second layer of poly was de-posited and the gates of the peripheral transistors and the controlgates of the memory cells were defined simultaneously. Finallygates and source/drains were doped together by boron implan-tation. The resulting parameters are listed in Table III.

TABLE IIIPROCESSPARAMETERS FORCELL IMPLEMENTATION

As can be seen from Table III, the differential oxidation ratebetween the heavily doped floating gate and the lightly dopedsubstrate resulted in the lower oxide layer in the ONO stackbeing about twice as thick for the ONO on the floating gate as itis in the control gate channel region. This results in a lower con-trol gate coupling ratio than would be the case if the ONO werethe same thickness in the two regions. Nevertheless, a couplingratio of 0.74 was measured on the cell.

III. CHARACTERIZATION

A. Operational Characteristics

As is clear from Fig. 1, the cell consists of three transis-tors is series; read current is limited by the transistor with thelowest conduction. Fig. 3 shows the ID-VD characteristic of acell with a programmed floating gate. The read current becomesvery small for V. One of the tradeoffs in the designof nonvolatile cells is the use of select transistors. One the onehand, it is very useful to have a select transistor because it elimi-nates many over-erase and disturb considerations. Also, it is de-sirable to integrate the select transistors with the control gate toreduce cell area, but this limits the measurement of floating gatethreshold. It is very difficult to measure a floating gate thresholdthat is significantly more positive (i.e., further toward deple-tion) than that of the control gates. With the fabrication flowchosen for this demonstration, the control gate thresholds areonly V. In normal memory operation, the floating gatewould be programmed into depletion to maximize read current,but, for characterization, it was convenient to program the cellsto a threshold of V so that the program threshold could beobserved.

Fig. 4 shows the time evolution of the floating gate threshold(as measured from the control gate) for program pulses between12 and 15 V. The time for the floating gate threshold to programto V ranges from s at a bias of 12 V to ms ata bias of 15 V. Since our goal is to program to a threshold ofless than V in ms, a control gate bias of 14 V is used forprogramming in the balance of the characterization.

Fig. 5 shows the time evolution of the floating gate thresholdas a function of the pulse amplitude during erase. The time re-quired to erase the floating gate threshold to4 V ranges from

s at 13 V to ms at 16 V. For the balance of the character-ization, an erase pulse of 16 V is employed.

CAYWOOD et al.: NOVEL NONVOLATILE MEMORY CELL 805

Fig. 3. I -V curves for a programmed cell. The gate bias is decreased from0 to�3.0 V in steps of�0.25 V.

Fig. 4. Time evolution of floating gate threshold during programming forcontrol gate biases of 12 V, 13 V, 14 V, and 15 V.

To test the retention of the memory cells, a number of cellswere programmed and erased 10 000 times. The thresholds ofthe cells were measured before and after a bake of 168 hoursat 250 C. The results are shown in Fig. 6. As can be seen, theretention is excellent with the maximum shift in thresholdmV. It is seen that the thresholds of the erased cells shifted morethan those of the programmed cells. This is the result of higherfield across the dielectrics surrounding the floating gate for theerased cells during storage.

The endurance of this approach was measured by applyingpulses in accordance with Table I. The for programmingwas 14 V applied for 5 ms and for erasing was 16 V applied for5 ms. The 1 A thresholds for program and erase were measuredas a function of number of cycles. The results are shownin Fig. 7. The window is seen to close by V. The thresholdof the select transistors can be measured by programming thefloating gate into depletion. Using this trick, the threshold ofthe select transistors was found to decrease by 100 mV after10 cycles as is seen in the insert of Fig. 7, indicating that theobserved window closure is caused by trapping in the tunneloxide. These traps are a result of the FN tunneling process usedfor writing.

Fig. 5. Time evolution of the floating gate threshold during erasing for controlgate biases of 13 V, 14 V, 15 V, and 16 V.

Fig. 6. Thresholds of cells before and after 168 h bake at 250C. The opensymbols are prebake, and the shaded symbols are postbake.

Fig. 7. Threshold of cell as function of number ofP=E cycles. The insertshows the time evolution of cell threshold during programming. During the shorttimes the cell threshold is controlled by the floating gate threshold while theselect gate threshold dominates at long times.

To further examine the effect of cycling, drain currentwas measured as a function of control gate voltage withcycles as a parameter for a drain bias ofV as is shown in the

806 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5, MAY 2002

Fig. 8. Subthreshold conduction slope as a function ofP=E cycles. Insertshows actual I -V curves after varying number of cycles.

inset of Fig. 8. As the plot of subthreshold slope versus cy-cles shows, there is substantial degradation in the subthresholdslope with cycling. This degradation may be the consequencesurface states created by high electric fields as described byMcPherson [8].

The consequence of this degradation in an array would be anincrease in the conduction of a selected erased cell. In the deepsubthreshold region, Fig. 9 shows that the leakage current in-creases from 0.2 pA to 200 pA. This increase would have noeffect on the ability of the selected erase bit to be detected cor-rectly.

B. Disturbs

Because the cell was implemented with ONO gate dielectricfor the cell select transistors, there is concern about the stabilityof the threshold of these transistors in view of the well knownSONOS memory technology. The effective oxide thickness ofthe ONO select transistor dielectric is 240. For an applied biasof 16 V, the field across the dielectric is 6.67 MV/cm. The oxidesemployed in the ONO dielectric were thick enough to precludedirect tunneling from the silicon of the substrate or gate intothe nitride, which is the usual method for charging the nitride inSONOS technology. However, electrons can be injected into thenitride via FN tunneling into the oxide followed by drift to thenitride or by trap assisted tunneling, TAT. The FN tunnel currentat under the applied field of 6.67 MV/cm can be calculated tobe A/cm , which would give C/cmafter 10 s, a time greater than that required for a millioncycles on a selected cell. This calculation is confirmed by theendurance data shown in Fig. 7.

The bias across the gate dielectrics of the unselected cells onthe selected row can be reduced by choosing to bias the unse-lected bit lines at a potential above ground. For example, if theunselected bit lines are biased at 5 V, the field across the gatedielectrics of the unselected cells is drastically reduced to 4.58MV/cm.

The price to be paid for the reduction in field across the se-lect gate dielectrics of the unselected cells is that there is now

Fig. 9. Leakage current through a cell with current limited by the floating gateat a threshold of�1 V as function ofP=E cycles.

Fig. 10. Accelerated program disturb versus time.

the possibility of disturbing the charge on the floating gate be-cause of the field between the floating gate and the underlyingchannel. If there are 256 words along a row, the total time thatthe disturb voltage can be applied is 1.28 s (2565 ms). In orderto obtain an observable change in the floating gate threshold ina convenient length of time, the disturb bias was increased from5 V to 9 V. Fig. 10 shows the result of biasing a cell with 9 V onthe bit line and 0 V on the control gate in an n-well biased at 16V. The programmed threshold can be seen to begin to increaseafter s. Since the increased bias used in the stress is equiv-alent to orders of magnitude in time, the cell has excellentresistance to this disturb.

A test was also carried out to determine the new cell’s sensi-tivity to read disturb. In this test a cell was biased in read modewith 1 V on the drain with varying bias applied to the controlgate. The time for the threshold to shift by 0.1 V was determined.A plot of the inverse of the magnitude of the control gate biasversus disturb time is shown in Fig. 11 for cells with 10and10 cycles. From this plot, it can be seen that even after10 cycles, the magnitude of bias to disturb a cell in 10years is V. Clearly, the intended control gate bias of2.5V has a large margin. Because of the select gates, the cells onunselected rows are not subjected to drain disturb as is the casefor many flash cells.

IV. DISCUSSION ANDCONCLUSIONS

In this paper, we describe a novel nonvolatile memory cellemploying channel FN tunneling for both program and erase.

CAYWOOD et al.: NOVEL NONVOLATILE MEMORY CELL 807

Fig. 11. Read disturb time versus the magnitude of the control gate bias forcells with10 and 10 P=E cycles.

Characterization shows that the cell programs and erases within5 ms with modest voltage pulses. The data shows good chargeretention characteristics that are insensitive to disturb or over-program. Endurance of more than a million cycles is alsodemonstrated.

In this demonstration, the interpoly dielectric and select gatedielectric were fabricated with the same ONO stack for processsimplicity. The cell is operated with essentially no voltage dif-ference between source and drain which allows the select tran-sistor gate length to be scaled aggressively. Measurements inthis study show that the array can be operated with reducedbiases on internal junctions without compromising reliability.This cell shows good promise for scaling to next generation andbeyond. Most lateral dimension are limited by lithographic con-siderations. The exception is the channel length of the selecttransistors, but simulation shows that this length can be scaledto m without experiencing punchthrough in read oper-ation or disturb during the write operation. The cell has beenlaid out in m with 0.25 m technology rules and in

m with 0.18 m rules. The process simplicity that thiscell approach allows is especially attractive for embedded ap-plications.

ACKNOWLEDGMENT

The authors would like to thank S.F. Hong and A. Wu forassistance in fabricating the devices and Y. C. Liu for assistancein characterization and helpful discussions.

REFERENCES

[1] T. C. Ong, A. Fazio, N. Mielke, S. Pan, N. Righos, G. Atwood, and S.Lai, “Erratic erase in ETOX flash memory array,” inVLSI Tech. Dig.,1993, pp. 83–84.

[2] C.-Y. Hu, D. L. Kenke, S. K. Banerjee, R. Richard, B. Bandyopadhyay,B. Moore, E. Ibok, and S. Garg, “Substrate-current-induced hot electron(SCIHE) injection: A new convergence scheme for flash memory,” inIEDM Tech. Dig., 1995, pp. 283–286.

[3] D. Esseni, C. Villa, S. Tassan, and B. Riccò, “Trading-off programmingspeed and current absorption in flash memories with the ramped-gateprogramming technique,”IEEE Trans. Electron Devices, vol. 47, pp.828–834, Apr. 2000.

[4] A. Brand, K. Wu, S. Pan, and D. Chin, “Novel read disturb failure mech-anism induced by FLASH cycling,” in31st Annu. Proc. Int. ReliabilityPhys. Symp., 1993, pp. 127–132.

[5] S. Haddad, C. Chang, A. Wang, J. Bustillo, J. Lien, T. Montalvo, and M.Van Buskirk, “An invetigation of erase-mode dependent hole trapping inflash EEPROM memory cell,”IEEE Electron Device Lett., vol. EDL-11,pp. 514–516, 1990.

[6] J. Caywood and G. Derbenwick, “Nonvolatile memory,” inULSI De-vices, C. Y. Chang and S. M. Sze, Eds. New York: Wiley, 2000, pp.377–473.

[7] C. J. Huang, Y. C. Liu, S. F. Hong, A. Wu, M. C. Wang, S. Hsu, L. C.Hsia, Y. J. Chang, Y. T. Lo, and F.-T. Liu, “A Novel P-channel flashEEPROM cell with simple process and low power consumption,” inProc. SSDM, 2000, pp. 278–279.

[8] J. W. McPherson and H. C. Mogul, “Disturbed bonding states in SiOthin-films and their impact on time dependent breakdown,” inProc.IEEE Int. Reliability Physics Symp., 1998, pp. 47–56.

John M. Caywood (M’70–SM’76) received theB.S.Eng., M.S.E.E., and Ph.D. degrees from Cali-fornia Institute of Technology (CalTech), Pasadena,in 1963, 1964, and 1969, respectively.

During the time at CalTech, he participated on theteams that published the first reports of solid stateepitaxy and molecular tunneling. After PostdoctoralFellowship positions at the University of Basel andCalTech, he joined Texas Instruments, Houston, TX,in 1972, where he worked on CCD technology andCMOS process development. In 1975, he joined

Fairchild Semiconductor with responsibility for development of the processfor advanced CCD memories. In 1976, he joined Intel Corp., where he wasresponsible successively for pseudo-static RAM development and reliabilityengineering for nonvolatile memories. In 1980, he joined Xicor, where over aperiod of nine years, he contributed to building the company from a start up,serving variously as Vice President of Reliability and QA and as Vice Presidentof Technology Development. Since 1989, he has served as a Consultant to theIC industry, chiefly in the area of nonvolatile memory.

Chih-Jen Huang received the M.S. and Ph.D. de-grees in electronics engineering from National ChengKung University, Taiwan, R.O.C., in 1988 and 1992.His doctoral research was directed toward process ofoxide film prepared by photo-assisted CVD, studieson oxide/III-V semiconductors interface, and MOSdevice characteristics.

In 1994, he joined the ERSO/ITIS, Hsin-Chu,Taiwan, where he worked on CCD process integra-tion, color filter, and microlens. From 1995 to 1999,he was in process development, Macronix Corp.,

(MXIC), Hsin-Chu, as a Senior Member of flash technology development.His area of concentration has been process and reliability of flash cell andlogic devices. Since 1999, he has been with United Microelectronics Corp.(UMC), and has been engaged in developing embedded flash technology. He iscurrently in charge of next generation nonvolatile memory development.

Y. J. Chang received B.S.E.E. from Cheng KungUniversity, Taiwan, R.O.C., the M.S.E.E. fromChiao Tung University, Hsinchu, Taiwan, and thePh.D. degree in electrical engineering from theUniversity of Southern California, Los Angeles.

He is currently in charge of the Quality and Re-liability Assurance Division, UMC, Hsinchu. Beforeshifting to this new job, he took care of the Device,RAM, Embedded DRAM, and Embedded NVM De-partments of the Technology Development Division.He joined UMC in 1998 and is currently the Vice

President of UMC. Prior to UMC, he was Senior Director of Holtek and As-sistant Vice President of Powerchip Semiconductor, Taiwan. In the U.S., he hadbeen with the companies of Cirrus Logic, Samsung, and Advanced Micro De-vices for 18 years. His major research interests are device and process technolo-gies as well as quality and reliability of semiconductors.