A New ZVT Snubber Cell for PWM PFC Boost Converter · 2017-09-26 · Switching (ZVS). Besides, the...

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2016.2608319, IEEETransactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Abstract—In this paper, a new Zero Voltage Transition (ZVT) snubber cell is developed for Pulse Width Modulated (PWM) and Power Factor Corrected (PFC) boost converters operating in Continuous Conduction Mode (CCM). A new family of PFC boost converter implemented with this new ZVT snubber cell is proposed. In this new PFC boost converter, the main switch is turned-on perfectly with ZVT and turned-off under Zero Voltage Switching (ZVS). Besides, the auxiliary switch is turned-on under Zero Current Switching (ZCS) and turned-off under ZVS. The main and all auxiliary diodes are operating under Soft Switching (SS). During ZVT operation, the switching energies on the snubber inductance are transferred to the output by a transformer, and so the current stresses of the inductance and the auxiliary switch are significantly decreased. Also, this transformer ensures the usage of sufficient capacitors for ZVS turning off of the main and auxiliary switches. The main switch and main diode are not subjected to any additional voltage and current stresses. In this study, a detailed steady state analysis of the proposed new ZVT-PWM-PFC boost converter is presented and this theoretical analysis is verified by a prototype with 100 kHz, 2 kW.

Index Terms—Soft switching, zero voltage switching,

zero voltage transition, power factor correction, boost converter.

I. INTRODUCTION

NERGY consumption has been increasing by the effect of

technological developments and rising prosperity,

therefore energy should be used more efficiently and

economical. The increasing nonlinear loads draw harmonic

currents which causes failures and corruptions on sensitive

devices which connected to the grid. Thus, energy should be

used in a quality manner, too. There are international

mandatory standards about power factor and harmonics in

terms of the use of energy with high quality and efficiency.

Manuscript received February 7, 2016; revised May 20, 2016 and

June 17, 2016; accepted June 18, 2016. This work was supported in part by the Office of Scientific Research Project Coordination of Yildiz Technical University under Grant number 2013-04-02-DOP04.

H. Bodur is with the Electrical Engineering Department, Electrical and Electronics Engineering Faculty, Yildiz Technical University, 34220 Istanbul, Turkey (e-mail: [email protected]).

S. Yıldırmaz is with AIM Energy Technologies Co., İstanbul Technical University Technopark, 34469 Istanbul, Turkey (phone:+90 212 286 33 35; fax:+90 212 383 58 58; e-mail: [email protected]).

Therefore, to cope with these standards, device manufacturers

use various techniques known as Power Factor Correction

(PFC) circuits. Power factor can be improved by means of

bulk passive filter or very complex and expensive active

filters, but nowadays academic and industrial applications

focused on high frequency AC-DC converter based PFC

circuits [1, 2]. Different approaches have been proposed to

improve efficiency and quality of energy by using PFC [3-12].

Basically PFC means reducing reactive power and

harmonics to zero. In the PFC circuits, as the frequency

increases, the wave shape of the current drawn from the source

approaches to sinusoidal wave, thus Total Harmonic

Distortion (THD) of the current is reduced. In power factor

corrected AC-DC converters, boost converters are used widely

because of simple structure, ease of control and high-power

density [1, 2]. Continuous Current Mode (CCM) operation is

preferred in high-power applications. In this case, the reverse

recovery of main diode causes turning off loss on this diode

and turning on loss on main switch, Electro Magnetic

Interference (EMI), and so a decrease in efficiency [2]. When

frequency is increased for a more quality PFC, the problems

mentioned above increase. These problems can be solved by

using soft switching (SS) techniques instead of hard switching

(HS) techniques. SS techniques can be classified as zero

voltage switching (ZVS), zero current switching (ZCS), zero

voltage transition (ZVT) and zero current transition (ZCT)

[13-40].

In order to solve the problems of the boost converter

operating in CCM, a lot of papers have been proposed in the

literature [13-15], [17], [18], [21, 22], [24-27], [32-34].

Although these studies are successful and provide most of the

desired properties, they still have some drawbacks. When

MOSFET is used as a power switch, discharge loss of the

parasitic capacitor becomes important [34]. In basic ZVT

technique providing the recovery of parasitic capacitor energy

[13], an anti-parallel diode to the main switch, an auxiliary

switch and an inductor are used for the aim of active

suppression. In this circuit, main switch is turned-on perfectly

with ZVT and main diode is turned off with ZCS. A parallel

capacitor can be added to the main switch for ZVS turn off of

the main switch and ZVS turn on of the main diode. However,

the auxiliary switch turns off hard and the current stress of this

switch is high in the circuit. Also, the capacitor added to the

main switch increases these problems further. In order to solve

these problems in the conventional ZVT converter, a lot of

papers have been proposed in the literature.

A New ZVT Snubber Cell for PWM-PFC Boost Converter

Hacı Bodur, Member, IEEE, and Suat Yıldırmaz

E




As an example, main switch is turned on with ZVT and

turned off with ZVS in the paper [17]. Auxiliary switch is

turned on with near ZCS and turned off under ZVS. However,

an additional current stress occurs on the main switch, current

stress on the auxiliary switch is considerably high and

auxiliary diode has an additional voltage stress. In the paper

[18], a coupled inductor is used in order to reduce the turning

off loss of the auxiliary switch. Main switch is turned on with

ZVT and turned off under ZVS. As the turning off energy of

the auxiliary switch is transferred to output by the aid of a

transformer, the switch turns on hard.

Similarly, main switch is turned on with ZVT and turned

off with ZCT in the paper [21]. The auxiliary switch is turned

on with ZCS and turned off with ZVS. At the same time main

diode is turned on with ZVS and turned off with ZCS. In this

circuit, main switch has an additional current stress, auxiliary

switch has high current stress and auxiliary diodes are

subjected to an additional voltage stress. In the paper [22], all

semi-conductors operate with ZVS or ZCS. There is no

additional current or voltage stress on the main switch and

main diode. Current and voltage stresses of the auxiliary

switch are considerably low. However, SS operation of the

main switch decays at light loads.

Snubber cell proposed in the paper [25] provides the turning

on of the main switch with ZVT and turning off with ZCT in

wide line voltage and load range. There is no additional

current or voltage stress on the main switch and main diode.

Stresses on the auxiliary semiconductor devices are

considerably low. However SS operation of the auxiliary

switch decays because of leakage inductance. In the paper

[26], as the main switch is turned on with ZVT and turned off

with ZCT, main diode and auxiliary switch is turned on and

turned off under SS. However, there is an additional current

stress occurs on the main switch. In the paper [28], as the main

switch turns on with ZVT and turns off under ZVS, auxiliary

switch turns on under ZCS without causing any additional

current stress of the main switch.

In the papers [17], [18], [19] and [26], anti-parallel diode is

required for the auxiliary switch. Total time of the transient

periods is significantly long in the papers [17], [21], [28]. In

[29], main switch turns on with ZVT, the auxiliary switch

turns on with ZCS and turns off with ZVS. There is no

additional current or voltage stress on the main switch.

Besides, auxiliary switch has high current stress, turning off of

the main switch occurs with near ZVS and depends on the

load. Moreover, total time of the transient periods is long.

In the paper [33], a snubber cell has been developed by

using MOFSET instead of the main diode. In this circuit, main

switch turns on with ZVT, main diode turns on and off with

ZCS, auxiliary switch turns on with ZVT. However, main

switch turns off hard. In [34], ZVT turn on and ZVS turn off

of the main switch is achieved. Auxiliary switch turns on and

off under ZCS. However, current stress of the auxiliary switch

is very high. The main switch is turned on with ZVT and

turned off with ZCT in [35]. The auxiliary switch is turned on

with ZCS and turned off with ZCT. The main switch is not

subjected to any current and voltage stresses. Also, the

auxiliary switch has no additional voltage stress but it has high

current stress. In the paper [27], a ZVT circuit is proposed in

order to reduce the current stress of the auxiliary switch. In

this circuit, ZVT turn on and ZVS turn off of the main switch

and reducing of current stress of the auxiliary switch are

achieved. However, in this circuit a transformer with a

magnetizing inductance of high value is required and the

auxiliary switch is turned off partially hard under the

magnetizing current. A capacitor with high value and a

resistance are used to reset magnetizing energy. Also, the

auxiliary switch and the auxiliary diode are subjected to an

additional voltage stress.

Consequently, a perfect PFC system can be achieved by

using a suitable AC-DC converter and with the application of

a convenient SS technique. In recent years, many papers have

been published about this topic. These studies focus on

providing SS operation for all semiconductor devices at all

load conditions and wide line range [27], [30–35].

In this study, a new ZVT-PWM-CCM-PFC boost converter,

which ensures most of the desired features and does not have

most of the drawbacks listed above, is proposed. In the PFC

boost converter equipped with new ZVT snubber cell, SS

operation of all main and auxiliary semiconductor devices is

provided. The switching energies are transferred to the output

by using a transformer during ZVT operation, thus the current

stresses of the auxiliary semiconductor devices are

significantly reduced, and so the usage of sufficient capacitors

for ZVS turning off of the main and auxiliary switches is

ensured. The main switch and the main diode are not subjected

to any additional voltage and current stresses. There is no

additional voltage stress on the auxiliary switch. Moreover,

this new converter can operate successfully at all rectified line

voltage values and under all load conditions. The proposed

converter has a quite simple structure, low cost and ease of

control. In this study, a detailed steady state analysis of the

proposed new ZVT-PWM-CCM-PFC boost converter is

presented and this theoretical analysis is verified by a

prototype with 100 kHz, 2 kW.

II. OPERATION MODES AND ANALYSIS

A. Definitions and Assumptions

The circuit scheme of the proposed PFC boost converter

equipped with new ZVT cell is given in Fig.1. In this circuit,

Vi is rectified line voltage, Vo is output voltage, TB is the main

or boost switch, DTB is the body or anti-parallel diode of the

main switch, DB is the main or boost diode, LB is the main or

boost inductor, Co is the output capacitor, Ro is the load

resistor. The proposed ZVT snubber cell consists of an

auxiliary switch (TS), four snubber diodes (D1, D2, D3, D4), a

snubber inductor (LS), a center tapped transformer (TR) which

has magnetizing inductor (LM), and snubber capacitors (CS1

and CS2). The capacitor CS1 contains the parasitic capacitors of

the main switch and the main diode.

Some assumptions can be made to simplify the converter

steady-state analysis in a switching cycle. Input voltage Vi,

output voltage Vo and the input current Ii are constant in a




switching period. The main switch TB, the auxiliary switch TS

and the auxiliary diodes could be treated as ideal.

B. Operation Stages of the Converter

Nine stages occur in the steady state operation of the

proposed converter over one switching cycle. The equivalent

circuit schemes of these operation stages are given in Fig. 2

respectively. Also key waveforms concerning the operation

stages are given in Fig. 3.

At the t<t0, TB and TS are in the off state. The main diode

DB is in the on state and conducts input current Ii of the main

inductor LB to the load. At the moment t = t0, the equations

iTB=0, iTS=0, iDB=Ii, iLS=0, iLM=0, vCS1=Vo, vCS2=0 are valid.

Stage 1 [ 0 2t t t : Fig. 2(a)]: At t=t0, the turn on signal

VGSTS is applied to the gate of the auxiliary switch TS. The

semiconductor devices TS, D1 and D3 are turned on under

ZCS. The rise rate of the current through TS, D1 and D3 is

limited by the snubber inductor LS. The equations obtained for

this stage are given as follows.

oLS D3 0

S

Vi i t t

L (1)

oLM 0

M

Vi t t

L (2)

oTS LS LM 0

e1

Vi i i t t

L (3)

oDB i 0

e2

Vi I t t

L (4)

In these equations, the following equations are valid.

S Me1

S M

L LL

L L

(5)

S Me2

S M

(L / 2)LL

(L / 2) L

(6)

In the interval of this stage, TS current rises and DB current

falls simultaneously and linearly. At t = t1, DB current falls to

zero. As a result, at t = t2, the reverse recovery current of DB

drops to –Irr. At the moment t = t2, main diode DB is turned off

with ZVS due to CS1 and ZVS through LS and this stage is

finished. Moreover, soft switching energies are stored in LS

and LM inductors and transferred to the load through LS. By

this way, the current stresses of auxiliary components decrease

significantly.

Stage 2 [ 2 3t t t : Fig. 2(b)]: At t=t2, iTB=0, iTS=ILS2+ILM2,

iDB=0, iLS=ILS2, iLM=ILM2, vCS1=Vo, vCS2=0 are valid. In this

interval, a resonance starts between CS1, LM and LS under the

input current Ii. For this resonance, the following equations are

obtained.

e3 oLS e3

S e3 S

e3i LS2 LM2 e3

S

e3 OLS2

S S

2L Vi 2 1 sin( (t t2)

L L

L2(I 2I I ) 1 cos( (t t2))

L

4L V1 t I

L L

(7)

e3 oLM e3

S e3 M

e3i LS2 LM2 e3

M

e3 OLM2

S M

2L Vi 1 sin( (t t2)

L L

L(I 2I I ) 1 cos (t t2)

L

2L Vt I

L L

(8)

e3 oCS1 e3

S e3

i LS2 LM2 e3

2L Vi 1 sin( (t t2)

L Z

(I 2I I )cos (t t2)

(9)

e3CS1 O e3

S

e3 i LS2 LM2 e3

e3O

S

2Lv 1 V cos( (t t2)

L

Z (I 2I I )sin (t t2)

2LV

L

(10)

In this interval, also the following equations are valid.

D3 LSi i (11)

TS LS LMi i i (12)

i CS1 LS LMI i 2i i (13)

In these equations,

s Me3

s M

(L / 4)LL

(L / 4) L

(14)

e3e3

S1

LZ

C (15)

e3

e3 s1

1

L C (16)

are valid. At the end of this interval, CS1 voltage becomes zero

and body diode DTB of the main switch TB is turned on with

ZVS through CS1. In this interval, switching energies which

includes CS1 is transferred to both LS and LM inductors and

output through LS. It should be noted that the capacitor CS1

includes the parasitic capacitors of the main switch and the

main diode.

Stage 3 [ 3 4t t t : Fig. 2(c)]: At t=t3, iTB=0, iTS=ILS3+ILM3,

iDB=0, iLS=ILS3, iLM=ILM3, vCS1=0, vCS2=0 are valid. Antiparallel

diode DTB of the main switch TB is in the on state.

Fig. 1. Proposed new ZVT-PWM-PFC boost converter.




(a) t0 < t < t2

(b) t2 < t < t3

(c) t3 < t < t4

(d) t4 < t < t5

(e) t5 < t < t6

(f) t6 < t < t7

(g) t7 < t < t8

(h) t8 < t < t9

(i) t9 < t < t10

Fig. 2 Equivalent circuit schemes of the operation modes in the proposed converter.




This interval is the interval of zero voltage transition (ZVT)

and the turn on signal VGSTB is applied to the gate of TB.

During this period, the voltage applied to LM inductor and

transformer is zero, the voltage produced by LS inductor is

equal to VO. For this stage, the following equations are

obtained.

OLS D3 LS3 3

S

Vi i I (t t )

L (17)

LM LM3i I (18)

OTS LS LM LS3 LM3 3

S

Vi i i I I (t t )

L (19)

DTB LS TS ii i i I (20)

At t=t4, the gate signal of auxiliary switch TS is removed, and

so TS is turned off with ZVS and TB is turned on with ZVT

perfectly, and this stage finishes. Energy of LS continues to be

transfer to the output, and this aids in decrease of the current

stresses of auxiliary components.

Stage 4 [ 4 5t t t : Fig. 2(d)]: At t=t4, iTB=0, iTS=ILS4+ILM4,

iDB=0, iLS=ILS4, iLM=ILM4, vCS1=0, vCS2=0 are valid. Just after

the gate signal of auxiliary switch TS is removed, iTB=Ii-ILS4

and iTS=0 and this stage begins. During this interval, a

resonance occurs between LS, LM inductors and CS2 capacitor

under constant input current Ii, via the paths seen in the

equivalent circuit.

e4 oLS e4 4

S e4 S

e4LS4 LM4 e4 2

S

e4 OLS4

S S

L Vi sin( (t t )

L L

L(I I ) 1 cos( (t t ))

L

L V1 t IL L

(21)

e4 oLM e4 4

S e4 M

e4LS4 LM4 e4 4

M

e4 OLM4

S M

L Vi sin( (t t )

L L

L(I I ) 1 cos( (t t ))

L

L Vt I

L L

(22)

e4 oCS2 e4 4

S e4

LS4 LM4 e4 4

L Vi sin( (t t )

L Z

(I I ) cos( (t t ))

(23)

are valid. At t=t5, as soon as inductor current iLS drops to zero

and D3 diode is turned off, this stage finishes. In this stage,

CS2 voltage is applied to auxiliary switch TS and so auxiliary

switch TS is turned off under ZVS through CS2. Also D3 diode

is turned off under ZCS through LS. Moreover, transferring of

the LS energy to the output and contribution to the reduction of

current stresses continues.

Stage 5 [ 5 6t t t : Fig. 2(e)]: At t=t5, iTB=Ii, iTS=0, iDB=0,

iLS=0, iLM=ILM5, vCS1=0, vCS2=VCS25 are valid. This stage starts

when D3 diode is turned off and at the same time iD2=ILM5. In

this interval, a resonance occurs between LM and CS2. For this

resonance, following equations is obtained.

CS25

LM e5 5 LM5 e5 5

e5

Vi sin( (t t ) I cos( (t t )

Z (24)

CS2 CS25 e5 5 e5 LM5 e5 5v V cos( (t t )) Z I sin( (t t )) (25)

In the equations above,

e5

M S2

1

L C (26)

M

e5

S2

LZ

C (27)

are valid. At the time t=t6, CS2 voltage reaches VO, and D4

diode turns on with ZCS, and this stage finishes.

Stage 6 [ 6 7t t t : Fig. 2(f) ]: A t t=t6, iTB=Ii, iTS=0 , iDB=0,

iLS=0, iLM=ILM6, vCS1=0, vCS2=Vo are valid. At the same time,

D2 and D4 diodes are turned on, and iTB=Ii-ILM6 and

iD2=iD4=ILM6 are valid, and this stage starts. The following

equations can be written.

o

LM LM6 6

M

Vi i (t t )

L (28)

TB i LMi I I (29)

Fig. 3. Key waveforms concerning the operation stages in the proposed converter.




At t=t7, the current of LM falls to zero and the current of TB

rise to Ii simultaneously and linearly, and this stage finishes. In

this stage, D1, D2 and D4 auxiliary diodes are turned off with

ZCS.

Stage 7 [ 7 8t t t : Fig. 2(g) ]: During this stage main

switch TB continues to conducts input current Ii and the

snubber circuit is not active. This stage is normal on state

duration of the conventional PWM converter and duration of

this stage depends on duty cycle. For this interval, the

following equation can be written.

TB ii I (30)

Stage 8 [ 8 9t t t : Fig. 2(h) ]: At t=t8, this stage starts by

removing the gate signal of main switch SB. In this interval,

CS1 capacitor is charged and CS2 is discharged by input current

Ii simultaneously and linearly. The following equation is

derived for this stage.

i

CS1 SB o CS2 8

S1 S2

Iv v V v (t t )

C C

(31)

At t=t9, the voltage of CS1 reaches Vo and the voltage of CS2

drops to zero, and so the main diode DB is turned on and this

stage finishes. In this stage, the sum of CS1 and CS2 ensures the

turn off of the main switch and turn on of the main diode with

ZVS.

Stage 9 [ 9 10t t t : Fig. 2(i) ]: During this stage main

diode DB continues to conduct input current Ii. The snubber

circuit is not active. This interval is off state duration of the

conventional PWM converter and the time period of this stage

depends on directly duty cycle. For this interval, the following

equation can be written.

DB ii I (32)

At t=t10=t0, at the moment the control signal of TS is applied to

its gate this stage finishes, at the same time one switching

period is completed and a new switching period is started.

III. DESIGN PROCEDURE

According to the assumptions commonly used in the

literature, design procedures of the proposed new ZVT

snubber cell can be summarized as follows.

a) If the ratio of magnetizing inductance LM of the center

tapped transformer TR to the snubber inductance LS is defined

as K, it has to be as high as possible in order to limit

transformer cost and current stress of auxiliary switch TS.

Also, inductance LS must be as high as possible to provide SS

and it must be as low as possible to limit transient intervals.

Depending on ratio K and inductance LS, inductance LM can be

written as follows.

M SL KL (33)

Here, the value of inductance LM can be selected to be at least

twice the value of inductance LS.

b) During turning on operation of auxiliary switch TS, the

current rising time from 0 to Ii must be at least the rise time tr

of the switch to provide turning on with ZCS at maximum

input current. In this situation, the following equation is

derived from (3) and (5).

O

S rTS

imax

VK 1L t

K I

(34)

c) During turning off operation of main diode DB, the current

falling time from Ii to 0 must be at least three times the reverse

recovery time trr of the diode to provide turning off with ZCS

at maximum input current. The following equation is derived

from (1), (3) and(6).

O

S rrDB

imax

V2K 1L 3t

K I

(35)

d) In this circuit, the sum of CS1 and CS2 snubber capacitors

provides ZVS turning off of main switch TB and only CS2

provides ZVS turning off of auxiliary switch TS. These

capacitors must be as high as possible to provide SS and as

low as possible to limit transient intervals. If the ratio of

capacitor CS1 to the capacitor CS2 is defined as M, depending

on the ratio M and the capacitor CS2, the capacitor CS1 can be

written as follows.

1 2S SC MC (36)

Here, the value of capacitor CS1 can be selected as equal to the

value of capacitor CS2.

e) During turning off operation of main switch TB, the voltage

rising time from 0 to Vo must be at least the fall time tf of the

switch to provide turning off with ZVS at maximum input

current. In this situation, the following equation is derived

from(31).

imax

S1 S2 S2 fTB

O

IC C (M 1)C t

V (37)

f) During turning off operation of auxiliary switch TS, the

voltage rising time from 0 to Vo must be at least the fall time tf

of the switch to provide turning off with ZVS at maximum

input current. If it is assumed that the capacitor CS2 is charged

from 0 to Vo with the current Ii approximately, the following

equation can be written.

imax

S2 fTS

O

IC t

V (38)

It can be seen that the selection of CS1 and CS2 to be equal is

suitable, if the fall time of TS is half of the fall time of TB and

they have equal turn off currents.

IV. CONVERTER FEATURES

The advantages of the PFC boost converter equipped with

the proposed ZVT snubber cell can be summarized as follows.

1. In ZVT operation, the switching energies are transferred

to the output by using center tapped transformer, therefore

the current stresses of the inductor, auxiliary switch and

other auxiliary components are decreased significantly.




2. By using the center tapped transformer, also the usage of

sufficient capacitors for ZVS turning off of the main and

auxiliary switches is ensured.

3. With the sum of two snubber capacitors provides the ZVS

turn off for the main switch and with one of them

provides the ZVS turn off for the auxiliary switch, and

also this is decreased the current stresses of the auxiliary

components.

4. The main switch turns on with ZVT and turns off under

ZVS.

5. The auxiliary switch turns on with ZCS and turns off

under ZVS.

6. All auxiliary diodes and the main diode operate under SS.

7. There is no additional voltage and current stresses on the

main switch and the main diode.

8. There is no additional voltage stresses on the auxiliary

switch.

9. There is no additional component on the main current

path.

10. It is not necessary a body diode on the auxiliary switch.

11. Energies stored in the parasitic capacitors of the main

switch and the main diode is recovered.

12. There is no negative effect of the center-tapped

transformer leakage inductance on the operation of the

converter. Leakage inductance does not affect the

operation or the performance of the converter.

13. SS conditions are maintained at very wide line and load

ranges.

14. The total time of the transient periods is very short

according to switching period.

V. EXPERIMENTAL RESULTS

A prototype of a 100 kHz and 2 kW shown in Fig. 4 was

performed to verify the theoretical analysis of the proposed

new ZVT-PWM-PFC boost converter. A photograph of the

experimental circuit is given in Fig. 5.

The boost inductance LB and output capacitor Co are

selected as 250 µH and 1500 µF respectively. LS=10 µH,

LM=20 µH, CS1=3.3nF, CS2=2.2nF are determined. Some

nominal values of the semiconductor devices used in the

prototype are listed in Table 1 with reference to the datasheets

of the manufacturers.

The oscillograms of the main switch TB, the auxiliary

switch TS, the main diode DB, the input, the output, and the

boost inductor LB are given in Fig. 6(a)-(f) respectively. The

experimental waveforms were obtained at nominal load. With

respect to Fig. 6(a), the main switch TB is turned on with ZVT

and turned off with ZVS. As shown in Fig. 4, the current iSB is

the sum of the main switch current and its body diode current.

The auxiliary switch TS is turned on with ZCS and turned off

with ZVS according Fig. 6(b). The signal of TS begins nearly

600 ns before the signal of TB. In Fig. 6(c), it can be seen that

the main diode DB is operated under soft switching conditions

at both turn on and turn off processes. There are no overlaps

between voltage and current waveforms of TB, TS and DB.

The input voltage and current waveforms are given in Fig.

6(d) for operating with 220 V and 50 Hz line values.

Measured power factor is near unity and THD is 4.2% for this

line voltage. At lower grid voltages, i.e. 85V, THD decreases

to 1.2%.

The output voltage and current waveforms are shown in Fig.

6(e) at full load. Maximum peak to peak voltage ripple is

measured 10 V. This value can be reduced by increasing the

value of the output capacitor.

In Fig. 6(f), the voltage and current waveforms of the boost

inductor can be seen. The Peak to peak current ripple of the

boost inductor has been chosen 20% of the peak input current.

To increase inductor value reduces current ripple and total

harmonic distortion.

In Fig. 7, the waveforms of current stresses of the auxiliary

switches can be seen. It is clearly that the proposed snubber

cell reduces current stress of the auxiliary switch dramatically,

so overall efficiency of the converter is higher than the

traditional ZVT boost converter [13].

Fig. 8 exhibits the power factor comparison for the different

line voltages. It can be observed that power factor at the low

line voltage or full load at any input voltage are near unity.

Fig. 4. Prototype circuit scheme of the proposed new ZVT-PWM-PFC boost converter.

Fig. 5. A photograph of experimental circuit of the proposed converter.

TABLE I

NOMINAL VALUES OF THE SEMICONDUCTORS USED IN THE PROTOTYPE OF

THE PROPOSED CONVERTER

Semiconductor

Devices V(V) I(A) rt(ns)

ft (ns) rrt(ns)

TB

(IXFH30N60P) 600 30 20 25 200

TS

(IXFH15N60P) 600 15 43 40 250

DB (DSEP8-

06B) 600 10 - - 30

D2,D4

(UF4005) 600 1 - - 75

D3 (UF4007) 1000 1 - - 75




When the voltage of the input is increased, the input current

decreases. This cause more current ripple so THD increases

and power factor decreases.

From Fig. 9 it can be seen that the efficiency values of the new

ZVT-PWM-PFC boost converter are much higher than that of

the hard switched converter and the traditional ZVT boost

converter. These efficiency values for hard switched, the

traditional ZVT and the proposed converters are obtained from

high precision power analyzer under same conditions and on

the same printed circuit board.

The overall efficiency of the proposed converter is measured

about 97.4% at nominal output power.

As a result, it can be clearly seen that the predicted theoretical

analysis and operation principles of the new ZVT-PWM-PFC

boost converter are experimentally verified.

VI. CONCLUSION

In this paper, a new ZVT-PWM-PFC boost converter is

presented for PFC applications. In the proposed new

converter, the main switch is turned-on perfectly with ZVT

and turned-off under ZVS. The auxiliary switch is turned-on

under ZCS and turned-off with ZVS. All diodes are operating

under SS. By using a transformer, during ZVT operation the

switching energies are transferred to the output, and so the

current stresses of the auxiliary components are significantly

decreased. Also, this transformer ensures the usage of

sufficient capacitors for ZVS turning off of the main and

auxiliary switches. The main switch and the main diode are

not subjected to any additional voltage and current stresses.

The auxiliary switch is not subjected to any additional voltage

(a)

(b)

(c)

(d)

(e)

(f)

Fig. 6. Main oscillograms of experimental circuit of the proposed converter. (a) Voltage (250V/div) and current (5A/div) of TB. (b) Voltage (250V/div) and current (10A/div) of TS. (c) Voltage (250V/div) and current (10A/div) of DB. (d) Voltage (250V/div) and current (10A/div) of the line. (e) Voltage (250V/div) and current (5A/div) of the output. (f) Voltage (250V/div) and current (5A/div) of the boost inductor LB

Fig. 7. Waveform comparison of the current stresses of the auxiliary switches.

Fig. 8. Power factor comparison for different line voltages and load conditions.

Fig.9. Efficiency curves of the proposed ZVT, traditional ZVT and the HS converters.




stress. Furthermore, the proposed converter can operate

successfully at all input voltage and output current values. The

new converter has a quite simple structure, ease of control and

low cost. In this study, a detailed steady state analysis of the

new converter has been done and this theoretical analysis has

been verified by a prototype with 100 kHz, 2 kW.

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Hacı Bodur (M’00) was born in Ordu, Turkey, in 1959. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Yildiz Technical University, Yildiz, Turkey, in 1981, 1983, and 1990, respectively.

He was employed as a Research Assistant from 1982 to 1986, a Lecturer from 1986 to 1991, an Assistant Professor from 1991 to 1995, and an Associate Professor from 1995 to 2002, in the Department of Electrical Engineering,

Yildiz Technical University, Turkey, where, since 2002, he has been a




Professor. He has published over 50 journal and conference papers in the area of power electronics. He also took part in more than 10 research projects concerning power electronics. His research has been concentrated on the areas of motor drives, power factor correction, uninterruptable and switching power supplies, high frequency power conversion, and active and passive snubber cells in power electronics.

Suat Yıldırmaz was born in Istanbul, Turkey, in 1984. He received B.S. and M.S. degrees in electrical engineering from Yildiz Technical University, Yildiz, Turkey, in 2006 and 2008, respectively, where he is working toward the Ph.D. degree in electrical engineering. During 2007-2012, he was a researcher with power electronics technologies group of the Scientific and Technological Research Council of Turkey. He has been working as a R&D

specialist for Aim Energy Technologies Co. since 2012. He has worked on many research projects concerning power electronics and signal processing both as a researcher and a project manager.

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