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A New Approach to Single Event A New Approach to Single Event Upset Testing of Complex FPGA Upset Testing of Complex FPGA Designs Designs Melanie Berg Melanie Berg NASA NASA Goddard Goddard Space Flight Center Space Flight Center Radiation Effects and Analysis Group Radiation Effects and Analysis Group Contributing Authors: Contributing Authors: Dan Gardner, Mentor Graphics Dan Gardner, Mentor Graphics Ron Press, Mentor Graphics Ron Press, Mentor Graphics Sponsors: Sponsors: NASA Electronic Parts and Packaging (NEPP) Program and NASA Electronic Parts and Packaging (NEPP) Program and Defense Threat Reduction Agency under IACRO# 06-4012I
Transcript of A New Approach to Single Event Upset Testing of Complex ... · A New Approach to Single Event Upset...
A New Approach to Single Event A New Approach to Single Event Upset Testing of Complex FPGA Upset Testing of Complex FPGA DesignsDesigns
Melanie BergMelanie BergNASA NASA GoddardGoddard Space Flight CenterSpace Flight Center
Radiation Effects and Analysis GroupRadiation Effects and Analysis GroupContributing Authors:Contributing Authors:Dan Gardner, Mentor GraphicsDan Gardner, Mentor GraphicsRon Press, Mentor GraphicsRon Press, Mentor Graphics
Sponsors: Sponsors: NASA Electronic Parts and Packaging (NEPP) Program andNASA Electronic Parts and Packaging (NEPP) Program andDefense Threat Reduction Agency under IACRO# 06-4012I
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 22
OverviewOverviewFPGA Radiation Testing: Objective is to FPGA Radiation Testing: Objective is to determine SEU/MBU susceptibility of:determine SEU/MBU susceptibility of:
General device operationGeneral device operationSpecific Design responseSpecific Design response
FPGA complexity has grown exponentially: FPGA complexity has grown exponentially: Testability and Testability and observabilityobservability are inversely are inversely proportional to design complexity.proportional to design complexity.Radiation Testing has become very expensive. Radiation Testing has become very expensive. Expense & Complexity: We are no longer able Expense & Complexity: We are no longer able to consider traditional methods of testing as to consider traditional methods of testing as conclusiveconclusiveScan Ring application has the potential to be an Scan Ring application has the potential to be an effective means to increasing Test coverage effective means to increasing Test coverage
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 33
AgendaAgenda
Complex Circuitry and Radiation TestingComplex Circuitry and Radiation TestingDesignDesign--forfor--test (DFT) and its application to test (DFT) and its application to FPGAFPGANASA/GSFC & Mentor design case studyNASA/GSFC & Mentor design case study
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 44
Complexity of Complexity of FPGAsFPGAs and and Testing Testing –– WhatWhat’’s the Issue?s the Issue?
Functional State space has exponentially increased: Functional State space has exponentially increased: Traditional Definition: 2Traditional Definition: 2#DFFs+IO#DFFs+IO
Space designs must include SEU mitigation and thus Space designs must include SEU mitigation and thus exponentially increases the verification/testing state exponentially increases the verification/testing state space:space:
22#DFFs+IO#DFFs+IO ?? 22#DFFS+IO+GateInputs#DFFS+IO+GateInputs
Definition of test coverage is generally not accurate for Definition of test coverage is generally not accurate for complex designs complex designs ……
DID YOU THINK OF EVERY CORNOR POINT?DID YOU THINK OF EVERY CORNOR POINT?Toggle metrics generally do not take into account all possible Toggle metrics generally do not take into account all possible combinationscombinations
Do you have the Do you have the timetime and and moneymoney to run several types of tests to run several types of tests with varying input test vectors???????with varying input test vectors???????
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 55
FPGA SubFPGA Sub--block Complexity: block Complexity: Xilinx ExampleXilinx Example
FPGAFPGA’’s are made s are made up of logic blocksup of logic blocksDesigns are Designs are mapped into the mapped into the preexisting logicpreexisting logicBlock complexity Block complexity (granularity) (granularity) gives the gives the designer more designer more flexibility:flexibility:
Too complex Too complex ––logic is unusedlogic is unusedToo simplistic Too simplistic ––Final area/power Final area/power may to too largemay to too large
Xilinx SubXilinx Sub--modulemodule
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 66
Radiation Testing: ConcernsRadiation Testing: Concerns
Single and Multiple bit Effects are difficult to Single and Multiple bit Effects are difficult to accurately observe and characterizeaccurately observe and characterize
Radiation Testing is ExpensiveRadiation Testing is ExpensiveCharacterization: Choosing design models that Characterization: Choosing design models that depict corner case behaviordepict corner case behaviorSingle/Multiple Event UpsetsSingle/Multiple Event Upsets
Functional complexity and maskingFunctional complexity and maskingClock cycles necessary for observed Fault propagationClock cycles necessary for observed Fault propagation
Basically comes down to maximizing Control Basically comes down to maximizing Control and Observation Points in a complex system and Observation Points in a complex system
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 77
Complex Circuitry and Radiation Complex Circuitry and Radiation TestingTesting: :
Traditional Methods of Device Traditional Methods of Device Characterization Characterization
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 88
Traditional Methods of Device Traditional Methods of Device CharacterizationCharacterization
N levels of single input logic
Q
QS E T
CLR
D
Q
QS E T
CLR
D
Q
QS E T
CLR
D
Q
QS E T
CLR
D
DUT Test Structure:DUT Test Structure:Shift RegisterShift RegisterVariable levels of Variable levels of combinatorial logiccombinatorial logic
Frequency Response Frequency Response TestsTests
Vary Test FrequencyVary Test FrequencyVary Data Input Vary Data Input FrequencyFrequencyVary Heavy Ion Vary Heavy Ion speciesspecies
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 99
FPGA Error Cross Section FPGA Error Cross Section Characterization Characterization –– Modeling & Modeling & Accuracy Accuracy
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
0 10 20 30 40 50 60 70 80
LET (MeV-cm2/mg)
12.5 MHz50 MHz100 MHzWeibull
No errors
AeroflexAeroflex Frequency Effects 4 Frequency Effects 4 Inverter Strings: DICEInverter Strings: DICE
No Statistical Difference with No Statistical Difference with Frequency VariationFrequency Variation
Actel Frequency Effects Varying Actel Frequency Effects Varying Inverter Strings: TMRInverter Strings: TMR
σσ Increase with Frequency Increase with Frequency VariationVariation
σse
u(c
m2 /
bit)
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1010
We Took it Further!We Took it Further!
More testing in May 2007More testing in May 2007Opposite of traditional theoryOpposite of traditional theoryAeroflexAeroflex inverters have too inverters have too small of a cross section to small of a cross section to characterize the frequency characterize the frequency effectseffects
Aeroflex Frequency Effects 20 Inverter Strings
0.00E+00
5.00E-09
1.00E-08
1.50E-08
2.00E-08
2.50E-08
3.00E-08
3.50E-08
4.00E-08
0 10 20 30 40 50 60 70
Frequency MHz
27.3 Mev*cm2/mg
19.3 MeV*cm2/mg
σσcmcm
22 /b
it/b
it
Error Cross Section decreases
Error Cross Section decreases
as Frequency increases!!!!!!
as Frequency increases!!!!!!
20 Inverters between each 20 Inverters between each DFFDFF
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1111
Complex Circuitry and Radiation Complex Circuitry and Radiation TestingTesting::
Fault Propagation & Functional Fault Propagation & Functional Masking Masking
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1212
Testing Complex Circuit: Fault Testing Complex Circuit: Fault PropagationPropagation
2 clock cycles2 clock cycles
4 clock cycles4 clock cycles
How long do we run a test????How long do we run a test????
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1313
Testing Complex Circuit: Testing Complex Circuit: Functional MaskingFunctional Masking
00
0 on node input:
0 on node input:
Error is Masked
Error is Masked
Will we ever see the error????Will we ever see the error????
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1414
ReiteratingReiterating…… Circuit Complexity Circuit Complexity and Testand Test--point point ObservabilityObservability
Duration of Radiation Tests are relatively short Duration of Radiation Tests are relatively short (compared to system ground tests)(compared to system ground tests)……
ExpensiveExpensiveVariations necessary:Variations necessary:
LETLETEnergyEnergyFrequencyFrequencyDeviceDevice
As we increase complexity, Testability and As we increase complexity, Testability and ObservabilityObservabilityis decreasedis decreasedDue to the complex nature of FPGA subDue to the complex nature of FPGA sub--blocks, we can blocks, we can no longer consider DFF and inverter data as conclusive.no longer consider DFF and inverter data as conclusive.How do we increase complexity but retain high levels of How do we increase complexity but retain high levels of observabilityobservability??
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1515
AgendaAgenda
Complex Circuitry and Radiation TestingComplex Circuitry and Radiation TestingDesignDesign--forfor--test (DFT) and its application to test (DFT) and its application to FPGAFPGANASA/GSFC & Mentor design case studyNASA/GSFC & Mentor design case study
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1616
Common MythsCommon Myths
FPGAsFPGAs are thoroughly tested by manufacturerare thoroughly tested by manufacturer
Common test coverage is complete (or good Common test coverage is complete (or good enough)enough)DonDon’’t add extra logic:t add extra logic:
DFT takes up too much areaDFT takes up too much areaDFT increases SEU susceptibilityDFT increases SEU susceptibility
Antifuse Example: Antifuse Example:
Nodes are tested at manufacturer Nodes are tested at manufacturer –– however, after programming the however, after programming the device, the electrical characteristics have changed. There is ndevice, the electrical characteristics have changed. There is no o guarantee that nodes are 100% functional (i.e. stuck at faults, guarantee that nodes are 100% functional (i.e. stuck at faults, speed, speed, increase in degradation process)increase in degradation process)
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1717
What is The Scan ProcessWhat is The Scan Process
It provides the ability to It provides the ability to load (control) every DFF within the Designload (control) every DFF within the DesignShift out (observe) every DFF within the DesignShift out (observe) every DFF within the Design
Utilizes alternate data flow paths Utilizes alternate data flow paths Scan mode vs. functional modeScan mode vs. functional modeCan place Can place DFFsDFFs in shift register chains (scan in shift register chains (scan mode)mode)
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1818
Scan Insertion ProcessScan Insertion Process
Q
QSET
CLR
D
combinational
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
Dcombinational
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
1
3
4
25
67
8
9
••Start with a designStart with a design
••Create alternate path containing only Create alternate path containing only DFFsDFFs: Shift Register: Shift Register
Shift data INShift data INShift data OUTShift data OUT
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 1919
Scan Test StructureScan Test Structure
Scan cells make sequential elements control Scan cells make sequential elements control and observe pointsand observe pointsDFFs replaced with scan DFFs replaced with scan cellscells
Scan cells concatenated into scan chainsScan cells concatenated into scan chains
Original
Flip-Flop
CLK
D Q
Replaced byMUX-D Scan Cell
SC_IN
CLK
D
SC_EN
Sout (Q)D
N_2
Q
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 2020
SEU Testing with ScanSEU Testing with Scan--Rings: Rings: Proposed MethodologyProposed Methodology
Determine starting state Determine starting state spacespace
ResetResetCustomCustom
Apply ResetApply Reset Load Load DFFsDFFs via via Scan Clock and Scan Clock and
Scan EnableScan Enable
Start Functional Start Functional ClocksClocks
Irradiate PartIrradiate Part
Stop Functional Stop Functional ClocksClocks
Shift out Shift out DFFsDFFsvia Scan Clock via Scan Clock
and Scan and Scan EnableEnable
Increase C
overage
Increase C
overage
Increase Increase Observability
Observability
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 2121
Scan and FPGA Scan and FPGA –– is it worth it ?is it worth it ?
Major advantage: Increases Major advantage: Increases control and observe pointscontrol and observe pointsIncreases test coverage while decreasing Increases test coverage while decreasing time necessary for testtime necessary for testTests for degradations causing timing Tests for degradations causing timing problems: potential at speed defectsproblems: potential at speed defectsProvides thorough diagnostics of failure root Provides thorough diagnostics of failure root cause (hone in on problem node)cause (hone in on problem node)Fault InjectionFault InjectionMajor Disadvantage: Adds logic and will Major Disadvantage: Adds logic and will increase Areaincrease Area
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 2222
AgendaAgenda
Radiation mitigation techniquesRadiation mitigation techniquesDesignDesign--forfor--test (DFT) and its application to test (DFT) and its application to FPGAFPGANASA/GSFC & Mentor design case study NASA/GSFC & Mentor design case study
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 2323
Test Chip Design: Actel Test Chip Design: Actel RTAX2000S deviceRTAX2000S device
Multiple functional blocks to test radiation effects and Multiple functional blocks to test radiation effects and mitigation techniquesmitigation techniquesTwo Designs implemented within the deviceTwo Designs implemented within the device
Multiple Multiple UARTsUARTs with large with large muxmux and and demuxdemux to created high to created high fanoutfanout and area usageand area usage–– 80 MHz clock80 MHz clockEDAC RAM EDAC RAM –– 40 MHz clock40 MHz clock
One version without ScanOne version without ScanSecond version with scan insertionSecond version with scan insertion
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 2424
Results are postResults are post--placement using ACTEL placement using ACTEL designer analysis toolsdesigner analysis toolsStatic Timing Analysis (STA) was preformed Static Timing Analysis (STA) was preformed on deviceon deviceScan insertion had little effect on frequency Scan insertion had little effect on frequency of operationof operation
ResultsResults
86MHz86MHz88MHz88MHz80MHz80MHzsys_clksys_clk
44MHz44MHz47MHz47MHz40MHz40MHzmem_clkmem_clk
Design with Scan Design with Scan InsertionInsertionOriginal DesignOriginal DesignTargetTargetClocksClocks
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 2525
Scan insertion adds one Scan insertion adds one muxmux per register, plus control per register, plus control logiclogic
RTAX2000S has about 2:1 CRTAX2000S has about 2:1 C--cell:Rcell:R--cellcellNeeded to force usage of internal Needed to force usage of internal muxmux within RCELLwithin RCELLUsing internal Using internal muxmux does not significantly add area does not significantly add area ……After After combining combining muxesmuxes into to the Rinto to the R--cellcell
Mentor Graphics DFT tool (DFT Advisor) indicated: Over Mentor Graphics DFT tool (DFT Advisor) indicated: Over 99% coverage of internal nodes99% coverage of internal nodes
ResultsResults
25,302 (78%)25,302 (78%)17,410 (81%)17,410 (81%)7,892 (73%)7,892 (73%)Design w/ Scan Design w/ Scan
Insertion *Insertion *
25,302 (61%)25,302 (61%)12,342 (57%)12,342 (57%)7,365 (69%)7,365 (69%)Design with Scan Design with Scan
Insertion **Insertion **
17,927 (56%)17,927 (56%)10,562 (49%)10,562 (49%)7,365 (69%)7,365 (69%)Original DesignOriginal Design
Total AreaTotal AreaCC--CellCellRR--CellCellDesignDesign
*Old version: did not force the usage of internal MUX within RCE*Old version: did not force the usage of internal MUX within RCELLLL
** New Version: Force RCELL MUX utilization when ever possible** New Version: Force RCELL MUX utilization when ever possible
A New Approach to Single Event Upset Testing of Complex FPGA DesA New Approach to Single Event Upset Testing of Complex FPGA Designs igns Melanie Berg: NASA/GSFC REAGMelanie Berg: NASA/GSFC REAGSingle Event Effects Symposium: Long Beach 2007Single Event Effects Symposium: Long Beach 2007 Page Page 2626
SummarySummary
Radiation Testing is very expensive and time Radiation Testing is very expensive and time limitedlimitedDue to the complexity of state of the art FPGA Due to the complexity of state of the art FPGA technology, traditional methods of SEU crosstechnology, traditional methods of SEU cross--section characterization/testing are no longer section characterization/testing are no longer conclusive.conclusive.Scan Ring Insertion provides an alternative Scan Ring Insertion provides an alternative approach to increasing control and observe test approach to increasing control and observe test pointspointsUtilizing Scan Rings can increase test coverage Utilizing Scan Rings can increase test coverage while decreasing necessary time for test.while decreasing necessary time for test.
