A Multi-Gate CMOS Compact Model – BSIMMG

Darsen Lu , Sriramkumar Venugopalan, Tanvir Morshed, Yogesh Singh Chauhan, Chung-Hsun Lin, Mohan Dunga,

Ali Niknejad and Chenming Hu

University of California , Berkeley

Acknowledgments

• Support– Semiconductor Research Corporation– IMPACT, UC Discovery and its industrial sponsors– SOITEC

• Test Chip Fabrication– Texas Instrument and ATDF– TSMC

• Technical Discussions– Wade Xiong (TI)

2

– Need thinner oxide to suppress leakage

in scaled CMOS

– Gate leakage is an issue!

Difficult to suppress leakage in scaled transistors

GateOxide

L

Source Drain

Path of Ioff

3

Solution: Multi-gate MOSFETs

GateOxide

L

Source Drain

– Leakage is suppressed by multiple -gates

– Scale body thickness instead of oxide thickness

OxideGate

4

Lg = 5 nm

Multi-gate Examples

5

F. Andrieu et al. VLSI 2010 (LETI / ST / IBM / SOITEC)

Tsi=7nmTbox=10nm

UT2BFinFET

X Huang et al., IEDM 1999 (UC Berkeley)

F.-L. Yang et al., VLSI 2004 (TSMC)

• Multi-gate FETs can extend CMOS scaling.

• BSIM-MG compact model has been developed.

65nm 45nm 32nm 22nmC

MO

S S

olut

ions

ENHANCED MOBILITY (StraiENHANCED MOBILITY (Strained Si)

65nm 45nm 32nm 22nm

HIGH -k / METAL GATEHIGH -k / METAL GATE

MG-FETMulti-gate

6

Outline

• BSIM-CMG: Common Multi-gate MOSFET Model

• BSIM-IMG: Independent Multi-gate MOSFET Model

• Modeling of Real Device Effects

• Experimental Verification

• Summary

7

Common -Multi-Gate Modeling• Common Multi-gate (BSIM -CMG):

– All gates tied together

– Surface-potential-based core I-V and C -V model– Supports double-gate, triple-gate, quadruple-gate,

cylindrical-gate; Bulk and SOI substrates– Physics-based model verified against TCAD and

measurements 8

Surface Potential Calculation (DG)

• Surface potential obtained by solving the 1D Poisson ’s equation

{2

2Body DopingInversion Carriers

chB BqVqφ qφqψi kT kT kT kT

Si

qnψe e e e

x ε

− −− −− −− − ∂∂∂∂ = ⋅ ⋅ ⋅ += ⋅ ⋅ ⋅ += ⋅ ⋅ ⋅ += ⋅ ⋅ ⋅ + ∂∂∂∂ 1 4 44 2 4 4 43

Vg

Vg

xn+ n+y

Vs VdNA

• A Perturbation approach is used to handle finite body doping

{ { {Net Surface Potential Inversion Carriers only Perturbation due to finite doping

inv pertψ ψ ψ= += += += +

M. V. Dunga et al.,TED 2006

9

• Model matches 2D TCAD very well without fitting parameters in both fullyboth fully --depleted and partiallydepleted and partially --depleted regimes.depleted regimes.

Surface Potential Calculation

0.0 0.4 0.8 1.2

-0.4

0.0

0.4

0.8Symbols : TCAD Lines : Model

Sur

face

Pot

entia

l (V

)

Gate Voltage (V)

Na = 1x1015

Na = 1x1018

Na = 3x1018

Na = 5x1018

10

• Drain current derived from drift diffusion

I-V Model & Verification

0.0 0.5 1.0 1.50

500µ

1m

Vg = 0.9V

Vg = 1.2V

Vg = 1.5V

Na = 3e18cm -3

Dra

in C

urre

nt (

A)

Drain Voltage (V)0.0 0.5 1.0 1.50

500µ

1m

Dra

in C

urre

nt (

A)

Gate Voltage (V)

Na = 3e18 cm -3

Vd = 0.1 Vd = 0.2 Vd = 0.4 Vd = 0.6

M. V. Dunga, UCB Ph.D. Thesis 11

Drain Current in Volume Inversion

In volume inversionvolume inversion Id TSi in sub-threshold.∝∝∝∝

M. V. Dunga, VLSI 2007 12

10µ10µ10µ10µ

Lines: ModelSymbols: TCAD

0.00 0.25 0.50 0.7510f

10p

10n

10µ Vds = 0.2V

Dra

in C

urre

nt (A

)

Gate Voltage (V)

Na = 1e15 cm -3

Tsi = 5nm Tsi = 10nm Tsi = 20nm

C-V Model Verification

• C-V model agrees well with TCAD without any fitting parameters.

• The transcapacitances exhibit the correct symmetry behaviors.

13

0.5 1.0 1.50.0

0.5

1.0

Cdg

Csg

Cgg

Na = 3e18cm -3

Vds = 1.5VSymbols : TCADLines : Model

Nor

mal

ized

Cap

acita

nce

Gate Voltage (V)

0.0 0.5 1.0 1.50.0

0.5

1.0

ModelSymmetry

Cgs

CgdCdg

Csg

Cgg

Na = 3e18Vg = 1.5V

Symbols : TCADLines : Model

Nor

mal

ized

Cap

acita

nce

Drain Voltage (V)

Independent Multi-Gate Modeling

• Independent Multi-gate (BSIM -IMG):– Separate Front- and Back-Gates– Asymmetric gate stacks: workfunction, T ox, …

– Physical surface-potential-based core I-V and C -V model agrees with TCAD without fitting parameters.

14

BOX

p-subP+ back-gate

Target device: BG -ETSOI or UTBB

Surface Potential

• Analytical Solution forΨΨΨΨs is known

• Newton iteration needed for ΨΨΨΨs calculation

• Approximation for front-, back -surface potential and charge developed– Better computational efficiency

Y. Taur, TED 2001H. Lu et al., TED 2006

VFG

VBG

S D

TOX1

TOX2

ΦM1

ΦM2

D. Lu, UCB Master’s Report

15

Surface Potential Verification

• Analytical Q S, ΨΨΨΨSFSFSFSF agrees with Exact Poisson Solution & TCAD without fitting parameters.

• Scalability of the model is demonstrated.

Symbols: TCAD Lines: ModelSymbols: Exact Poisson Lines: Model

16

-0.5 0.0 0.5 1.0

0.0

0.5

1.0

Cha

rge

Den

sity

(C

/m2 )

Sur

face

Pot

entia

l (V

)

Front Gate Voltage (V)

Vch = 0.0V Vch = 0.3V Vch = 0.6V

0.00

0.02

0.04

-0.5 0.0 0.5 1.0

0.0

0.3

0.6

Tsi = 5 nm Tsi = 10 nm Tsi = 15 nm Tsi = 20 nm

Sur

face

Pot

entia

l (V

)

Front Gate Voltage (V)

Tox1=Tox2=1.2nmTsi=10nmVbg=0

0.0 0.3 0.6 0.9-200

-100

0

100

200

300

Vfg = 0.5V

Symbols: TCADLines: Model

Cap

acita

nce

(fF

)Drain Voltage (V)

Cfg,d Cfg,s Cfg,fg

-0.3 0.0 0.3 0.61E-12

1E-10

1E-8

1E-6

1E-4

Vds = 50mV

Symbols: TCADLines: Model

Dra

in C

urre

nt (

A)

Front Gate Voltage (V)

Tox2 = 40nmTox2 = 20nmTox2 = 10nmTox2 = 5nmTox2 = 2.5nm

• Physical I-V and C -V model agrees well with TCAD• Transcapacitances exhibit correct symmetry

Core I-V and C -V Model

Model SymmetryTox1=1.2nm Tox2=40nmTsi=15nm Vbg=0

D. Lu et al., IEDM 2007

17

Real-Device Effects Modeled

• Quantum effects (charge centroid model)• Short Channel Effects -- Vth roll-off, Sub-threshold swing

degradation, DIBL, CLM• Mobility Degradation• Velocity Saturation• GIDL, GISL and Junction Leakage• Gate Tunneling Current• Temperature effects• Parasitic Capacitance• Series Resistance• Etc.

18

Short Channel Effects

Vth Definition: Ith = 300nA * W / L

- Z. Liu et al., TED 1993

Symbols: MeasurementsLines: Model

SS: Subthreshold Swing19

0.1 160708090

100110120

Vds = -1.0V

SS

(m

V/d

ec)

Gate Length (µm)

0.1 1

60

70

80

90

100

110

SS

(m

V/d

ec)

Gate Length (µm)

Vds = -50mV

0 .1 1

-0 .4

-0 .3

-0 .2

-0 .1

0 .0

V d s = -5 0 m V V d s = -1 .0 V

Thr

esho

ld V

olta

ge (

V)

G a te L e n g th (µ m )

Scale Length for Various Modes

• Double-gate

• Triple-gate

• Cylindrical-gate

• Independent-gate

20

- K. Suzuki et al., TED 1993

Leakage path at front surface

Leakage path in the center

Temperature Effects• Temperature dependence are well-modeled

– Mobility temperature dependence: U0(T), UA(T)– Saturation Velocity temperature dependence: VSAT(T)– Subthreshold Swing = nkT/q– GIDL Leakage: BGIDL(T) – A few others

21

Symbols: SOI FinFET dataLines: Model

Vds=1.0

0.0 0.2 0.4 0.6 0.8 1.00

200

400

600

800

1000

1200

1400

LG

=60nm

20 fins

-50C --> 200C in s teps o f 50C

Increasing T

Dra

in C

urre

nt (

µA)

G a te V o ltage (V )-0.4 -0.2 0.0 0.2 0.4

1E-12

1E-9

1E-6

1E-3

LG=60nm

20 fins

Increasing T

-50C --> 200C in stepsof 50C

Gate Voltage (V)

-3.0 -2.0 -1.0 0.00.0

0.2

0.4

0.6

0.8

VDS

= 50mV

Symbols: TCAD Lines: Model

Thr

esho

ld V

olta

ge (

V)

Back Gate Bias (V)

LFG

= 45 nm

LFG

= 22 nm

LFG

= 13nm

0.01 0.1 1

0.18

0.20

0.22

0.24

Gam

ma

(γ)

Gate Length (µm)

TCAD Model

Vds = 1V

Length Dependent γγγγ Model for Independent-gate

22

Gamma definition:

Capacitance network analysis:

Front Gate

Back Gate

Source / Drain

Cox1

Csi

Cox2

Cd1(Leff)

Cd2(Leff)

Tsi=8nm

Tbox=4nm

γγγγ degradation for short channel:

SOI FinFET Global Parameter Extraction

• FinFET with LG = 1µµµµm, 235nm, 95nm, 85nm, 75nm H fin=60, Tfin=22, 20 lightly-doped fins D. Lu et al., SISPAD 2009 23

0.0 0.2 0.4 0.6 0.8 1.00.0

0.3

0.6

0.9

1.2

Gate Voltage (V)

Vds = 1.0 V

Decreasing L

Dra

in C

urre

nt (

mA

)-1.0 -0.8 -0.6 -0.4 -0.2 0.0

0.0

0.3

0.6

0.9

1.2

1.5

Dra

in C

urre

nt (

mA

)

Gate Voltage (V)

Vds = -1.0 V

Decreasing L

0.0 0.2 0.4 0.6 0.8 1.00.00

0.05

0.10

0.15

0.20

0.25

Decreasing L

Vds = 50mV

Dra

in C

urre

nt (

mA

)

Gate Voltage (V)-1.0 -0.8 -0.6 -0.4 -0.2 0.0

0.00

0.05

0.10

0.15

0.20

0.25

Decreasing L

Vds = -50mV

Dra

in C

urre

nt (

mA

)

Gate Voltage (V)

0 0.5 1.01p

1n

1µ

1mLg = 1 µµµµm

V g = 1 .0 - 0 .2V

Out

put C

ondu

ctan

ce (

S)

D rain Vo ltage (V )0.5 1.0

0

20

40

60

Vd = 1 V

Vd = 50mV

Lg = 1 µµµµm

gm E

ffici

ency

, gm/I d (

V-1)

Gate Voltage (V)

Analog metrics (SOI FinFETs)

• Analog metrics ( gm/Id and gds) for the long channel are also captured well.

gm Efficiency ( gm/Id) Output Conductance

24Dunga et al., VLSI 2007

0.0 0.4 0.8 1.20

25µ

50µ

Vd = 1.2V

Vd = 50mV

Lg = 50nm

Dra

in C

urre

nt (

A)

Gate Voltage (V)

1p

1n

1µ

1m

0.0 0.4 0.8 1.20

25

50Vg = 1.2 - 0.4V

Lg = 50nm

Dra

in C

urre

nt (

µµ µµA)

Drain Voltage (V)0.0 0.4 0.8 1.2

1p

10p

100p

Vd = 1.2V

Lg = 50nm

Bul

k C

urre

nt (

A)

Gate Voltage (V)

Short Channel Bulk FinFETs�Model is used to describe bulk FinFET

technology also.

�Substrate Current: Impact Ionization

IdId--VgVg IbIb--VgVgIdId--VdVd

25Dunga et al., VLSI 2007

Validation of BSIM -IMG Model

� Global parameter extraction

� 22nm ETSOI technology (IBM)

� Ids for NMOS and PMOS

� Lg = 24.5nm … 66nm

� Model extracted using ICCAP

� Parasitic capacitances calibratedto mixed-mode TCAD

26

ETSOIK. Cheng et al. IEDM 2009(IBM / ST)

27

Gummel Symmetry Test• Ids continuity at V ds=0 is verified through the

Gummel symmetry test.• Both BSIM -CMG and BSIM -IMG passes this test

Results shown here are 1 st & 3rd order derivativesof Ids for BSIM -IMG

-0.2 -0.1 0.0 0.1 0.20

20

40

60

dId /

dVx (

mS

)

Gummel Test Voltage Vx (V)

Vfg = 0.0 Vfg = 0.2 Vfg = 0.4 Vfg = 0.6 Vfg = 0.8 Vfg = 1.0

-0.2 -0.1 0.0 0.1 0.2-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

d3 I d

/ dV

x3 (A

/ V

3 )

Gummel Test Voltage Vx (V)

Vfg = 0.0 Vfg = 0.2 Vfg = 0.4 Vfg = 0.6 Vfg = 0.8 Vfg = 1.0

Summary• Core I-V and C -V models for common and independent

multi-gate FETs are developed and verified with TCA D without using fitting parameters

• Volume inversion and the effect of finite body dopi ng are captured.

• BSIM-like real device effects are implemented.

• BSIM-CMG is calibrated to an SOI FinFET technology and a bulk FinFET technology. Short channel effects, temperature dependence, GIDL leakage, substrate cur rent and analog metrics agree well with data.

• BSIM-IMG is also calibrated to an ETSOI technology with good agreements. 28