co

n,

96,

Current mode

DCDC converter

-mo

ove

itho

dra

ula

th

peri

ot v

erte

g s

is 8

& 2012 Elsevier Ltd. All rights reserved.

Dynamppliedof SoCm [1,tive Dhe fasttart-updifferee DCDference

[9,10]. However, the compensation capacitor still limits the raise of

forward only a few years ago. The maximum current charge method

/PSMused. Theation

are introduced in Section 2. Measurement results are shown in

Contents lists available at SciVerse ScienceDirect

.elsevier.com/locate/mejo

Microelectron

Microelectronics Journal 44 (2013) 128136chip. The peak current mode control is adopted in this converter.E-mail address: swffrog@seu.edu.cn (W. Sun).is used in the up-tracking to increase the tracking speed [4]. But the

2. Circuit descriptions

Fig. 1 shows the proposed block diagram of the developed

0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved.

http://dx.doi.org/10.1016/j.mejo.2012.12.004

n Corresponding author. Tel.: 86 25 83795811; fax: 86 25 83795077.the slew rate. The concept of reference tracking speed has been put Section 3 and the conclusion is made in Section 4.to settle down after the large load transient. It will get worse when itdelivers power to a high dynamic processor. Therefore someresearchers adopted on-chip re-congurable Miller capacitor toimprove the transient response performance with variable slew rate

overshoot voltage and inrush current. In addition, the PWMdual mode with DPSS (dynamic partial shutdown strategy) isto obtain high conversion efciency in a wide load rangestructure of the proposed converter and circuits implementbang-controlled is adopted to reach the fast load transient responsedue to a wide bandwidth of the converter loop [6]. However, theswitching frequency is variable, and output voltage ripple is high.A linearnon-linear control is proposed [7,8], but the transitionbetween linear and nonlinear is not smooth, which makes it difcult

fall slowly. And the converter is forced to work in PWM modewhen the output voltage changes. The tracking speed can beincreased without overshoot voltage. A fast novel circuit withsimple D/A (digital-to-analog) converter and variable minimumduty cycle is proposed to apply variable output voltage without1. Introduction

In recent years, the high speed(DVS) method has been widely asystems, such as the power supplyincrease the efciency of the systemodules to achieve DVS is the adapshould contain the characteristics of tthe fast tracking speed and the fast s

Many researchers have proposedthe fast response characteristic of ththe load transient response and reic voltage schedulingin portable electronicor power amplier, to2]. One of the criticalCDC converter, whichload transient response,speed [35].nt methods to improveC converter, especiallytracking speed. Bang-

overshoot voltage will be introduced. Besides, for down-tracking,only the load path discharges the charge of output capacitor.Unfortunately, few people focus on decreasing the start-up time.The conventional soft-start-up circuits need an external capacitor ora large resistance on chip to regulate the soft-start-up time and thepiecewise limited current to eliminate the inrush current [4,11,12].Then the overshoot and inrush current can be suppressed. But thetime is very long. It needs millisecond timescale generally.

In this paper, the converter loop without the large compensa-tion capacitor is proposed to enhance the transience response.The recovery time is decreased dramatically. The up counter anddown counter are adopted to make the reference voltage rise orA monolithic peak current-mode buckfor high speed DVS application

Miao Yang, Weifeng Sun n, Shen Xu, Changbing Qi

National ASIC System Engineering Research Center, Southeast University, Nanjing 2100

a r t i c l e i n f o

Article history:

Received 4 June 2012

Received in revised form

4 December 2012

Accepted 10 December 2012Available online 2 January 2013

Keywords:

Fast transient response

Fast tracking

Soft-start-up

Current sensing

a b s t r a c t

A monolithic peak current

presented in this paper. A n

inrush current. The loop w

error amplier, which can

automatic pulse width mod

conversion efciency during

0.13 mm CMOS process. Exinrush current and oversho

changes 300 mA. This conv

application. The up-trackin

Measured power efciency

journal homepage: wwwnverter with fast response

Shengli Lu

China

de step-down DCDC converter with fast response for DVS application is

l fast on-chip soft-start circuit is used to reduce the overshoot voltage and

ut large capacitor compensation is adopted to increase the slew rate of the

matically decrease the transient response time of the system. Meanwhile,

tion (PWM) and pulse skip modulation (PSM) switching are used to improve

e wide load range. The DCDC converter has been fabricated with a standard

mental results show that the start-up time is less than 50 ms without theoltage. The recovery time is less than 8 ms while the load current suddenlyr can operate at 1.5 MHz with output voltage from 0.725 V to 1.5 V for DVS

peed is about 31.25 ms/V and down-tracking speed is about 21.75 ms/V.4.293.8% for 1400 mA load current.ics Journal

It contains a power stage, control circuit, voltage setting circuitsand soft-start-up circuits. Voltage setting circuits, including theresistance network and the OPA (operational amplier), generatethe expected setting voltage VSET for the input of the erroramplier in control circuits. The control circuits contain the EA(error amplier), PWM modulator, current sensor, slope compen-sation, PWM/PSM digital circuits, buffer and some comparatorsthat are shown in Fig. 1. It supplies appropriate duty cycle for thedifferent output voltages Vout. The soft-start-up circuits areadopted to suppress the overshoot voltage and inrush current atthe start-up phase of the converter.

At moderate to heavy loads, the converter operates in PWMmode in order to increase the conversion efciency in general.The SR latch is included in the digital control circuits as shown inFig. 1. The clock pulse at the input of the SR latch initiates theswitching period. The off signal of the PMOSFET Mp is supplied bythe output of the modulator. If the inductor current is larger thanthe limited current, the limited current comparator will ip toturn off the Mp too.

With decreasing load current, the converter automaticallyswitches into PSM mode. The inductor current zero crossing pointacts as the condition of PWM mode switch to PSM mode at thedecreased phase of inductor. In order to increase the conversionefciency, the low side NMOSFET MN will be turned off when theinductor ramps zero. Once the current crosses zero, the PWMcontrol loop will be cut off. The DPSS method is used in the

setting circuit. For example, when we want the output voltage tochange from 0.725 V to 1.5 V, the data register should be changedfrom 5b00000 to 5b11111. If the data suddenly change, over-shoot voltage would be generated. Therefore the up counter ordown counter are used in the converter, respectively, in order tomake RNET increase or decrease slowly. From Fig. 1, the equationof the VSET can be obtained as follows:

VSET 1RNETRF

VREF 1

Then VSET will rise or fall slowly. So the output voltage Vout can bechanged smoothly. The frequency of counter decides the trackingspeed of VSET. The converter is forced to work in PWMmode whenthe VSET changes. Therefore, the up/down tracking speed canincrease without overshoot and undershoot. The design of thecounting frequency can refer to the design method of the frequencyof the D/A in the soft-start-up circuits, which will be discussed inthe following.

2.1. On chip fast soft-start-up circuits

The proposed soft-start-up circuits contain two sections: over-shoot suppression circuit (Fig. 2) and inrush current suppressioncircuit (Fig. 3). In Fig. 2, the transistors M2, M3, OPA and resistancenetwork are used to set a variable reference voltage VSET asmentioned above. The gate voltage of transistor M1 is supplied

M. Yang et al. / Microelectronics Journal 44 (2013) 128136 129structure [4]. Many modules are disabled such as the PWMmodulator, current sensor, and error amplier. The output voltageVout decreases slowly, depending on the discharge speed of theoutput capacitance C as shown in Fig. 1. When the voltage is lessthan VSET, a constant value, the output of the voltage comparatorwill switch at once. Then the system starts the PWM loop again,which will be forced to work ten cycles. So the inductor currentzero crossing point will be sensed again. If the inductor currentcan not decrease to zero, the system will switch to the PWMmode. Otherwise, the system works in PSM mode.

In addition, the implementation of dynamic output voltagechange depends on the data register by I2C interface in the voltageFig. 1. Structure of propoby the output of 6-bit D/A converters slowly. However, the gatevoltage of the transistor M2 has been xed at VREF, which is largerthan the gate voltage of M1. So at the initial phase of start-up, M2is cut off for the reason that the drain current of M1M3 alwaysmeet

IM1 IM2 IM3 2Because of the virtual short characteristics of operational ampli-er, the gate voltage of the transistor M3 will increase by the gatevoltage of the transistor M1 rising. IM1 will decrease and IM2 willincrease. When the gate voltage of the transistor M1 rises to acertain value, the transistor will be cut off. At this time, IM2 IM3.sed buck converter.

3M. Yang et al. / Microelectronics Journal 44 (2013) 128136130DCLKEN

Q_

Q

DCLKEN

Q_

Q

DCLKEN

Q_

Q

DCLKEN

Q_

Q

D/A

QQ2Q1Q0

Q0Q2Q3Q4Q5Q6

Q1VREF

EN

M1 M2The soft-start-up of the setting voltage is completed successfully.Therefore the Vout will rise following the setting voltage VSETand avoid the overshoot voltage. This method can be applied toset different voltage values. The clock frequency CLKRAMP of theD/A converter decides the start-up time. If the ideal fastestcondition is considered, the system will work using maximumduty cycle up to a limited current Ilimited and then work usingIlimited until output voltage becomes stable. Therefore the fastesttime is

trise IlimitedL =V inRloadC ln VoutRloadC

Ilim itedC

ln Ilimited

C

3In the proposed circuit, the rise time of VSET is designed slightlylonger than trise to get better and faster Vout start-up wave withoutovershoot voltage.

In order to prevent the power MOSFET from being excessivelyon and avoid ip error of PWM modulator or limited currentcomparator by the switch noise disturbance, the minimum dutycycle is used in DCDC converter. The minimum duty cycle ismade as big as possible on the premise of the input and outputvoltage range. At the time of start-up, though the limited current

R1

Fig. 2. Overshoot sup

Vmodulator_out

Mux2-1

VREF1

Vout Comparator

CLKNORMALCLKSTRAT

Vlimited_out

CLKNORMALCLKSTRAT

Fig. 3. Inrush current sDCLKEN

Q_

Q

DCLKEN

Q_

Q

DCLKEN

Q_

Q

_

Q6Q5Q4

OPA

RF

RNET

VSET

CLK1

M3

DCLKEN

Q

Qcomparator is adopted, it is invalid at the time of minimum powerof MOSFET. Therefore the system will still generate inrushcurrent. The charge slope of the inductor is Kup_slope(VinVout)/L, and the discharge slope is Kdown_slopeVout/L. It is obviousthat charge slope is much larger than discharge slope at theincipient stage of Vout rising. The inductor current will exceed thelimited current value after several cycles. Fig. 4(a) is the simu-lated result when the constant minimum duty cycle is adopted. Itis obvious that the inrush current still exists.

In the proposed converter, the variable minimum duty cycle isadopted, which means that several clock cycles will be shielded atthe beginning of start-up. When the system meets some condi-tions, it will change the minimum duty cycle. The dividing point isdecided by VREF1 in Fig. 3, as follows:

V inVREF1 DminTs=L VREF1 1Dmin Ts=L 4

where Dmin is the minimum duty cycle of the steady stage. WhenVout is less than VREF1, the system uses smaller duty cycle andslower clock CLKSTART. After several clocks, the charge energy anddischarge energy of the inductor will be equal at one cycle. Thenthe clock CLKNORMAL is adopted in the system. The simulation

ResistanceNetworkR2

pression circuit.

BufferCKP

CKN

uppression circuit.

the EA design in order to make the common output not affectedby the variable common input. In addition, the switching noisecoupled from output node can be ltered out easily. Thus, a nearlynoiseless error signal is derived through this structure [14]. TheEA is composed of transistors M1M10 and resistances R1R4.TheDC gain of the EA is expressed as

Tc gm1gm5R1R3 7

The PWM modulator is composed of transistors M12M18,resistances R5R6 and a comparator. The current sensing signaland slope compensating signal are necessary in the peak currentmode converter. The high accuracy current sensor will be ana-

ons

Fig. 5. Bode plots comparison between conventional loop and proposed loop.

M. Yang et al. / Microelectronics Journal 44 (2013) 128136 131results are shown in Fig. 4(b). The inrush current can be avoideddue to this design method.

2.2. Error amplier and PWM modulator

In order to design the peak current mode buck converter, theloop design consideration is reported [13]. When the outervoltage loop is open and inner current loop is closed, the looptransfer function Ac from the control voltage Vc(s) to the outputvoltage Vout(s) is

Ac RloadRS

1

1 RloadTsL mcD00:5 1sCrc

1 swp1

1 swnQ s2

wn2

5

where, D1D, mc1Se/Sn, wp 1=CRloadTs=LC mcD00:5

,Q1/p(mcD0 0.5), wnp/Ts, and D, Se, Sn, Rload, Ts, RS stand forthe duty cycle, the slope of the compensation ramp signal, the riseslope of inductor current, load resistance, switch frequency andcurrent sampling resistance, respectively. When the outer voltageloop and inner current loop are all closed, the loop transferfunction

T loop TcAc 6where Tc is the transfer function of the EA. In conventional design,the zero in Tc is in order to compensate the pole wp in Ac. A polemust be generated by TC as the main pole in the loop. Howeverthis design not only introduces large RC compensation, but alsolimits the slew rate of the EA. Therefore the response speed is

.51.5

I L(A

)V

out(V

)

0

0.51

1.5

2.5

-.25.25.75

1.25

.5

1.01.25

3.5

CLK

(V)

VS

ET(

V)

Ilimited

00

Time(s)110 220 330 440 50

Fig. 4. Simulated results of start-up VSET, Vout IL and CLK for (a) climited at this condition.Based on the above analysis, a loop without the large capacitor

compensation design method is proposed. In the EA, the RCcompensation is not considered. Bode plots comparison betweenconventional design and proposed design is shown in Fig. 5. Theproposed loop has the same bandwidth as that of the conven-tional loop with large capacitor compensation. The only differ-ence with the conventional loop is the loop gain at a lowfrequency. The proposed loop adopts lower loop DC gain to keepthe system stable as shown in Fig. 5. The DC gain of loop isdecreased. So the load regulation performance will be sacricedslightly. However, the DC offset of the output voltage is veryclearly not due to the small load current. It is obvious that 3 dBof loop has increased by this method. So the response of loop isimproved. The frequency response simulation results of theproposed loop are shown in Fig. 6. The loop width is about360 kHz and the phase margin is about 421. The system can bekept stable under different load conditions.

The circuits of EA and PWMmodulator are shown in Fig. 7. Thedifferential-input and differential-output scheme is adopted inI L(A

)V

out(V

)C

LK(V

)V

SE

T(V

)

Ilimited

01234

0.51

-.5

0.51

1.5-.25.25.75

1.25

00

Time(s)

110 220 330 440 50

tant minimum duty cycle and (b) variable minimum duty cycle.

Conventionalloop

Proposedloop

Loopgain(dB)

w (Hz)wc0lyzed in detail in the next section. In the proposed EA andmodulator circuits, simple circuits are used to achieve thecomposition of signals and the generation of constant commonoutput of the error amplier as shown in Fig. 7. It can be obtainedthat

Vn VeaoVgs17 I12 I13 R5 8

Vp Veao Vgs18 I14R6 9

And the aspect ratios of M11 to M14, M12 to M15, M13 to M16,and M17 to M18 are equal. M17 and M18 work in the saturationregion. So Vgs17 will be equal to Vgs18. If VpVn is assumed, thenVeaoVeao I14R6 I12 I13 R5 10

Therefore the value of I14R6 is equal to the common output of theEA and would not be changed by the variable common input ofthe error amplier. Fig. 8 shows the simulation contrast resultsbetween the proposed loop and conventional loop. It is obviousthat the proposed loop has faster transient response. The recovery

(360kHz,0dB)

M. Yang et al. / Microelectronics Journal 44 (2013) 128136132Mag

nitude(dB)time for a 300 mA step load transient is only 2 ms and the outputvoltage drop is about 5 mV.

2.3. Current sensor

There are mainly two derivational structures in emergentpapers based on an American patent [15]: one uses operationalamplier to clamp the voltage of the drain of sensing MOSFET andpower MOSFET [16,17]; the other employs current mirror to makethe voltage equal to them [18,19]. Both of these schematics

hase(degree)

Phase(degree)

Freque

Fig. 6. Frequency response simulation results of

Fig. 7. Error amplier and P

Time(s)75 100 125 150 175

1.18

1.22

0

400

Vou

t(V)

I load

(mA

)

100mA

400mA

2s

12mV9.6s

5mV

9.5s

12m V5mV

Vout1

Vout2 2s

Fig. 8. Load transient response comparison between Vout1 (conventional loop) andVout2 (proposed loop) with load current step between 100 mA and 400 mA.neglect the effect of the clamping current, which can introducea term in the current sensing expression and result in inaccuratesensing current especially at large sensing ratio with small

(360kHz,-138)

ncy(Hz)

the proposed loop (Vin3.3 V, Vout1.2 V).

MW modulator circuits.

CKP

CKP CKPCKP CKP

CKN

MP

M1

MNM2

M3

M4

M5

M6

M7

M8

M9

MSM10

M11

M18

I1

C

rc

L

RSEN

Vin

VAVB

VCIclamp

M12

M13 M14

MB1

MSW

M15 M16 M17

ICS

Rload

Fig. 9. Proposed current sensing circuit.

current sensing. In this converter, the appropriate aspect ratio ofthe transistor MSW and several series MOSFET are used to solvethe problem of clamping current error to achieve high accuracy ina wide load range, which can be seen in Fig. 9. The principle ofoperation will be described in detail as follows.

When the clock signal CKP is low, the transistor MS is on. TheMOSFET MS is composed of the three cascade transistors M10M12. The series association of three transistors has a trans-conductance-to-output conductance ratio as high as that of along-channel transistor but a shorter physical channel length.Hence, the composite transistors have a cutoff frequency higherthan the cutoff frequency of its Dc equivalent long-channeltransistor [20]. The other advantage is that the equivalent gatelength of MS and the switch MSW get triple length of signaltransistor. The match of the two transistors will become better, sothe sensing current will be better. If the relationship of the aspectratio of MS to MP is designed as 1:K, K is designed as 16,000 todecrease the work current of the current sensor, in order to make

are shown in Fig. 10. The current sensing has enough band-width to make ICS wave follow IL well. This sensing circuit has awide current sensing range with high accuracy as shown inFig. 11. The minimum accuracy and the maximal accuracy are

I CS(

A) 5

67

43

I L(m

A)

-100

100150

-500

50

Fig. 11. Simulated accuracy of the proposed sensing circuit for load current from50 mA to 400 mA and Vin3.3 V, Vout1.2 V.

Fig. 12. Chip microphotograph of the proposed converter.

M. Yang et al. / Microelectronics Journal 44 (2013) 128136 133the sensing current proportionally copy the inductor currentprecisely. The relationship between the actual sensing currentand the drain of MP should be as follows:

K IPICS

12mPCox

WMPLMP

2VSG_MP9VTP9VSD_MPV2SD_MP 12mPCox

WMSLMS

2 VSG_MP9VTP9

VSD_MSV2SD_MS

Iclamp WMP=LMPWMS=LMS

11If the highest order terms of Eq. (11) are neglected, the necessaryand sufcient condition of Eq. (11) is

2 VSG_MP9VTP9

VSD_MP

2 VSG_MS9VTP9

VSD_MSIclamp

12mpCox

WMSLMS

1 12

The transistors M13, M14, M16, and M17 and compose a common-gate amplier to make the potential of VA equal to the potential ofVB. Besides, M15M17 have equivalent aspect ratios. Therefore, thedrain currents of M15 and M16 are equal to the clamping currentIclamp. Then Eq. (12) becomes

2Iclamp

mpCox VSG_MSW9VTP9 WMSW

LMSW

IclampmpCox VSG_MS9VTP9

WMSLMS

13

The source of the switch MSW is connected to the drain of MP,not the power Vin. The sourcegate voltage of the switch MSW isless than the sourcegate voltage of MS. When the aspect ratio ofthe switch MSW is adopted to be slightly larger than and close totwo times the aspect ratio of MS, the clamping current error canbe eliminated. Simulated results of IL, ICS at different currents

Time(s)44 45 46 47 48

I L(mA)

100

150

200

250

300

I CS(A)

0

5.0

10

15

20Fig. 10. Simulated results of IL, ICS for (a) Vin3.3 V, Vout1.2 VTime(s)

0

21

44 45 46 47 48, Iload200 mA and (b) Vin3.3V, Vout1.2 V, Iload50 mA.

94% and 99.2% for load current from 50 mA to 400 mA, respec-tively. Therefore this current sensing circuit can be applied in theproposed converter to ensure high performance.

3. Experimental results

The proposed buck converter shown in Fig. 1 has beenimplemented in the SMIC CMOS 0.13 mm process. The converteris designed to provide variable output voltage and fast responsefor SoC DVS application. Fig. 12 shows the micrograph of the chip,the area of which is only 2.24 mm2, including I2C communicationinterface and bonding PADs. The widths of the power MOSFET MPand MN are 24,860 mm and 7810 mm, respectively. And thelengths of them are all 0.35 mm.

IL

C1

C2

20s/div

43s

1V/div

200mA/div20s/div

Vout

IL

Vout

C1

C2

43.5s

20s/div 1V/div

200mA/div20s/div

Fig. 13. Measured output voltage Vout (Channel 1) and inductor current IL (Channel 2) during the start-up process for (a) no-load and (b) Iload200 mA.

IL

VPgate

C1

C2

0.5s/div 2V/div

0.5s/div 200mA/div

1V/div

IL

VPgate

C1

C2

0.5s/div

0.5s/div 200mA/div

inductor current IL (Channel 2) for (a) duty cycle o50% (Vin3.3 V, Vout0.725 V) and

LX

VoutC1

C2

C3

VLX0.5s/div

IL

4mV

10mV/div

1V/div

200mA/div

0.5s/div

0.5s/div

C1

C2

VSET 19.5s

19.8s 25s

19.5s

20s/div 0.5V/div

20s/div 0.5V/div

Vout

Fig. 16. Measured reference tracking response with Iload200 mA: Vout (Channel 1);VSET1.5 V-0.725 V-1.5 V (Channel 2).

M. Yang et al. / Microelectronics Journal 44 (2013) 128136134C2

C3

20s/divIL

1V/div100mA/div20s/divFig. 14. Measured steady-state waveforms of MP gate voltage VPgate (Channel 1) and(b) duty cycle450% (Vin2.7 V, Vout1.5 V).

C1

V20mV/div

22mV

20s/div

VoutFig. 15. Measured steady-state waveforms of output ripple voltage Vout (Channel 1 AC coupled); switch node LX voltage VLX (Channel 2); inductor current IL (Channel 3) for(a) Iload50 mA and (b) Iload150 mA.

Fig. 13 shows the measured output voltage and inductorcurrent during the start-up with noload and 200 mA load.Experimental results can match the analysis results, which cannot induce overshoot voltage and inrush current. And the start-uptime is less than 45 ms. Fig. 14 shows the steady-state wave-forms of Mp gate voltage and inductor current under different

conditions. It can be seen that the proposed converter can bestable for all output voltages. Fig. 15 shows the steady-statewaveforms of output voltage at different load currents. From thegure, the ripple voltage is 22 mV when the system works in PSMmode and the ripple voltage is only 4 mV when it works inPWM mode.

The reference tracking response of output voltage is shown inFig. 16. When the set voltage VSET changes between 1.5 V and0.725 V, the output voltage can follow VSET better without over-shoot and undershoot. The down tracking speed is 24.75 ms/V andup tracking speed is 31.25 ms/V. The converter load transientresponse is shown in Fig. 17. The recovery time for a 300 mA stepload transient is 8 ms more or less and the output voltage drop isonly 8 mV. These results can approach the simulated results. Theadvantage of the proposed loop can be proved from the measuredload transient response results.

The proposed converter incorporated with DPSS adopting thePWM and PSM mode gives high conversion efciency in a wide

Iload

C1

C2 100mA/div

(7.8s,8mV) (8s,8mV)

10mV/div20s/div

20s/div

Vout

Fig. 17. Measured load transient response with load current Iload (Channel 2) stepbetween 100 mA and 400 mA of the output voltage Vout (Channel 1).

Fig. 18. Measured conversion efciency for Vin3.3 V and Vout1.5 V.

Table 1Performance comparison.

[3] [4] [

Technology (mm) 0.35 0.6 0Efciency (%) 8894.5 8296.7 7

Input voltage range (V) 3 2.26 1

Output voltage range (V) 0.52.5 0.6(Vin0.2) 1Maximum load current (mA) 800 1000 5

Switching frequency 828866 KHz 1.1 MHz 0

4

1

N

l

N

1

M. Yang et al. / Microelectronics Journal 44 (2013) 128136 135Inductor/capacitor 4.7 mH/10 mF 4.7 mH/10 mFOutput ripple voltage (mV) NA o3Reference tracking speed (ms/V) 12.5 (up)

100 (down)

NA

Transient recovery time/transient

voltage variation

NA o20 ms/80 mV@ 500 mAload step

Start-up time NA 2 ms

Load regulation (%/A) NA 0.084. Conclusion

This paper describes a PWM/PSM dual mode converter for DVSapplication. The method of the loop without capacitor compensa-tion and high accuracy sensing circuit is proposed in the design.The DPSS method is also used to decrease the power. The test chiphas been fabricated using a standard 0.13 mm CMOS process andexperimental results are presented for theoretical analysis. Theexperimental results show that the converter has fast responseunder different conditions, including start-up, load transientresponse and tracking speed. Therefore it can well suit for on-chip converter implementation especially for mobile devices thatrequire fast start-up, fast load transient response, high trackingspeed and high conversion efciency.

21] [22] This work

.18 0.35 0.13

2.485.6 87.292.7 84.293.8

.8 3 2.73.6

0.92.1 0.71.5

00 450 400

.6571.2 MHz 1.7 MHz 1.5 MHz

.7 mH/10 mF 4.7 mH/9.1 mF 4.7 mH/10 mF5 o10 4A 17.8 (up)

12.5 (down)

31.25 (up)

21.75 (down)

o10 ms/44 mV@ 400 mAoad step

14.4 ms/52 mV@ 400 mAload step

o8 ms/8 mV@ 300 mAload step

A NA o45 ms.2 NA 2.2load range from 1 mA to 400 mA. The measured results are shownin Fig. 18. When the input voltage is 3.3 V and the output voltageis 1.5 V, the full load of the conversion efciency of the converteris above 84%. The peak efciency is over 93.8% at 240 mA.

Table 1 shows the performance comparison with previouslyreported works [3,4,21,22]. With all the advancements describedabove, the proposed design features higher conversion efciencyand fastest load transient response. On chips safe fast soft-start-up circuits and preferable reference tracking speed are alsoincluded. Besides, high accuracy sensing circuit design methodsare used to ensure stability over different load and voltage ranges.All these features are realized in a low size SMIC 0.13 mm CMOSprocess.

Acknowledgment

The authors would like to thank the National Natural ScienceFoundation of China (61274022 and 61201034) and the Programfor New Century Excellent Talents in University (NCET-10-0331).

References

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A monolithic peak current-mode buck converter with fast response for high speed DVS applicationIntroductionCircuit descriptionsOn chip fast soft-start-up circuitsError amplifier and PWM modulatorCurrent sensor

Experimental resultsConclusionAcknowledgmentReferences