› ~kumar › CISS Invited Talk.pdf · Title Goes Here LDPC Codes for Storage ChannelsTitle Goes...
Transcript of › ~kumar › CISS Invited Talk.pdf · Title Goes Here LDPC Codes for Storage ChannelsTitle Goes...
1Vijayakumar Bhagavatula
Vijayakumar BhagavatulaHongwei SongLingyan Sun
Toshihiro Horigome
Title Goes HereLDPC Codes for Storage Channels
2Vijayakumar Bhagavatula
Outline! Data storage channels! LDPC code attributes
! Structured
! Column weight
! Girth
! FPGA implementations! Summary
3Vijayakumar Bhagavatula
Digital Data Storage Channel
M edia
W riteHead
ReadHead
User Bits
User BitsW riteCurrent
W riteCurrent
Timing Recovery
EqualizationEqualization
EncodingEncoding
DetectionDetectionDecodingDecoding
Analog•Digital data represented by• magnetization changes (hard disk,
tape, MO)• pits and lands (CD/DVD)• phase change (DVR)
4Vijayakumar Bhagavatula
HDD Signal Processing Trends
PEAK DETECTM FM
(2,7)
(1,7)
PR4EPR4 NPM L with PARITY
d=0 ord=1
Density
Tim e
ANALOG DIGITAL
E PR4, GEnPR4n
TURBO /LDPC CO DES
d=0
Courtesy: H. Thapar
• Normalized densities > 3• Lower SNRs; 6 to 10 dB range?• Higher data rates; need faster detection
5Vijayakumar Bhagavatula
Optical Data Storage Evolution
System Capacity Laserwavelength
LensNA
CD 650 M B 780 nm 0.45
DVD 4.7 GB 650 nm 0.60
Blue Ray Disk 23-27 GB 405nm 0.85
• PRML being used• Moving from d=2 RLL codes to d=1• Jitter vs. tilt a more popular metric than BER• Longer codewords than in HDD (DVD block size 32 KB)• How do we combine RLL coding with iterative soft decoding?
6Vijayakumar Bhagavatula
Schematic of a Read/write PRML Channel
Tim ingRecovery
ViterbiDetector
RLLDecoder
RSDecoder
User Data Sector Data512 Bytes
RSEncoder
RLLEncoder
ParityEncoder
To read channel
LPF
FIR
ParityDecoder
User DataSector Data512 Bytes
To diskcontroller
Sym bol-ratesam pler
8Vijayakumar Bhagavatula
Partial Response Maximum Likelihood (PRML)
0 1 3 3 1 03PR3
0 1 2 1 02PR2
0 1 1 01PR1
Pulse ResponsenName
Pulse Response
Target Pulse Response
Example of PR2 Equalization
-3 -2 -1 0 1 2 3
0
1
2
Symbol Time
Amplitude
0
Channelpulse response
Equalizer
PR Target(1+D)n
ViterbiAlgorithm
ViterbiAlgorithm
Detected bitsChannelbits
9Vijayakumar Bhagavatula
Iterative Soft Decoding for PR Channels
! Using a partial response (PR) channel as an inner Code.
! Outer code can be either turbo code, convolutionalcode or LDPC code.
Extrinsic Information
ChannelDetector
ChannelDetector
Outer Decoder
Outer Decoder
OuterEncoder
OuterEncoder
Channelh(t)
Channelh(t)
User data
Noise
EqualizerEqualizer
PR ChannelD Dm n(1- ) (1+ )
10Vijayakumar Bhagavatula
PRML Vs. Serial Turbo
4 6 8 10 12 1410
-5
10-4
10-3
10-2
10-1
PRM L-1+D -no ~1 PRM L-1+D 2-no ~2Seri-1+D -no ~1 Seri-1+D 2-no ~2
SNR = 10 log10(Etarget/Noise_Level)
BER
11Vijayakumar Bhagavatula
LDPC Codes Vs. Turbo Codes
5 6 7 8 9 1010
-6
10-5
10-4
10-3
10-2
10-1
SNR
BER
Turbo-1+D -no ~1.0 Turbo-1+D -1+D ~1.0 Turbo-1+D 2-no ~2.0 Turbo-1+D 2-1+D 2 ~2.0LD PC -1+D ~1.0 LD PC -1+D 2 ~2.0
12Vijayakumar Bhagavatula
LDPC Code Issues
! Structured parity check matrix H to improve memory storage and access.
! Large girth LDPC codes to allow more iterations of optimal decoding.
! Small column weight LDPC codes to reduce computations.
! Can a single high-rate LDPC code provide 10-15 type BER?
! Are block error statistics of LDPC codes compatible with outer ECC?
13Vijayakumar Bhagavatula
Cycle, Girth and Code Length
Bit
Check
Graph with short cycles of length 4, 6
1 2 3 4 5 6 7 8 9
0 0 0 0 1 0 0
0 0 0 0 0 1 0
0 0 1 0 0 0 1
0 0 0 0 0 0 1
0 0 0 0 1 0 0
0 0 1 1 0 0 0 1 0
H
=
1 1
1 1
1 1
1 1
1 1
M N×
1 1( 1) ( 1) ... ( 1)( 1)p pN k k j k k j k− −≥ − − + + − − +12 2
[ ( 1) ( 1) ... ( 1) ]/p p
N k k j k j k j−≥ − − + + − +
LDPC codes with girth g=4p,
LDPC codes with girth g=4p+2,
Column weight j=2Row weight k=3
j
k
14Vijayakumar Bhagavatula
" Cyclic codes, shift register encoding
" Large minimum distance due to large column weight
# High decoding complexity due to large column weight
Finite Geometry LDPC Codes
! Example: cyclic LDPC code (N=4599, K=4227)
2 5 372( ) 1 ...g X X X X X= + + + + +3 4 4227( ) 1 ...h X X X X X= + + + + +
4599 1 ( ) ( )X g X h X+ =
Generalized Euclidean Geom etry LDPC codes
col. wt. N K dm in Rate Density GF3 63 37 9 0.587 0.1270 643 4599 4227 >9 0.92 0.0157 5124 255 175 17 0.686 0.0627 2565 1023 781 33 0.763 0.0313 10246 4095 3367 65 0.822 0.0156 4096
15Vijayakumar Bhagavatula
! Assume D1, D2 ,… , Dt are disjoint difference sets(v, j, t), we can construct 4-cycle-free DDS-LDPC code (N=vt, j, k=jt) with
! DDS-LDPC codes with column weight j≥ 3 have girth g=6.! DDS-LDPC codes have minimum distance
1 2 t=H [H H H ]!
min1 2j d j+ ≤ ≤
DDS-LDPC Codes
! Example: D={{0, 1, 4}, {0, 2, 7}} is a DDS with v=13
1 2
0 0 0 0 0 0 0 0 0 0
= =
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
H H H
0 1 4 0 2 7
16Vijayakumar Bhagavatula
2 3 1
2 4 6 2( 1)
1 2( 1) 3( 1) ( 1)( 1)
q
q
j j j j q
−
−
− − − − −
=
I I I I I
I σ σ σ σH I σ σ σ σ
I σ σ σ σ
!!!
" " " " ! "!
1
1
1
1q q×
=
σ#
Permutation Matrix (PM) LDPC Codes! PM -LDPC codes with column weight j≥ 3 have girth g=6.
! PM -LDPC codes have minimum distance
! Efficient encoding
min
minmin
min
min
6 3 6
12 4 10
20 5 16
32 6 ??
j d
j dd
j d
j d
= = = =≤ = = = =
17Vijayakumar Bhagavatula
3 3.5 4 4.5 5 5.5 610
-6
10-5
10-4
10-3
10-2
SNR (dB)
BER
PM LD PC , AW G NR andom , A W G NPM LD PC , EP R 4R andom , E PR 4
! Girth g=8 PM -LDPC code slightly outperforms random LDPC codes for both AW GN channels and EPR4 channels.
R=8/9
N=4509
j=3
BER Performance
18Vijayakumar Bhagavatula
LDPC vs. RS ECC
5 5.5 6 6.5 7 7.5 8 8.5 910
-10
10-8
10-6
10-4
10-2
100
SNR (dB)
Sector ER
Code rate=0.94
j=3 LDPC, 5/3 itj=3 LDPC, 1/50 itj=4 LDPC, 5/3 itj=4 LDPC, 1/50 it
RS code
EPR4, Rate=16/17
! LDPC codes outperform by 0.5+0.7=1.2dB at SER=1e-3, 0.7dB comes from global iteration
Does the gain hold at SER=1e-11 ?
20Vijayakumar Bhagavatula
ChannelDetector
ChannelDetector
LDPCDecoder
LDPCDecoder
LDPCencoder
LDPCencoder
Channelh(t)
Channelh(t)
Noise
EqualizerEqualizer
PR Channel
LDPCEncoder
LDPCEncoder
LDPCDecoder
LDPCDecoder
u u
4 5 6 7 8 910
-7
10-6
10-5
10-4
10-3
10-2
10-1
100
SNR (dB)
SER
j=2 + j=4 codeRS code
1.4 dB
EPR4
rate=0.827
N=5110
Concatenated LDPC Codes
Does the 1.4dB gain hold at SER=1e-11 ?
22Vijayakumar Bhagavatula
4 4.5 5 5.5 6 6.5 710
-6
10-5
10-4
10-3
10-2
10-1
SNR (dB)
BER
j=2j=3j=4j=6
! Largercolumn weight j$ worseBER performance at the cliff region
! Largercolumn weight j$ largerminimum distance, lowererror floor.
! Cycle code provide significant coding gains for PR2 channel.
j=3 j=4 j=6
j=2
EPR4 Channel
Column Weights Vs. BER Performance
5 5.5 6 6.5 7 7.510
-7
10-6
10-5
10-4
10-3
10-2
10-1
SNR (dB)BER
j=2, PR2j=3, PR2j=4, PR2
PR2 Channel
23Vijayakumar Bhagavatula
Block Error Statistics
! j=2 LDPC code exhibits block error statistics more compatible with an outer ECC such as RS code.
0 5 10 15 20 250
5000
10000
15000
SNR=5.5 BER=9.6e-005 Blocks=167072
0 2 4 6 8 10 12 14 160
5000
10000
15000
SNR=5.625 BER=6.1e-005 Blocks=228894
# of blocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 140
2000
4000
6000 SNR=5.75 BER=3.7e-005 Blocks=155269
# of errors
0 20 40 60 80 100 120 140 1600
50
100
SNR=5.375 BER=8.4e-5 Blocks=38599
0 50 100 1500
10
20
30
SNR=5.5 BER=7.6e-6 Blocks=19728
# of blocks
0 20 40 60 80 1000
10
20
30
SNR=5.625 BER=8.9e-7 Blocks=162492
# of errors
j=2 LDPC code j=3 LDPC code
32Vijayakumar Bhagavatula
LDPC Decoder Implementation
PlatformFPGA : ALTERA Stratix
PC interface : NI-DAQ (PC side)
Throughput : 200M bps for 8 iterations
33Vijayakumar Bhagavatula
Simulator Implementation
PC FPG A
RandomNum berG enerator
+LDPCEncoder
AW G NG enerator
LDPCDecoder
ErrorCounter
LLRConverter
Num bersof errors
SNRValue
# ofIterations
Num berof data
34Vijayakumar Bhagavatula
BER vs. SNR from FPGA Simulator
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
3 4 5 6 7 8 9
Signal to N oise Ratio [dB ]
Bit Error Rate
1st iter.
2nd iter.
3rd iter.
4th iter.
5th iter.
6th iter.
7th iter.
8th iter.
Rate 8/9, Colum n-weight 3, Structured, DDS LDPC Code
36Vijayakumar Bhagavatula
Soft Output Viterbi Algorithm (SOVA)
• VA modified to deliver not only the most likely path in the trellis, but the reliability information for each bit• Larger differences between surviving paths and competing paths imply larger confidences• Three SOVA structures examined: Classic, Two-step & Bidirectional
Relative time index l
path jδ
path
path
Time index i i<k i=k k<i<k+l k+l k+δ
l=0 l δ
(jl)
38Vijayakumar Bhagavatula
SOVA ImplementationPlatform: Xilinx Vertex II 2000
Throughput: 100M bps
PerformanceBidirectional SOVA +LDPC decoder Performance
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
5 5.5 6 6.5 7
Signal to Noise Ratio
Bit Error Rate
BI_SOVA_floating
BI_SOVA_fixed/Implementation
M AP_floating
39Vijayakumar Bhagavatula
SOVA and LDPC Decoder IntegrationChallenges:
Not enough memory resourceson Xilinx Vertex II 2000
Interfaceincompatibility
Different platform (SOVA in VHDL on Xilinx, LDPC decoder in Verilogon Altera)
SOVA: M odify the Interface
LDPC Decoder :
Cut half of the memory (sacrifice the speed)
Reduced the Logic
Changed the Interface for Real Time Processing
From Verilogto VHDL (whole environment)
From Alterato Xilinx (final platform)
42Vijayakumar Bhagavatula
Format of Hard Drive
Pream ble Synch M ark
User Data Postam ble
Data Sector
Pream blePream ble Synch M arkSynch M ark
User DataUser Data Postam ble
Data Sector
43Vijayakumar Bhagavatula
Loss of Lock
Loss of Lock
0 500 1000 1500 2000 2500 3000 3500 4000-3
-2
-1
0
1
Phase offset (T)
B it Index (T)0 500 1000 1500 2000 2500 3000 3500 4000
-3
-2
-1
0
1
Phase offset (T)
B it Index (T)0 500 1000 1500 2000 2500 3000 3500 4000
-3
-2
-1
0
1
Bit Index (T)
Phase offset (T)
0 500 1000 1500 2000 2500 3000 3500 4000-3
-2
-1
0
1
Bit Index (T)
Phase offset (T)
(Cycle Slip) (Hangup in Tracking)
Phase trajectory of the recovered clockPhase trajectory of the actual clockPhase trajectory of the actual clock shiftedup by one bit interval
Results using the simulator
44Vijayakumar Bhagavatula
10-6
10-5
10-4
10-3
10-3
10-2
10-1
100
Loss of Lock Rate
Throughput Loss
Throughput Loss versus Loss of Lock Rate
Throughtputlossis defined as the ratio of the time spent to re-read to the average time the system can read without need to re-read.
In order to re-read, the disk needs to undergo one revolution. Assuming 1000 sectors per revolution.
45Vijayakumar Bhagavatula
6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 1210
-5
10-4
10-3
10-2
10-1
SNR(dB)
Loss of Lock Rate
C onventional Hard Decision Directed TED Schem eSDD-TED DSK-STRHard Decision Directed DSK-STRSDD-TED DSK-STR Linear Phase Drift M odelSDD-TED Single Segm ented-Kalm an-Filter
Performance of DSK-STR
Loss of Lock Rate
46Vijayakumar Bhagavatula
Summary
LDPC codes of interest in data storage applicationsStructuredLow column weightLarge girthCompatibility with outer codes
FPGA hardware for simulating codes
But other problems (e.g., timing recovery) may prove to be bigger issues.