FOA-R--99-01085-409--SEMarch 1999

ISSN 1104-9154

Technical Report

Division of Systems and Underwater Technology

SE-172 90 STOCKHOLM

A GPSBased Time Synchroniser

Gunnar SundinÅke Arvidsson

Jörgen PihlHåkan Lans

1

FOA-R--99-01085-409--SEMarch 1999

ISSN 1104-9154

A GPSBased Time Synchroniser

Gunnar SundinÅke Arvidsson

Jörgen PihlHåkan Lans

DEFENCE RESEARCH ESTABLISHMENTDivision of Systems and Underwater TechnologySE-172 90 STOCKHOLMSweden

2

Date of issueMarch 1999

Document title

A GPS Based Time Synchroniser

Issuing organization

Defence Research EstablishmentDivision of Systems and UnderwaterTechnologySE-172 90 STOCKHOLMSweden

Distributor (if not issuing organization)

Author(s)

Gunnar SundinÅke ArvidssonJörgen PihlHåkan Lans

Initiator of sponsoring organization

Project managerJörgen Pihl

Scientifically and technically responsibleGunnar Sundin

Abstract

Pages 24 p. Price Acc. to pricelist

Document ref. No., ISRNFOA-R--99-01085-409--SE

Project No.E6031

Project name (abbrev. if necessary)Surveillance sonars

ISBNISSN 1104-9154

Further bibliografic information Language English

Key words

The report describes a GPS synchronised clock. Its intended use is to synchronise transmitter and receiverin a bistatic sonar system. It uses the one-second-pulse form a GPS receiver to synchronise the clock toUTC time and at the same time to steer the built in oscillator to exactly 5 MHz. After the synchronisationthe clock is estimated to keep its time to within a few milliseconds for a period of two months. Thus theclock can be used even if the GPS signal is not available for a long time as in a submarine. When the GPSsignal is available, the accuracy of the clock is expected to be better than 100 ns. With a built in directdigital synthesis chip the clock can also deliver a sinusoidal signal which can be modulated in amplitude,frequency or phase.

Synchronised clock, GPS, Bistatic Sonar, Multistatic Sonar, Direct Digital Synthesis

3

Dokumentets titel i översättning

Dokumentets utgivare

Försvarets forskningsanstaltAvdelningen för Styrning, simulering ochundervattensteknik172 90 STOCKHOLM

Distributör (om annan än ovan)

Upphovsman(män)

Gunnar SundinÅke ArvidssonJörgen PihlHåkan Lans

En GPS-synkroniserad klocka

Uppdragsgivare

ProjektansvarigJörgen Pihl

FackansvarigGunnar Sundin

Sammanfattning

Omfång 24 s Pris Enl prislista

Dokumentbeteckning, ISRNFOA-R--99-01085-409--SE

Dokumentets datumMars 1999

UppdragsnummerE6031

Projektnamn (ev förkortat)Spaningssonarer

ISBNISSN 1104-9154

Övriga bibliografiska uppgifter Språk Engelska

Nyckelord

Rapporten beskriver en GPS-synkroniserad klocka. Den är avsedd att synkronisera sändare och mottagare iett bistatiskt sonarsystem. Den använder ensekundpulserna från en GPS-mottagare för att synkronsera klockantill UTC-tid och styr på samma gång den inbyggda oscillatorn till exakt 5 MHz. Efter synkroniseringen för-väntas klockan hålla tiden inom ett par millisekunder under en tid av två månader. Klockan kan alltså ävenanvändas då GPS-signalen inte är tillgänglig under lång tid som i en ubåt. När GPS-signalen är tillgänglig ärklockans förväntade noggrannhet bättre än 100 ns. Med ett inbyggt DDS-chip (direct digital synthesis) kanklockan även lämna en sinussignal som kan moduleras i amplitud, frekvens och fas.

Synkroniserad klocka, GPS, Bistatisk sonar, Multistatisk sonar, Direct Digital Synthesis

4

Contents

1. Introduction 51.1 The Multistatic Sonar 51.2 Requirements 6

2. Design and Operational Principle 62.1 Basic ideas behand the GPS synchronisation unit 62.2 PCB 62.3 Main components 72.4 Software 8

3. First test results 8

4. Conclusion 10

5. References 10

Appendix A: Electrical circuit design A-1

Appendix B: Quick Logic Circuit diagrams B-1

Appendix C: Description of I/O ports C-1

5

1. Introduction

1.1 The Multistatic Sonar

Figure 1. Examples of Multistatic Sonar in active surveillance. One transmitter is fixed at the bottom, and the otheronboard the surface ship. Receivers are positioned at the surface (sonobouys) and onboard the own submarine. Thepositions of the receivers are unknown to the target submarine.

Modern submarines and surface ships are becomingmore and more quiet. As a result, the detection distancesfor passive sonar are getting shorter. A possible wayaround this problem is to use active sonar, which mightgive you the detection distances you need. However,using active sonar might be undesirable for a submarine,which wants to operate silently and covertly. By puttingthe transmitter on a co-operating platform and the re-ceiver on the submarine, it can still be silent but gainfrom the longer detection distances obtainable by theactive sonar. Such a sonar is called a Multistatic Sonar(Figure 1).

Multistatic sonar has been tested by several nations(1). At FOA we are just now setting up a test system toinvestigate the performance of multistatic sonar in theBaltic. Figure 2 shows a schematic picture of an expe-rimental setup. In this example the transmitter, the tar-get and the receiver are at the corners of a triangle (Tr-T-R). To know the position of the target the receiverhas to know the length of the triangle side C and thedirection to the target. This can be computed if thedistances A and (B+C) are known. Then the target must

lie on an ellipse, and if the direction to the target isknown its position can be uniquely determined. Thus ifthe position of the sender and the time of the transmis-sion is known the position of the target can bedetermined.

By using several transmitters, and/or severalreceivers, we obtain a pattern of overlapping ellipses.In such cases the target position can be determined evenif the direction is not known.

Figure 2. Principle of Multistatic Sonar

T

Tr RA

BC

6

Counter

D/A-converter

5 MHzoscillator

Freq.multiplierx 10

µ-processor

GPSreceiver

50 MHz

1 secpulse

controlvoltage

1.2 Requirements

In multistatic sonar the receiver must know the timewhen the transmitter emits a pulse. A radio link or adirect cable connection usually achieves this timesynchronisation. However, if the receiver is on asubmarine or another submerged platform, we can notestablish a communication link. One way in such a caseto obtain time synchronisation is to have very accurateclocks at the transmitter and receiver. These clocks needto be accurate enough so that negligable errors areintroduced in the signal processing. In principle, theaccuracy in timing should be better than the accuracyin positioning and target localisation. The latter dependson the emitted pulse type and length, the processingmode, and the selected range of search. The bestobtainable range estimates of a surveillance sonar areof the order of one meter, corresponding to a fewmilliseconds accuracy in time. The goal of our designis to achieve an accuracy of one millisecond over a pe-riod of two months, which corresponds to an estimatedmaximum time for a submarine operation.

2. Design and operationalprinciples

2.1 Basic ideas behind the GPSsynchronisation unit

The main components of the time synchronisation unitare a very stable oscillator, a GPS receiver, amicroprocessor and a logic unit built into a FPGAcircuit.

Figure 3 shows the basic structure of thesynchronisation control loop. The frequency of the os-cillator can be varied by changing the voltage appliedto one of its connections, but only within a small rangearound 5 MHz. With the frequency multiplier, theaccuracy of the control loop is increased tenfold.

A period counter counts the periods of the 50 MHzsignal from the frequency multiplier for an integernumber of seconds. The microprocessor compares theoutput from the counter with the corresponding valuefrom a true 50 MHz oscillator. If a difference isobserved, it sends a command to the D/A converter tochange the frequency of the oscillator to make it closerto 5 MHz.

The logic unit of the counter is contained in a Quick-Logic FPGA chip. The normal procedure to start thesynchronisation process is to use one second as theinitial measurement time, giving a coarse adjustmentof the oscillator frequency. The next step is to increasethe measurement time and make finer adjustments untilthe stability limit of the oscillator is reached.

The stability of the oscillator within one day(5x10-10 ), corresponds to 1 period of 50 MHz in 40seconds.

The main purpose of the clock is to make it possibleto have synchronised time at separate measurementsites with high accuracy. However, the design of theunit is so versatile that it can be used for various otherapplications. A possible use is for frequencymeasurements or measurements of time delays.

The unit is also equipped with a digital direct syn-thesis chip (DDS). This chip can produce a sinusoidalsignal with precisely controlled frequency, phase andamplitude. The output frequency can be set to anyfrequency from DC to 50 MHz with a resolution ofabout 1/100 Hz . The unit also has a microphone in-put. With this, the DDS signal can be modulated infrequency, phase or amplitude in real time.

Figur3 Basic structure of the GPS synchronisation unit

7

Figure 4 The PCB.

2.3 Main components

2.3.1 Oscillator

The oscillator, a PMTP 5.1E, with a frequency of 5MHz is manufactured by CEPE (Compagnied´électronique et de piézo-électricité). It is a crystaloscillator operated in a capsule with regulated tempera-ture, enclosed in a small sealed metal package. It has ashort term stability (up to 10 seconds) of 10-12. The oneday stability is 5x10-10 and the one month stability is10-8(reference 3).

2.3.2 GPS receiver

The GPS receiver is of the type Rockwell TU30-D140�Jupiter�. It is a 12 parallel-channel receiver. It canaccept Differential GPS (DGPS) corrections in theRTCM SC-104 format. Its size is 71 x 41 x 11 mm(reference 2).

5 MHzoscillator

GPSreceiver

EpromFlashprom Ram

Micro-processor

Programmablelogic

DDSmodulator

2.2 PCB

The PCB is a two layer board, 260x200 mm large, asshown in figure 4.

Figure 5 The GPS receiver

EPROMFlash

PROM RAM

8

FUNCTIONAL BLOCK DIAGRAM

32

32

12

10

10

10

10

10SIN

COS

12

10-BIT DAC

PHASEACCUMULATOR

SIN/COSROM

IQMOD [9:0]

IOUT

COMP

FS ADJUST

SDATA

SCLK

GND

RESETTEST

CLOCK

VAA

WR CS

IOUT

AD7008

32-BIT SERIAL REGISTER

32-BIT PARALLEL REGISTER COMMAND REG

MPU INTERFACE TRANSFER LOGIC

FULLSCALEADJUST

10

IQMOD [19:10]

12

PHASE REG

D0 D15

32

32

FSELECT

MUX

FREQ1 REG

TC0 TC3 LOAD

Σ10

Σ

FREQ0REG

Σ

SLEEP

VREF

Figure 6. The DDS Functional Block Diagram

2.3.5 Quick-Logic programmable logicMost of the logic for counters and time-keeping isprogrammed in a Quick-Logic programmable chip,QL2007 (5). This means that it is easy to change thebehaviour of the clock and to add new functions withouthaving to change the main PC-board.

2.3.3 MicroprocessorThe microprocessor is a Hitachi HD64180 eight-bit pro-cessor. It is connected to three different memory chips– a 16 kB EPROM, a 16 kB Flashprom and a 32 kBRAM chip.

2.4 SoftwareThe EPROM contains a monitor program with debug-ging tools, flash memory programming routines, aroutine for loading program from a host, and a realtime kernel. The kernel handles the time scheduling ofseveral concurrently running tasks. The executable codeof the tasks is stored in the flash PROM or RAM.

The real-time tasks interprete the GPS receivermessages and the host commands, and handle the GPSsynchronisation.

In the normal use of the clock a simple commandlanguage is used. It includes commands to control thetiming of the output pulses, the pulse lengths and thesignal waveforms.

With the aid of a Windows based Fortran programthe user can set parameters to control the pulse shapesand timing, as well as display the GPS position, andperform frequency and time measurements.

2.3.4 Direct Digital Synthesis chipThis is a AD7008 CMOS DDS Modulator manu-factured by Analog Devices. This chip can generatesinusoidal signals with frequencies from DC up to 50MHz in steps of about 1/100 Hz (50000000 / 232) andwith the same stability as the 5 MHz oscillator. Thesignal can be modulated in amplitude, frequency andphase. The speed of the modulation is only limited bythe microprocessor (figure 6 and reference 4).

9

Figure 7. Power on behaviour of GPS synchronised clock. The green curve is the D/A control signal and the blue curvethe deviation from 50 MHz. The vertical scale for the difference signal is in Hz. The D/A control signal has an allowed

interval of ±32767.

Figure 8. Close up of the beginning of phase three in the control loop.

3. First test results

Figures 7 - 9 show the behaviour of the clock duringthe first minutes after power on. The blue curve showsthe difference between the output frequency of the clockmeasured between two consecutive GPS one-second-pulses and 50 MHz. The negative spikes in the curveare due to a counter being reset at regular intervals.You should only look at the positive envelope of the

curve. The green curve is the control signal to the D/A-converter that steers the oscillator frequency. We canse three distinct phases of the control loop. During thefirst few seconds the D/A output is steered in very coarsesteps to find a value where the frequency drift of theoscillator is towards 50 MHz. Then, in the second phase,the D/A converter is left in that state and the difference

0 100 200 300 400 500 600 700-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5x 10

4

seconds after power on

D/A control signal

Difference signal

200 210 220 230 240 250 260 270 280-300

-200

-100

0

100

200

seconds after power on

10

5. References

1. L. Mozzone: �Deployable multistatic active sonar:the cycle of system design, tests and data analy-sis�, Oceans� 98 conference, Nice, France Sep-tember 1998.

2. Rockwell Semiconductor Systems, �Jupiter�Global Positioning System (GPS) Receiver (PartNo. TU30-D140-221/231). Data sheet January 19,1997.

3. CEPE Thomson-CSF, PMTP 5.1E, OvenControlled Crystal Oscillators. Data Sheet.

4. Analog Devices, CMOS DDS ModulatorAD7008 Rev B. C1791a-10-2/95. Data sheet1995.

5. Quick Works Users Guide ver. 7.0, 1991-1998.4. Conclusion

Preliminary tests of the systems indicate that theaccuracy of the synchronised clock far exceeds ourrequirements. Further work is needed to verify the long-term stability. We also need to build a second clockunit to make a complete system for multistatic sonar.

300 350 400 450 500 550 600 650

-6

-4

-2

0

2

4

6

seconds after power on

Figure 9. Close up of the second half of the power up sequence.

(blue curve) is monitored. After 241 seconds when thefrequency just reaches 50 MHz the third phase of thecontrol loop begins. The stability of the oscillator isnow so good so that it is worth controlling it with theD/A-converter. As can be seen from the blue curve,the behaviour of the control loop is excellent. The meanabsolute difference is only 0.65 periods correspondingto 13 nanoseconds from 250 seconds after power on tothe end of the curve. After about 600 seconds the D/Aoutput has stabilised indicating that the oscillator ovenhas reached its final temperature. At this point the nextphase in the control loop should start with differencemeasurements over successively longer periods andmore fine-tuning of the oscillator. That part of the pro-gram however is not yet written.

A-1

Appendix A

Design of the electrical circuit

Contents A-1

Overview diagram of the unit A-2

Crystal oscillator and PLL frequency multiplier A-3

Analogue inputs A-4

Analogue outputs A-5

Microphone amplifier with low pass filters and A/D-converter A-6

Serial communication A-7

A-2

A-3

A-4

A-5

A-6

A-7

B-1

Appendix B

Quick logic circuit diagrams

Contents B-1

Counters and counter registers B-2

Data out address logic B-3

Address decoder B-4

D/A and A/D converter interface B-5

B-2

12

34

56

78

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56

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66

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MP

S[0:7]

SI3[0:7]

CO

MP

S[6]

CN

T[14]

CN

TB

[14]C

OM

PS

[5]ID

[0:7]ID

[0:7]IO

RC

NT

[15]C

NT

B[15]

OD

[3]IO

D[3]

CO

MP

S[1]

CO

MP

1ID

[3]S

A1

SA

0IO

WIO

WC

OM

PS

[6]IO

RA

D[7]

A[7]

A[12:18]

CO

MP

S[5]

OD

[4]IO

D[4]

ID[4]

CO

MP

S[0]

CO

MP

S[2]

CO

MP

2C

OM

PB

2[0:7]C

OM

PB

1[0:7]A

D[12]

A[12]

IOR

CN

T[8:15]

CN

T[0:7]

OD

[5]IO

D[5]

CO

MP

S[6]

A[2]

ID[5]

CO

MP

S[5]

A[1]

AD

[13]A

[13]C

50MO

D1[0:7]

AD

[16]A

[16]C

OM

PO

UT

TB

U1[0:7]

IOR

CO

MP

S[3]

CO

MP

3T

BU

2[0:7]O

D[6]

IOD

[6]T

BU

3[0:7]ID

[6]C

OM

P0

AD

[14]A

[14]S

O1[0:7]

AD

[17]A

[17]S

I3[4]C

OM

PS

[6]S

O1[4]

CO

MP

S[5]

IOR

OD

[7]IO

D[7]

AD

[15]A

[15]A

D[18]

A[18]

ID[7]

CO

MP

S[4]

CO

MP

4

1, 5, 10, 50 MC

Cnt. seq:

00000001 = 0000001

00000000 = 0000000

49999999 = 2F

AF

07F49999998 =

2FA

F07E

F7FAF2

B-3

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

A

B

C

D

A

B

C

D

HDPAD

I_567

23

GPSC32

CLREN

Q[0:31]

GPSC32

CLREN

Q[0:31]

DFFP

I_341

D

PRE

QDFFP

I_343

D

PRE

Q

DFFP

I_342

D

PRE

QDFFP

I_344

D

PRE

Q

CKPAD

I_571

24

MUX4x0

S0S1

GPSM2x 8MUX0[0:7]

MUX1[0:7]

SEL

MUXO[0:7]

XOR2i0

GPSMU4X8

INBU1[0:7]INBU2[0:7]INBU3[0:7]INBU4[0:7]

S0S1

OUTB[0:7]

GPSMU4X8

INBU1[0:7]INBU2[0:7]INBU3[0:7]INBU4[0:7]

S0S1

OUTB[0:7]

GPSMU4X8

INBU1[0:7]INBU2[0:7]INBU3[0:7]INBU4[0:7]

S0S1

OUTB[0:7]

GPSMU4X8

INBU1[0:7]INBU2[0:7]INBU3[0:7]INBU4[0:7]

S0S1

OUTB[0:7]

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

OUTPAD

I_355

39

INPAD

I_572

28

REGE8D[0:7]

EN

Q[0:7]

REGE8D[0:7]

EN

Q[0:7]

REGE8D[0:7]

EN

Q[0:7]

Sunnyvale, CA 940891277 Orleans Drive

CorporationQuickLogic

TIME1

1999-03-17 09:51:58

TIME1

.

FREIN1 SI5[7]SI5[6]

TIMEAI1TIMEBI1

FREOUT

FREIN2

A[2]FREIN

FRECK

A[1]SI5[0] SI5[1] OD2[0:7]

FCNT[0:7]FCNT[8:15]

LOAD2 FCNT[16:23]SI5[2] FCNTEN1 FCNTEN2 FCNT[0:31] FCNT[24:31]

A[2]

A[1]SI5[1] OD3[0:7]

DCNT[0:7]C50M DCNT[8:15]

C50M DCNT[16:23]DCNT[0:31]

SI5[3]DCNTEN1 DCNTEN2 DCNTEN3

DCNT[24:27],FCNTEN1,FCNTEN2,DCNTEN1,DCNTEN3

A[4]

SA5IOW A[3]

SI5[0:7] OD[0:7]OD1[0:7]OD2[0:7]ID[0:7]OD3[0:7]OD4[0:7]

A[2]

SO1[1]A[0]

A[1]OD4[0:7]

C50M TBU1[0:7]CNT[16:23] BU23[0:7]

TBU20[0:7]

BU23[0:7]SO1[1]

TBU20[0:7]BU24[0:7]

C50MCNT[24:27],CNTB[12:15] BU24[0:7]

FLASHR,WDIR,WDIE,BUSY,GND,GND,GND,GND

GND[0:7]

e x t. wi re

B-4

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

A

B

C

D

A

B

C

D

AND3i2

I_620

ADSAGPS1

A[0:4]

ES[0:23]

AND4i3

AND4i3

AND4i2

AND4i2

DFFC

I_493CLR

D Q

TRIPAD

I_494

13

AND3i1

AND3i1

AND3i1

DLAEC

CLRD

ENG

Q

DLAC

CLRD

G

Q

DLAC

CLRD

G

Q

DLAC

CLRD

G

Q

OR2i0

OR2i0

OUTiPAD

I_367

1

OUTiPAD

I_366

77

OUTiPAD

I_365

68

OUTiPAD

I_419

62

OUTiPAD

I_396

50

INV

INV

INV

INV

INV

AND5i0

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

AND2i1

AND2i1

DFF

I_520

D Q

AND2i0

AND2i0

AND2i0

OUTPAD

I_399

45

OUTPAD

I_401

48

OUTPAD

I_376

74

OUTPAD

I_550

26

OUTPAD

I_397

49

OUTPAD

I_398

47

INPAD

I_392

18

INPAD

I_496

20

INPAD

I_420

12

INPAD

I_377

17

INPAD

I_378

16

Sunnyvale, CA 940891277 Orleans Drive

CorporationQuickLogic

TIME1

1999-03-17 09:51:58

TIME1

.

A[14] CS1A[15]

A[14] CS2A[15]

A[15] CS3A[12]

IOWW WRCOMSA[6]

MEIA[12]A[13]A[14]A[15]

IOWWIOE41

ID[3]FLASHR

FLASH

RESETCLR1

SA[16]

S[0:5],SA[6:23]

ID[0] FSELDSA[0:4] S[0] SA0

RD S[1] SA1 SLEEPDS

ID[1]

TIM

E S[2]SA2

CSDSIORIORD S[3]

SA3 A1[2]A[4]A[3]S[4]

SA4 ID[2] LOADDSIOW A[5]

IOWRS[5]

SA5

WR RESETDSSA[17]

IOWW

A[0] A1[0]IOWW WRDS

IOE41A1[0]A1[1] IOWW

A[1] A1[1] A1[2] ID[0]WDIE

A[3]IOE

A[6]WDI

A[4] ID[1] WDIRA[5]

A[2] A1[2]A[7]

IOE1

ADENA[3]

ADDRESS DECODER

ARV

EPROM

FEPROM

RAM

48-4F

SA20-SA27

WATCHDOG

DIR

EC

T D

IGIT

AL

SY

NTH

ES

IS

B-5

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

A

B

C

D

A

B

C

D

AND5i2

AND4i3

AND4i2

DFFEPC

I_526

CLR

D

EN

PRE

Q

AND3i1

AND4i1

OUTiPAD

I_471

70

OUTiPAD

I_528

44

OUTiPAD

I_470

69

OUTiPAD

I_473

71

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

BUFF

AND2i0

AND2i0

OUTPAD

I_530

43

OUTPAD

I_467

73

OUTPAD

I_468

72

INPAD

I_531

42

Sunnyvale, CA 940891277 Orleans Dr ive

CorporationQuickLogic

TIME1

1999-03-17 09:51:58

TIME1

.

CLR1 CLRDAC

A[3]IOWW

A1[2] DACA[4] LBDAC

A1[0]A[5]

A1[1]

HBDAC

A0D AC

WRDAC

D[0:7]

A1[1] GNDID[0]

D[0]A1[2] CLR1

A[3]ADC

ID[1]D[1]

A[4] IOWWA[5] ID[0] HBENADC

ID[2] D[2]

ID[3] D[3]

RDADCID[4]

D[4]RD

ID[5]D[5]

ID[6]D[6]

BUSYADC BUSY

MIN 80ns

SA12-SA13

SA8-SA11

INERFACE D/A AND A/D CONVERTER

ARV

C-1

Appendix C

Description of I/O ports

Contents C-1

Analogue inputs C-2

Analogue outputs C-2

Serial I/O C-2

Power input C-2

LED C-2

C-2

The connections between PC, sonar and themicroprocessor are controlled by the microprocessor.There is no direct path to the GPS receiver, which isaccessed via the microprocessor.

Figure 2.4 The RS232 connections

Analogue inputs

Time A Used for start signal in Time A �Time B measurement

Time B Used for stop signal in Time A �Time B measurement

Frequency in 1 Input for frequency measurements

Frequency in 2 Input for frequency measurements

Frequency in Input for frequency measurements

GPS antenna Input from the active GPS antenna

Microphone input Input for condenser microphone.Low pass filtered at 3.3 kHz.Maximum sampling frequency 70kHz.

All inputs have BNC-connectors, except the GPSantenna which has a TNC-connector and themicrophone input which has an 3.5 mm earphoneconnector

Analogue outputs

50 MHz 50 MHz square wave

1 second pulse Short pulse

1 second pulse Long pulse

Com1 � Com4 These are four outputs on whichcan be generated pulses at arbitrarypredefined time points.

Com0 On this output is generated a pulseat the same time as the pulse at oneof the outputs Com1 � Com4.

Freout To this output is multiplexed oneof the inputs Frequency1,Frequency2, TimeA or TimeB.

Fout This output can be programmed togive 1, 5 , 10 or 50 MHz squarewave.

DDS out 1 Linear (sine wave) output fromDDS chip.

DDS out 2 Square wave output from DDSchip.

All these outputs have BNC-connectors. The level ofthe outputs can be chosen within 3 - 12 V.

Serial I/O

There are three 9-pin Dsub connectors.

DGPS Input for differential GPSmessage. Unidirectional.

PC For communication with PC host.

Sonar This connector is for communica-tion with the sonar transmitter thatwe are going to use in the bistaticexperiments.

Power input

220 V AC

12 V DC

LED

The front panel of the clock has three LEDs that canbe programmed to show status.

micro-processor GPS receiver

PC

Sonar

DGPS

1 secsync