A Fully Integrated Shock Wave Transmitter with an …A Fully Integrated Shock Wave Transmitter with...

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1 A Fully Integrated Shock Wave Transmitter with an On-Chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS Mai KHANH N. N. (1) , Masahiro SASAKI (2) , and Kunihiro ASADA (1,2) ( 1) The University of Tokyo ( 2) VLSI Design & Eduction Center (VDEC), Japan Email: [email protected]

Transcript of A Fully Integrated Shock Wave Transmitter with an …A Fully Integrated Shock Wave Transmitter with...

Page 1: A Fully Integrated Shock Wave Transmitter with an …A Fully Integrated Shock Wave Transmitter with an On-Chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS Mai KHANH

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A Fully Integrated Shock Wave Transmitter with an On-Chip Dipole Antenna for Pulse

Beam-Formability in 0.18-μm CMOS

Mai KHANH N. N. (1), Masahiro SASAKI(2), and Kunihiro ASADA (1,2)

(1)The University of Tokyo(2)VLSI Design & Eduction Center (VDEC), Japan

Email: [email protected]

Page 2: A Fully Integrated Shock Wave Transmitter with an …A Fully Integrated Shock Wave Transmitter with an On-Chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS Mai KHANH

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Object to be imaged

ττ

ττ

Wide-Band Antenna Array

MOTIVATION

θ

Page 3: A Fully Integrated Shock Wave Transmitter with an …A Fully Integrated Shock Wave Transmitter with an On-Chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS Mai KHANH

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IMPLEMENTATION

•Target freq. 10 – 12 GHz• Suitable to achieve θmin=14.4o for the array antenna.

Monte Carlo : Vthreshold (3σ;5%), 5000 points Temperature: -40oC to 80oC

R1K

W/L =4u/0.6u

M0x1

I0

b0 b1 b2 b3 b4

Binary weighted

x8 x1

I 2I 3I 4I 5II

Vss

VDD

Vss

= 1.8 V

Input CLK

Vss

VA = 1.8 V

VinQ0Idelay

Current Steering DAC

L

C

VA = 1.8 V

Ra

Q0200p

Vss

Shock Wave Gen.

Buffer

Small PMOS, operating as

resistor

Vpulse

Digital part

Analog partRadiation part

VpulseVpulse

SHOCk WAVE OUTPUT (sim.)

PULSE DELAY SIM.

Analog part

(0.18μm CMOS)

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Measurement for an on-chip Antenna

100μm pitch GSGSG probe

HP 8510 Network Analyzer

On-chip AUT

cable“open”

“through”

“short”

Return loss, S11

BW =4.5 GHz

Layer cross-section view

1840 μm

290μm

Top Metal

4 intermediate metal layers

Substrate

Meandering dipole

Top Metal

1840 μm

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Meas. of the Fully Integrated Transmitter

received signal from horn antenna: Vo(p-p)=1.1mV

FFT of Vo(t)Center frequency :

10GHz

CLKin

Received pulse from the horn antenna

D[4:0]=24

D[4:0]=31

1mV/div100ps/div

D[4:0]=8D[4:0]=4

D[4:0]=0

Pulse delays vs. input code D[4:0]

Received pulses from the horn antenna, minimum resolution of 3 ps

a standard 20dB horn antenna

d = 38 mm

PC’s based pattern

generator

opened lid package

Suitable for pulse beam-forming

1840μm

794μm

DPDC Buffer Shock Wave Gen.

to Digitizing Osc. HP 54750A

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Pulse generator with an integrated antenna for

beam-formability purposeYESdre = 3

drag = 34YES32.4100.4 (sim.)

0.0011 (received)

21.8-V

0.18-μm CMOS

This work

not integrating pulse transmitter, beam-steering

subsystem onlyNO

dre = 100drag =

100 – 500 YES100---

2.5-V 0.25-μm

CMOS

[5]-2006

UWB 3.1 – 10.6-GHz triangle pulse generator

pulse width = 250 psNO

drag = 1000 –3000

YES22N/A1(sim.)N/A

1.2-V 90-nm

CMOS

[4]-2007

Turnable sub-GHz UWB generatorNO-NO1.30.48

50.289 –0.3370.5

3-V 0.5-μm

CMOS

[3]-2009

UWB pulser co-designed with wire-bond transition with pulse width = 0.6 ns

NO-NO2.7N/A14.3 1.2-V

0.13-μm CMOS

[2]-2009

UWB timed-array receiverwith 188 on-chip inductorsNO

dre = 15drag =

225YES555--1 – 15

1.5-V 0.13-μm

CMOS

[1]-

2007

Circuit description

On-chip ant.

dre &

drag (*) (ps)

Beam-forma-bility

P (mW)

Freq(GHz)

Vout(V)

BW(GHz)ProcessRef.

[1] T. S. Chu, 2007 [3] Y. Joo, 2009

[2] S. Bourdel, 2009 [4] F. Zito, 2006 [5] M. Yan-Wah Chia

(*) dre is delay resolution; and drag is delay range