A E Lab manual

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING______________________________________________________________________________

Sri Bhagawan Mahaveer Jain College of EngineeringJakkasandra P.O, Kanakapura (T), Bangalore R Dist.-562112

III SEMESTER ELECTRONICS & COMMUNICATION ENGINEERING

ANALOG ELECTRONICS AND

DIGITAL ELECTRONICS

LAB MANUAL

NAME : _________________________________________________________________

USN : _________________________________________________________________

YEAR : _________________________________________________________________

INSTRUCTIONS

___________________________________________________________________________

Sri Bhagawan Mahaveer Jain College of Engineering, Bangalore-562112.

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1. Come well prepared for conducting the Lab. experiment.

2. Maintain the silence in the Lab.

3. Keep the Lab. Clean.

4. Keep your belongings in appropriate place provided to you.

5. Do not come late to the Lab.

6. Work only on table allotted for you.

7. In the first half an hour of your Lab. session start, take required Components, Instruments from the counter by submitting the Components Issue Slip (according to experiment) .

8. Check all the Components before rig up the circuit.

9. After completing the circuit connection, consult with the staff member before switching it ‘ON’.

10. The CRO once switched ‘ON’ need not switched ‘OFF’ till the completion of the experiment.

11. Before switching ‘ON’ Power Supply and Function Generator , make sure that the Voltage/Amplitude control knob of these Instruments are at their minimum position and

while switching ‘OFF’ the circuit, first switch ‘OFF’ the Function Generator and then the Power Supply.

12. Be sure about the result expected and set the instruments in the expected range.

13. After the completion of the experiment arrange all patch cords, CRO Probes and Instruments properly on the table and ensure that all AC Power Supply switches of the working table are switched ‘OFF’.

14. Return the Components taken from counter.

CONTENTS

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EXPERIMENTNUMBER

TOPIC PAGE NUMBER

1. R C-Coupled Amplifier 05

2. Darlington Emitter Follower 11

3. Voltage Series Feedback Amplifier using BJT 17

4. R C – Phase Shift Oscillator using BJT 23

5. Hartley oscillator using FET 27

6. Colpitt’s Oscillator using FET 29

7. Diode Clipping Circuits 33

8. Diode Clamping Circuits 41

9. OP-Amp Applications i) Inverting Amp. ii) Non-Inverting Amp. iii) Voltage Follower

45

10. Voltage Summer using Op-Amp. 51

11. Op-Amp. as an Integrator and Differentiator 55

12. Zero Crossing Detector(ZCD) and Schmitt Triggerusing Op-Amp.

59

13. Full Wave Precision Rectifier using Op-Amp. 63

14. Voltage Regulator using IC 723 67

15. R – 2R Ladder Network using Op-Amp. 73

16. Study of Flash ADC 77

R C COUPLED AMPLIFIER

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Fig. No (1) Circuit Diagram of single stage R C-Coupled Amplifier.

Fig. No (2).Biasing Circuit

TABULAR COLUMN:

Vin = 50 mVp-p

SL NO

FREQUENCYin Hz

Vo(p-p)

in VoltsAv=Vo/Vi GAIN in dB = 20 log10 (Vo/Vi )

EXPERIMENT NO: 01

RC – COUPLED AMPLIFIER

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AIM: To determine experimentally and a) To plot the frequency response of a single stage R C- Coupled Amplifier, b) To determine Gain bandwidth Product [GBW = Amid x BW] and

c) To measure input impedance (Zi) and output impedance (Zo)

EQUIPMENTS AND COMPONENTS REQUIRED:

SLNO

NAME OF EQUIPMENTS/ COMPONENTS SPECIFICATIONS QTY

1. Power Supply 0 – 30 V / 2 Amp D.C. 012. A.C.Milli Voltmeter(or Digital Multimeter) 013. Function Generator 0 – 3 MHz, 0 – 20 V(p-p) 014. CRO Analog, 30MHz, Dual

Channel01

5. Terminal Board -- 016. Capacitors 0.47 µF (Ceramic)

47 µF (Electrolytic)0201

7. DRB -- 018. Resistors 270 Ω

1 KΩ4.7 KΩ 27 KΩ *(all ½ Watt)

01020101

9. Transistor SL 100 0110. Patch cords, Connecting Wires,etc.

PROCEDURE:

A] To find Q point:

1) Connect the circuit as shown in the Fig. No. (2)

2) Switch on the power supply and set +12 V D.C. as VCC.

3) Measure the DC Voltage using CRO or DC Voltmeter at the Base VB , Collector Vc and Emitter VE with respect to ground. Then determine VCE = VCC – Vc - VE = _________Volts

IC = (VCC – VC) / RC = __________mA

Q point = (VCE, IC) ______, _______

DESIGN: Let VCC = 12 Vdc IC = 4.5 mA, β = 100(for SL 100) Choose VE = VCC / 10 = 12/10 = 1.2 V VE = IERE = 1.2 V RE = 1.2/Ic = 1.2/4.5mA = 0.267 KΩ (IE ≈ IC)

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RC: Choose VCE = VCC /2 12/2 = 6V Apply KVL in CE loop: VCC – ICRC – VCE – VRE = 0 12 – 4.5Rc – 6 – 1.2 = 0 RC = 1.o7 KΩ

Select

R1 and R2: VB = VBE + VE = 0.7 + 1.2 = 1.9 V

We know

R2 = 0.158R1 + 0.158R2

0.8416R2 = 0.158R2

R1 = 5.33R2

Let us assume R2 = 4.7KΩ R1 = 25 KΩ Choose R1 = 27KΩ

By pass capacitor CE:

Let

At f = 100 Hz;

Choose CE = 47 µF (electrolytic)Cc1 and CC2: Assume CC1= CC2=0.47 µF (ceramic)To design:

CC1 =? CC2 =?

PROCEDURE:

B] To find Frequency response:

1) Connect the circuit as shown in Fig. No. (1), set VCC = 12 V D.C.

2) Apply a sine wave of 50 mV (p-p) from the Function Generator.

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RE = 270 Ω

RC = 1KΩ

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3) Keep the frequency of the Function Generator in mid band range i.e. around 2 KHz. Increase amplitude of input signal till the output signal is undistorted. (CRO at output)

Measure Vi amplitude = _____Volt for corresponding maximum undistorted output. Measure Vo amplitude = _____Volt The ratio [Vo / Vi] max gives the maximum undistorted gain (Amid) of the amplifier. 4) Now Vary the input sine wave frequency from 10 Hz to 1 MHz in suitable steps and measure the output Vo of the Amplifier at each step using CRO or AC Millivoltmeter (The input Vi must remain constant through the Frequency range).

5) Note down the reading in table given and plot the graph of frequency v/s. Gain in dB, determine Bandwidth and G.B.W product (G.B.W. = Amid x B.W.).

PROCEDURE:

C] To measure Zi:

1) Connect the circuit as shown in Fig. No (4).

2) Set the following DRB to minimum (0 Ω) I/P sine wave amplitude to 50 mV (p-p) I/P sine wave frequency to 10 KHz

3) Measure Vo (p-p). Let Vo = Va (say)

4) Increase DRB till Vo = Va/2. The corresponding DRB value gives Zi.

D] To measure Zo:


2) Set the following DRB to its maximum resistance value I/P sine wave amplitude to 50 mV (p-p) I/P sine wave frequency to 10 KHz

3) Measure Vo (p-p), let Vo = Vb(say)

4) Decrease DRB till Vo = Vb/2. The corresponding DRB value gives Zo.

FREQUENCY RESPONSE CURVE:

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Fig. No (3)

TO MEASURE Zi:

Fig. No (4)

TO MEASURE Zo:

Fig. No (5)

RESULT:

1] Q Point : ________________________

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2] Bandwidth (Bw) : ________________________ Hz

3] G.B.W product : ________________________

4] Input Impedance (Zi) : ________________________

5] Output Impedance (Zo) : _________________ _______

**************************************************************************BJT Darlington Emitter Follower

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Fig. No (1) Circuit Diagram of BJT Darlington Emitter Follower

Fig. No (2) Biasing Circuit BJT Darlington Emitter Follower TABULAR COLUMN:

Vin = 1V (p-p)SL NO

FREQUENCYin Hz

Vo(p-p)

in VoltsAv=Vo/Vi POWER GAIN

in dB= 20log10 Av

EXPERIMENT NO: 02

BJT Darlington Emitter Follower

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AIM: To determine experimentally and a) To plot the frequency response of Darlington Emitter Follower and b) To measure Zi , Zo and find the Current gain Ai.

EQUIPMENTS AND COMPONENTS REQUIRED: SLNO


1. Power Supply 0 – 30 V / 2 Amp D.C. 012. A.C.milli Voltmeter(or Digital Multimeter) 013. Function Generator 0 – 3 MHz, 0 – 20 V(p-p) 014. CRO Analog, 30 MHz, Dual

Channel01

5. Terminal Board -- 016. Capacitors 0.47 µF (Ceramic) 027. DRB -- 028. Resistors 1.5 KΩ

68 KΩ100 KΩ *(all ½ Watt)

010101


PROCEDURE: A] To find Q point:

1) Connect the circuit as shown in the Fig. No. (2)

2) Switch on the power supply and set +12V D.C. as VCC.

3) Measure the DC Voltage using CRO or DC Voltmeter at the VB2, Collector VC2 and emitter VE2 with respect to Ground. Then VCE2 = VC2 – VE2

IC2 = IE2 = VE2 / RE

so Q point = (VCE2, IC2)

B] To find Frequency response: 1) Connect the circuit as shown in Fig. No. (1), set VCC = 12 V d.c.

2) Apply a sine wave of 1 V peak to peak amplitude (Vi = 1V p-p) from the Function Generator.

3) Vary the input sine wave frequency from 10 Hz to 1 MHz in suitable steps and measure the output Vo of Darlington Emitter Follower circuit at each step using CRO or AC milivoltmeter (The input Vi must remain constant through the Frequency range).

4) Note down the reading in table given and plot the graph of frequency v/s. Gain in dB.

DESIGN: Let VCC = 12 V D.C. IC2 = 4 mA, β = 100 (for SL 100)

Chose VE2 = VCC / 2 = 12/2 = 6V

RE = 6 / 4mA = 1500 Ω

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VB1 = VBE1 + VBE2 + VC2

= 0.7+0.7+6 = 7.4 V

We know

R2 = 0.616R1 + 0.616R2

0.383R2 = 0.616R1

R2 = 1.61R1

Let R2 = 100 KΩ R1 = 62.11

Choose R1 = 68 KΩ (nearest standard Resistance value)

Choose CC1 = CC2 = 0.47 μF

CURRENT GAIN [Ai]: Vo / Zo Vo Zi

[Ai] Io/Ii = ------------- = ---------. --------- Vi / Zin Vi Zo

Since Vo = Vin Ai = Zin / Zo

PROCEDURE:

C] To measure Zi:


2) Set the following DRB to minimum (0 Ω) I/P sine wave amplitude to 1V (p-p)

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RE = 1.5KΩ

12


I/P sine wave frequency to 10 KHz

3) Measure Vo (p-p). Let Vo = Va (say)

4) Increase DRB till Vo = Va/2. The corresponding DRB value gives Zi.

D] To measure Zo:


2) Set the following DRB to its maximum resistance value I/P sine wave amplitude to 1V (p-p) I/P sine wave frequency to 10 KHz

3) Measure Vo (p-p), let Vo = Vb (say)

4) Decrease DRB till Vo = Vb/2. The corresponding DRB value gives Zo.

FREQUENCY RESPONSE CURVE:

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Fig No. : (3)

TO MEASURE Zi:

Fig. No (4)

TO MEASURE Zo:

Fig. No (5)

RESULT:

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1] Q Point : ________________________

2] Bandwidth (Bw) : ________________________Hz

3] CURRENT GAIN [Ai] : ________________________

4] Input Impedance (Zi) : ________________________

5] Output Impedance (Z0) : _________________ _______

***************************************************************VOLTAGE SERIES FEEDBACK AMPLIFIER

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Fig. (1) Circuit Diagram of Voltage Series Amplifier without feedback

Fig. (2) Circuit Diagram of Voltage Series Amplifier with feedback

EXPERIMENT NO.: 03

VOLTAGE SERIES FEEDBACK AMPLIFIER

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AIM: To determine experimentally and a) To plot the frequency response of a two stage R C- Coupled Amplifier with and without feedback, b) To measure the Gain with and without feedback and

c) To measure input impedance (Zi) and output impedance (Zo) with and without feedback.

EQUIPMENTS AND COMPONENTS REQUIRED: SLNO

NAME OF EQUIPMENTS/ COMPONENTS SPECIFICATIONS QTY.

1. Power Supply 0 – 30 V / 2 Amp D.C. 012. A.C.milli Voltmeter(or Digital Multimeter) 013. Function Generator 0 – 3 MHz, 0 – 20 V(p-p) 014. CRO Analog, 30 MHz, Dual Channel 015. Terminal Board -- 016. Capacitors 0.47 µF (Ceramic)

47 µF (Electrolytic)0302

7. DRB -- 018. Resistors 180 Ω

330 Ω470Ω 1 KΩ 4.7 KΩ10 KΩ15 KΩ *(all ½ Watt)

01010102020102


PROCEDURE: Amplifier without Feed back;1] Connect the circuit as shown in Fig. (1), set VCC = 12 V D.C.2] Apply a sine wave to the first stage of amplifier with amplitude say 20 mV (p-p) from the Function Generator. 3] Keep the frequency of the Function Generator in mid band range i.e. around 2 KHz. Increase amplitude of input signal till the output signal is undistorted. (CRO at output)

Measure Vi amplitude = _____Volt for corresponding maximum undistorted output. Measure Vo amplitude = _____Volt The ratio [Vo / Vi] max gives the maximum undistorted gain [A] of the amplifier without feedback.4] Now Vary the input sine wave frequency from 10 Hz to 1 MHz in suitable steps and measure the output Vo of the Amplifier at each step using CRO or AC Millivoltmeter (The input Vi must remain constant through the Frequency range). 5] Note down the reading in table given and plot the graph of frequency v/s. Gain in dB, determine Bandwidth. Note: To measure Zi and Zo repeat the same procedure given in RC Coupled Amplifier.

DESIGN:Let VCC = 12 V, IC = 4 mAChoose VCE = VCC / 2 = 12 / 2 = 6V

Assuming VE = VCC / 6 = 12 / 6 = 2 V

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We know VE = IE x RE = 2 V

RE = 2 / IE = 2 / IC = 2 / 4mA = 0.500 K (IE ≈ IC) RE = 500 Ω For I stage split RE into two parts. RE = 180 Ω + 330 Ω

Applying KVL to the collector emitter loop RC: VCC – ICRC – VCE – VE = 0

RC = 1KΩ VB = VBE + VE = 0.7 + 2 = 2.7 V

=

R2 = 0.225R1 + 0.225R2

0.775R2 = 0.225R1

R2 = 0.29R1

R2 = 3.44R2

Let R2 = 4.7 KΩ then R1 = 16.18 KΩ Choose R1 = 15KΩ

Design of second stage is same as that of first stage. Use 470 Ω as Re.

Let CE = 50 µF≈ 47 µF for both the stages.Coupling capacitors Ci = CC = CO = 0.47 µF

The feedback factor

Ω

The feedback resistor Rf should be much greater than RC. Should be between 0.01 to 0.1.

Let Rf = 10 KΩ then

Hence is within the usual chosen values 0.01 to 0.1

PROCEDURE:

Amplifier with Feed back;

1] Connect the circuit as shown in Fig. (2), set VCC = 12 V D.C.

2] Apply a sine wave to the first stage of amplifier with amplitude say 25 mV (p-p) from the Function Generator.

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3] Keep the frequency of the Function Generator in mid band range i.e. around 2 KHz. Increase amplitude of input signal till the output signal is undistorted. (CRO at output)

Measure Vi amplitude = _____Volt for corresponding maximum undistorted output. Measure Vo amplitude = _____Volt The ratio [Vo / Vi] max gives the maximum undistorted gain [A mid] of the amplifier with feedback.

4] Now Vary the input sine wave frequency from 10 Hz to 1 MHz in suitable steps and measure the output Vo of the Amplifier at each step using CRO or AC Millivoltmeter (The input Vi must remain constant through the Frequency range).

5] Note down the reading in table given and plot the graph of frequency v/s. Gain in dB, determine Bandwidth.

Note: To measure Zi and Zo repeat the same procedure given in RC Coupled Amplifier.

TABULAR COLUMN:

Vin = 20 mV(p-p)FREQ.in Hz

Vo(p-p)

in Voltswithoutfeedback

Vo(p-p)

in Voltswithfeedback

Av

=Vo/Vi

Av fb

=Vo/Vi

GdB = 20 log10 (Vo/Vi )

Gfb dB = 20 log10(Vo/Vi )

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RESULT:

1] Q Point : ________________________

2] Bandwidth without Feedback : ________________________ Hz

3] Bandwidth with Feedback : ________________________

4] Input Impedance without Feedback : ________________________

5] Input Impedance with Feedback : ________________________

6] Output Impedance without Feedback : _________________ _______

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7] Output Impedance with Feedback : _________________ _______

***************************************************************RC PHASE SHIFT OSCILLATOR

Fig. (1)

Circuit Diagram of R C Phase Shift Oscillator

DESIGN: Amplifier Design: Let VCC = 12 V, IC = 4 mA, hfe = 100

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Let VE = 2 V, VCE = VCC / 2 = 12 / 2 = 6 V RE = VE / IE = VE / IC = 2 / 4mA = 0.5 KΩ = 500 Ω (IE ≈ IC) Choose RE = 470 Ω To Find RC ;

VCC – ICRC – VCE – VE

RC = 1KΩ To find R1 and R2 ; From the base circuit in the above figure,

We know VB = VBE +VE = 2 + 0.7 = 2.7 V

0.225R1 + 0.225R2 = R2 0.225R1 = 0.775R2 R1 = 3.44R2 Choose R2 = 6.8 KΩ Then R1 = 23.3 KΩ Choose R1 = 22 KΩ

EXPERIMENT NO.:04

RC PHASE SHIFT OSCILLATOR

AIM: To design and test a RC Phase Shift Oscillator for a given frequency


SLNO


1. Power Supply 0 – 30 V / 2 Amp D.C. 012. CRO Analog, 30MHz, Dual Channel 013. Terminal Board -- 014. Capacitors 0.01 µF

0.47 µF0301

5. Potentiometer 10 KΩ 016. Resistors 470 Ω

1 KΩ3.9 KΩ6.8 KΩ 22 KΩ *(all ½ Watt)

0101020101

7. Transistor BC107 018. Patch cords, Connecting Wires,etc. 01

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PROCEDURE: 1] Connect the circuit as shown in Fig. (1).

2] Switch on the D.C. power supply.

3] Observe the output Vo on CRO. The 10 K pot is adjusted to get a stable output on the CRO. 4] Measure the frequency of the output wave. 5] Compare the measured frequency with theoretical value.

6] With respect to output at point P, observe the waveforms at point Q, R and S on the CRO. We can see that phase shift at each point being 60°, 12° and 180° respectively.7] repeat the design for different value of frequency (in Audio range only). At each case Compare the generated frequency with theoretical value.

Note: a) The last Resistor in the phase shifting network is chosen to be a 10 K pot. This is done to get a overall phase shift of 180° at frequency of Oscillations. b) The minimum hfe required for the transistor to oscillate is Hfemin = 23 + 29(R / RC) + 4(RC / R) Where RC = 1 KΩ and R = 2.2 KΩ (Phase Shifting Network) Hfe min = 23 + 29(2.2K / 1K) + 4 = 1K / 2.2K ≈ 89 The transistor should be chosen to have a value of hfe greater than 89.

Choose Coupling Capacitor CC = 0.47 µFand CE = 47 µF

Design of phase shifting network: The frequency of oscillations is determined by phase shifting network. The oscillating frequency for the above circuit is given by

the ratio Rc / R is usually < 1

Let f = 1 KHz (Audio frequency in the range 20 Hz to 20 KHz)

and R = 3.9 KΩ Since Rc = 1KΩ we get

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23


C = 0.01 µF

RESULT: ______________

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***************************************************************************FET HARTLEY OSCILLATOR

Fig. (1) Circuit Diagram of FET Hartley OscillatorDESIGN: To design a Hartley Oscillator to produce sinusoidal oscillations of 100 KHz.

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Use FET BFW 11 with the following specifications; VDS = 10 V, ID = 1 mA , VGS = - 0.3 V Oscillator Frequency f = 100 KHz A) Select RG = 1 MΩ

B) VDD = VDS + ID (RD + RS) f = = 100 x 103 =

15 = 10 + (1 x 10-3) (RD + RS) where Leq. = L1 + L2

5 x 103 = RD + RS c) In designing Split Inductors, the ratio

VGS = (ID) (RS) or L2 = 2L1

+ 0.3 = (1 mA) RS Let L1 = 1 mH L2 = 2.2 mH Leq = 3.2 mH So 0.3 / (1 x 10-3) = Rs

RS = 0.300 KΩ D) = 791.57 pF

Select RS = 330 Ω Choose C=1000 pF Select RD = 4.7 KΩ E) Choose Cs = 47 µF and VDD = 15 V, VDS = 10 V, RD = 4.7 KΩ F) Choose CC1 = CC2= 0.1 µF

EXPERIMENT NO.: 05

FET HARTLEY OSCILLATOR

AIM: To design and test a FET Hartley Oscillator for a given frequency


SLNO


1. Power Supply 0 – 30 V / 2 Amp D.C. 012. CRO Analog, 30 MHz, Dual Channel 013. Terminal Board -- 014. Capacitor 47 µF

0.1 µF1000 pF (or DCB)

010201

5. Inductance 1 mH (or DIB)2.2 mH (or DIB)

0101

8. Resistors 330 Ω4.7 KΩ1 MΩ *(all ½ Watt)

010101

9. FET BFW10 or BFW11 0110. Patch cords, Connecting Wires,etc. 01

PROCEDURE: 1] Connect the circuit as shown in Fig. (1).


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26


3] Observe the output on CRO screen. 4] Measure the frequency of the output wave. 5] Compare the measured frequency with theoretical value.

6] Repeat the design for different value of frequency. At each case compare the generated frequency with theoretical value.

RESULT: ______________

***********************************************************************

FET COLPITT’S OSCILLATOR

Fig. (1) Circuit Diagram of Colpitt’s Oscillator

DESIGN: To design the FET Colpitts Oscillator to meet the following specifications; Oscillation frequency f = 100 KHz Use FET BFW 11 with the following specifications; VDS = 10 V, ID = 1 mA, VGS = - 0.3 V A) Select RG = 1 MΩ

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27


B) VDD = VDS + ID (RD + RS) 15 = 10 + (1 x 10-3) (RD + RS)

5 x 103 = RD + RS VGS = (ID) (RS) + 0.3 = (1 mA) RS So 0.3 / (1 x 10-3) = RS RS = 0.300 KΩ Select RD = 4.7 KΩ VDD = 15 V, VDS = 10 V, RD = 4.7 KΩ

EXPERIMENT NO.: 06

FET COLPITT’S OSCILLATOR

AIM: To design and test a FET Colpitts Oscillator for a given frequency


SLNO


1. Power Supply 0 – 30 V / 2 Amp D.C. 012. CRO Analog, 30 MHz, Dual Channel 013. Terminal Board -- 014. Capacitor 47 µF

0.1 µF1000 pF (or DCB)2200 pF (or DCB)

01020101

5. Inductance 3.6mH (or DIB) 028. Resistors 330Ω

4.7 KΩ1 MΩ *(all ½ W)

010101

9. FET BFW10 or BFW11 0110. Patch cords, Connecting Wires,etc. 01

PROCEDURE:

1] Connect the circuit as shown in Fig. (1).


3] Observe the output waveform on CRO screen.

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28


4] Measure the frequency of the output waveform. 5] Compare the measured frequency with theoretical value.

6] Repeat the design for different values of frequency. At each case compare the generated frequency with theoretical value.

C) Tank Circuit Design: Oscillation frequency f = 100 KHz

Where

Assume C1= 1000 pF and C2 = 2200 pF

D) Choose Cs = 47 µF and E) Choose CC1 = CC2= 0.1 µF

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29


RESULT: ______________

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30


***************************************************************1. Diode Shunt Clipping above Vr (reference voltage) or Positive Peak Clipping Circuit.

Fig. (1) Circuit Diagram of Diode Shunt Input output Waveforms Transfer Characteristic Clipping above Vr

Rf =10 Ω (Forward Resistance of Diode) Rr =10 KΩ (Reverse Resistance of Diode)

DESIGN: The output to be clipped above 2 V.

So Vo (max) = +2 V

From the Fig. (1)

Vo = Vo (max) – Vr + Vref

Where Vr is Diode drop which is nearly equal to 0.6 V.

So Vref = Vo (max) – Vr

= 2 – 0.6 = 1.4 V

Select the input amplitude more than 3Volts.

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31


R = 10 KΩ

EXPERIMENT No.: 07

DIODE CLIPPING CIRCUITS

AIM: To design the different types of Clipping Circuits and also to obtain the transfer characteristics Of different types of Clipping Circuits.

EQUIPMENTS AND COMPONENTS:

SLNO


1. Dual Power Supply Variable 0 – 30 V / 2 Amp D.C. 012. Function Generator 0 – 3 MHz, 0 – 20 V(p-p) 013. CRO Analog, 30 MHz, Dual Channel 014. Connecting Board 015. Resistance 10 KΩ (½ Watt) 016. CRO Probe -- 037. Diode 1N4007 028. Patch cords, Connecting Wires,etc.

PROCEDURE:

1. Circuit is wired up as shown in Fig.(1) and a sinusoidal signal of 1 KHz and amplitude of 6 V(p-p) (Peak amplitude should be greater then clipping level) is applied at input Vi.

2. Observe output signal on the CRO and verify it with the given waveforms.

3. Apply Vi and Vo to the X and Y channel of CRO and transfer characteristics is obtained using X – Y mode in CRO.

RESULT: ____________________

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32


2. Diode Shunt Clipping below Vr (reference voltage) or Negative Peak Clipping Circuit.

Fig. (2) Circuit Diagram of Diode Input output Waveforms Transfer Characteristic Shunt Clipping below Vr

DESIGN: Output voltage be clipped at + 2 Volt. Vo (max) = Vref = 2 V

R = 10KΩ

PROCEDURE:

1. Circuit is wired up as shown in Fig. (2) and a sinusoidal signal of 1 KHz and amplitude of 6 V(p-p) (Peak amplitude should be greater then clipping level) is applied at input Vi.



RESULT: ____________________

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33


3 Diode Series Clipping above Vr (reference voltage) or Positive Peak Clipping Circuit

Fig. (3) Circuit Diagram of Diode Input output Waveforms Transfer Characteristic Series Clipping above Vr


R = 10KΩ

PROCEDURE:

1. Circuit is wired up as shown in Fig. (3) and a sinusoidal signal of 1 KHz and amplitude of 6 Vp-p (Peak amplitude should be greater then clipping level) is applied at input Vi.



RESULT: ____________________

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34


4. Diode Series Clipping below Vr (reference voltage) or Negative Peak Clipping Circuit.

Fig. (4) Circuit Diagram of Diode Input output Waveforms Transfer Characteristic Series Clipping below Vr


R = 10KΩ

PROCEDURE:

1. Circuit is wired up as shown in Fig. (4) and a sinusoidal signal of 1 KHz and amplitude of 6V(p-p) (Peak amplitude should be greater then clipping level) is applied at input Vi.



RESULT: ____________________

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35


5. CLIPPING TWO INDEPENDENT LEVEL OR SLICER

Fig. (5) Circuit Diagram Input output Waveforms Transfer Characteristic

DESIGN: To clipping the signal below 2 Volt and above 4 Volt levels Let VR1 > VR2

1] Vo max = 4 V, i.e. Vo max = VR1 + Vr

VR1 = Vo max – Vr

= 4 – 0.6 so 2] Vo min = 2 V i.e. Vo min = VR2 – Vr

VR2 = Vo min + Vr

= 2 + 0.6

VR2 = 2.6 V

If

R = 10KΩ

PROCEDURE:1. Circuit is wired up as shown in Fig. (5) and a sinusoidal signal of 1 KHz and a suitable amplitude (Peak amplitude should be greater then clipping level) is applied at input Vi.

2. Observe output signal on the CRO and verify it with the given waveforms.3. Apply Vi and Vo to the X and Y channel of CRO and transfer characteristics is

obtained using X – Y mode in CRO.

RESULT: _______________

___________________________________________________________________________


VR1 = 3.4 V

36


6. DOUBLE ENDED CLIPPER TO GENERATE A SYMMETRICAL SQUARE WAVE OR SQUARER

Fig. (6) Circuit Diagram of Double ended Input output Waveforms Transfer Characteristic Clipper or squarer

DESIGN: To generate a symmetrical square wave Vref =± 4 Volts

i.e. VR = VR1 = VR2 = Vref = 4 Volts

Vo max = VR + Vr

VR = Vo max - Vr = 4 – 0.6 So

R = 10KΩ

PROCEDURE:

1. Circuit is wired up as shown in Fig.(6) and a sinusoidal signal of 1 KHz and a suitable amplitude (Peak amplitude should be greater then clipping level) is applied at input Vi.



RESULT: _______________

7. CLIPPER CIRCUIT TO CLIP THE CENTER PORTION AND TRANSMIT THE PEAKS OF SINUSOIDAL SIGNAL

___________________________________________________________________________


VR = 3.4 V

37


Fig. (7) Circuit Diagram to clip the center portion Input output Waveforms & transmit the peak of sinusoidal signal

Fig.(8) Transfer Characteristic

DESIGN: To clip a sine wave between +2 V and -3 V level. Vo = VR1 + 0.6 VR1 = 2 – 0.6 = 1.4V VR1 = 1.4 V -3 = VR2 – 0.6 -VR2 = 3 – 0.6 = 2.4 VR2 = -2.4 V

If

R = 10 KΩ

PROCEDURE:1. Circuit is wired up as shown in Fig. (7) and a sinusoidal signal of 1 KHz and suitable amplitude (Peak amplitude should be greater then clipping level) is applied at input Vi.2. Observe output signal on the CRO and verify it with the given waveforms.3. Apply Vi and Vo to the X and Y channel of CRO and transfer characteristics is

obtained using X – Y mode in CRO.

RESULT: ______________

***************************************************************1] POSITIVE PEAK CLAMPING:

___________________________________________________________________________


38


Fig. (1) Circuit Diagram of Positive Clamping Circuit

DESIGN:Clamping circuit to clamp positive peak at +3V.The input waveform has a frequency of1 KHz sine wave or square wave with suitable amplitude.Vo max = Vref + Vr

Vref = Vo max – Vr = 3 – 0.6

Given frequency 1 KHz

So

= 1mSec

RC = 10 T RC = (10) 1mSec = 10 mSec Rf = 10 Ω, Rr= 10 MΩ

C = 10 mSec / 10 K = 1µF If

Fig. (2) Input and Output waveforms of a Negative Clamping Circuit

Note: Set Vref = 0 and observe the output for both sine and square wave input.

EXPERIMENT NO.: 08

CLAMPING CIRCUITS

___________________________________________________________________________


Vref = 2.4 V

Choose RC » T

R = 10 KΩ

39

3V

0


AIM: To design and test a

1] Positive Clamping circuit and 2] Negative Clamping circuit for given reference voltage.

EQUIPEMENTS AND COMPONENTS:

SLNO


1. Single Power Supply 0 – 30 V / 2 Amp D.C. 012. Function Generator 0 – 3 MHz, 0 – 20 V(p-p) 013. CRO Analog, 30MHz, Dual Channel 014. Connecting Board 015. Resistance 10 KΩ (½ Watt) 016. Capacitor 1 µF 017. Diode 1N4007 018. CRO Probe -- 039. Patch cords, Connecting Wires,etc.

PROCEDURE:

1] Positive Clamping Circuit;

a) Connect the circuit as shown in Fig. (1)

b) Apply input sinusoidal signal of amplitude 6 V p-p and frequency of 1 KHz [Peak amplitude of input signal must be grater than clamping level]

C) Connect the output to CRO and compare the output with the given waveforms.

d) For the same circuit, give a square wave input and observe the output and compare output with given waveforms

e) Make Vref = 0 and observe the output.

2] NEGATIVE PEAK CLAMPING:

___________________________________________________________________________


40


Fig. (3) Circuit Diagram of Negative Clamping Circuit

DESIGN:

Clamping Circuit to clamp Negative peak of the output voltage at -3V.

Vo min = Vref - Vr

Vref = Vo min + Vr = -3 + 0.6

Fig.(4) Input and Output waveforms of a Negative Clamping Circuit.

Note: Set Vref = 0 and observe the output for both sine and square wave input.

PROCEDURE:

2] Negative Clamping Circuit;

___________________________________________________________________________


Vref = -2.4 V

41

0 0


a) Connect the circuit as shown in Fig. (3)

b) Apply input sinusoidal signal of amplitude 6 V(p-p) and frequency of 1 KHz [Peak amplitude of input signal must be grater than clamping level]

C) Connect the output to CRO and compare the output with the given waveforms.

d) For the same circuit, give a square input and observe the output and compare output with given waveforms

e) Make Vref = 0 and observe the output.

RESULT: ________________

***************************************************************OP-AMP AS INVERTING AMPLIFIER:

___________________________________________________________________________


42


Fig. (1) Circuit Diagram for Op-Amp as an Inverting Amplifier.

DESIGN: Let the gain of Op-Amp be 5. i.e. Av = 5 [Inverting Amplifier Gain] Av = -Rf/Ri

Select Rf = 47 KΩ, Ri = 10 KΩ If Vi = 1 Vp-p and Frequency = 1 KHz

Then Vo = -AV.Vi ≈ - 5Vi ≈ -5 Vp-p.

EXPERIMENT NO: 9

OP-AMP CIRCUITS___________________________________________________________________________


43


AIM: To design the following Op-Amp Circuits:

a) Inverting Amplifierb) Non-Inverting Amplifierc) Voltage Follower

and To observe the input & output wave forms and To determine the Voltage Gain Av.


SLNO


1. Power Supply ±12 V / 2 Amp D.C. 012. Function Generator 0 – 3 MHz, 0 – 20 V(p-p) 013. CRO Analog, 30MHz, Dual Channel 014. Terminal Board 015. Resistor 2.2 KΩ

10 KΩ 22 KΩ47 KΩ *(all ½ Watt)

01010101

6. CRO Probe -- 037. I.C. Op-Amp µA741 018. Patch cords, Connecting Wires,etc.

PROCEDURE:

a) Inverting Amplifier

(1) Connect the Inverting amplifier Circuit as shown in the fig.(1)using designed value of Ri and Rf.

(2) Switch on the fixed Power Supply (±12 V D.C. / 2 Amp).

(3) Apply input voltage Vin of 1 V D.C. and measure the outputi.e. Vo = (-Rf/Ri) Vi in Volts.

[Verify the same with different value of D.C. input Voltages.]

(4) Apply an A.C. sinusoidal signal (using Function Generator) of 1KHz Frequency and amplitude of 1 V(P-P) as the input.

(5) Observe the inverted, amplified output signal on CRO and measure the Voltage levels of input and output signals i.e. Vin max. and Vo max.

Voltage Gain = [Avf] =- Vo max / Vin max = -Rf/Ri = -------

(6) Frequency response can be obtained by applying variable value of Frequency signal having constant amplitude 1 V(p-p) as input.

OP-AMP AS NON-INVERTING AMPLIFIER:

___________________________________________________________________________


44


O/P VO = [1 + (Rf/Ri] Vi = AVfVi

Fig. (2) Circuit Diagram for Op-Amp as Non-Inverting Amplifier

DESIGN:

Let the Non-Inverting Amplifier Gain = 11 Avf = Vo / Vi = [1 + Rf / Ri] = 11

so Rf / Ri = 11-1 = 10. Select Rf = 22 KΩ and Ri = Rf / 10 = 22 / 10 KΩ = 2.2 KΩ

Select Ri = 2.2 KΩ

Practical AVf = [1+ (22 KΩ / 2.2 KΩ)] Vo = 11 Vi

If Vi = 1 Vp-p and Frequency = 1KHz

Hence Vo = 11[1Vp-p] = 11Vp-p.

PROCEDURE:

b) OP-AMP AS NON-INVERTING AMPLIFIER;

(1) Connect the Non-Inverting Amplifier circuit as shown in Fig.(2) using

___________________________________________________________________________


45


designed value of Ri and Rf.

(2) Switch on the D.C. power supply ±12 V D.C. /2 Amp.

(3) Apply an A.C. sinusoidal signal (using Function Generator) of 1 KHz Frequency and amplitude of 0.5 V(p-p). as the input.

(3) Observe the input and output waveforms on CRO and measure Vin max.,Vo max. and Voltage Gain Avf

Voltage Gain [Avf] = Vo max. / Vin max. = [1+ (Rf / Ri)] = -----------

OP-AMP AS VOLTAGE FOLLOWER

___________________________________________________________________________


46


Fig. (3) Circuit Diagram for Op-Amp as a Voltage Follower

DESIGN: The output Voltage Vo precisely follows the input signal Vi

Avf = 1 i.e. Vo = Vi

PROCEDURE:

b) OP-AMP AS VOLTAGE FOLLOWER;

___________________________________________________________________________


47


(1) Connect the Voltage Follower circuit as shown in Fig.(3) (2) apply a D.C. input Voltage of about 2, 3, 4 and 5 Volts at pin No. 3 (of Op-amp) as input and measure the output voltage Vo at Pin No.6

(3) verify the output Vo = Vi i.e. If Vi = +1 V then Vo = +1 V

Vi = +2 V then Vo = +2 V

Vi = +5 V then Vo = +5 V

Vi = -2 V then Vo = -2 V

(4) Apply a sinusoidal input signal of 2 Vp-p and frequency of 1 KHz at pin No.3 and observe the output signal on CRO.

(5) Measure the Vin max. and Vo max. and calculate Voltage Gain AVf

Voltage Gain = [Avf] = Vo max. / Vin max. = 1 (verify)

***************************************************************************a) OP-AMP AS INVERTING SUMMER AMPLIFIER

___________________________________________________________________________


48


Fig. (1) Circuit Diagram for OP-Amp as Inverting Summer Amplifier with D.C. input.

DESIGN: Output Vo = - [(Rf/R1) V1 + (Rf/R2) V2 + (Rf/R3) V3]

If R1 = 100 KΩ, R2 = 10 KΩ, R3 = 1 KΩ and Rf = 10 KΩ

so Vo = - [0.1V1 + V2 + 10V3]

If V1 = 10 Volts, V2 = 1 Volts and V3 = 0.5Volts Then Vo = - [(0.1)10 + (1) + (10) 0.5] = - [1+1+5]

Vo = -7 Volts

Fig. (2) Circuit Diagram for OP-Amp as Fig. (3) Waveforms Inverting Summer Amplifier with A.C. input.

Select R1, R2, R3 and Rf values

EXPERIMENT NO.: 10

OP-AMP AS SUMMER AMPLIFIER

___________________________________________________________________________


49


AIM: To design the Summer Circuits using Op-Amp;

a) Op-Amp as Inverting Summer Amplifier andb) Op-Amp as Non-Inverting Summer Amplifier


SLNO


1. Power Supply ±12 V / 2 Amp D.C. 012. Function Generator 0 – 3 MHz, 0 – 20 V(p-p) 013. CRO Analog, 30 MHz, Dual Channel 014. Terminal Board -- 015. Resistance 1 KΩ

10 KΩ 100 KΩ *(all ½ Watt)(or any other suitable values)

010201


PROCEDURE:

a) Op-Amp as Inverting Summer Amplifier;

1] Connect the circuit as shown in the Fig. (1).

2] With chosen value of Rf, R1, R2 and R3 provide D.C. voltage V1, V2 and V3 from D.C. Power supply.

3] Measure the output voltage and compare it with designed values.

4] For Inverting Summer Amplifier with A.C. signal, connect the circuit as shown in Fig. (2) and repeat the above procedure providing A.C. sinusoidal signal of frequency 1 KHz as common source. Observe the output waveform. Compare it with the designed values

RESULT: _______________

b) OP-AMP AS NON-INVERTING SUMMER AMPLIFIER

___________________________________________________________________________


50


Fig. (4) Circuit Diagram for OP-Amp as Non-Inverting Summer Amplifier with D.C. input.

DESIGN:

Select 5Rf+Rin

Then

Fig. (5) Circuit Diagram for OP-Amp as Fig. (6) Waveforms Non-Inverting Summer Amplifier with A.C. input. Select R1, R2, R3 and Rf values

PROCEDURE:b) Op-Amp as Non-Inverting Summer Amplifier

1] Connect the circuit as shown in the Fig. (4).

2] With chosen value of Rf, R1, R2 and R3 provide D.C. voltage V1, V2 and V3 from

___________________________________________________________________________


51


D.C. Power supply.

3] Measure the output voltage and compare it with designed values.

4] For Non-Inverting Summer Amplifier with A.C. signal, connect the circuit as shown in Fig. (5) and repeat the above procedure providing A.C. sinusoidal signal of frequency 1 KHz as common source and observe the output waveform. Compare it with the designed values.

RESULT: _________________

***************************************************************************OP-AMP AS INTEGRATOR

___________________________________________________________________________


52


Fig. (1) Circuit Diagram for Op-Amp as an Integrator DESIGN:

1] For RC = 10T

Since input is given to inverting terminal

Requirement of integration is RC >> T

Where T is the time period of input signal

Consider the square wave of frequency 1 KHz

So T = 1 / f = 1 mSec.

RC = T

Let RC = 10T = 10 mSec.

Let C = 0.1 µF then R = (10) (10-3) / (0.1) (10-6) = 100 KΩ

Cf = 0.1 µF, Rc = 100 KΩ and Rf = 1MΩ

2] Design for RC = T

3] Design for RC = 0.1 T

EXPERIMENT NO.:11

OP-AMP AS INTEGRATOR AND DIFFERENTIATOR

___________________________________________________________________________


53


AIM: To design Op-Amp as (a) an Integrator and

(b) Differentiator.


SLNO


1. Power Supply ±12 V / 2 Amp D.C. 012. Function Generator 0 – 3 MHz, 0 – 20 V(p-p) 013. CRO Analog, 30MHz, Dual Channel 014. Terminal Board 015. Resistance 1 KΩ

10 KΩ100 KΩ 1 MΩ *( all ½ Watt)

01010101

6. Capacitor 0.1 µF 017. CRO Probe -- 038. I.C. Op-Amp µA741 019. Patch cords, Connecting Wires,etc.

PROCEDURE: (a) Op-Amp as an Integrator ;

1] Connect the circuit as shown in Fig. (1)

2] Square wave of 1 KHz frequency and amplitude of 10 V (p-p) is applied at input.

3] R and C values are chosen according to the design.

4] The output waveform is observed on the CRO. The output triangular wave is out of phase w.r.t. input.

5] Repeat the above procedure for different value of T and C

say (RC = 10T,RC = T,RC = 0.1T). Observe and plot the waveforms. [Note: Observe the output waveform with sinusoidal signal of 1 KHz frequency and suitable amplitude as input.]

RESULT: ______________________

OP-AMP AS DIFFERENTIATOR

___________________________________________________________________________


54


Fig. (2) Circuit Diagram for Op-Amp as Differentiator

DESIGN:

The output of Differentiator is given by the equation

Requirement of Differentiator is RC << T, where T is the Time period of input signal.Consider input Square wave of F = 1 KHz and amplitude of 2 V p-p.

T = 1 mSec.

Since RfC1 << T

Let RfC1 = (1 / 10) T

RfC1 = 0.1 mSec.

Let C1 = 0.1 µF

So Rf = 0.1mSec / 0.1 µF = 1 KΩ

Rf = 1 KΩ

R1 = 10 KΩ

For Differentiator R1 = 10Rf

Rf = 10 KΩ

PROCEDURE:

(b) Op-Amp as a Differentiator;

___________________________________________________________________________


55


1] Connect the circuit as shown in Fig. (2)

2] Square wave of 1 KHz frequency and amplitude of 2 V(P-P) is applied at input.

3] R and C values are chosen according to the design.

4] The output waveform is observed on the CRO. The output will be a series of spikes.

5] Repeat the above procedure for different value of R and C

say (RC = 10T,RC = T,RC = 0.1T). Observe and plot the waveforms. [Note: Observe the output waveform with sinusoidal signal of 1 KHz frequency and suitable amplitude as input and also observe the output with triangular wave input]

RESULT: ______________________

***************************************************************************ZERO CROSSING DETECTOR (ZCD)

___________________________________________________________________________


56


Vi > Vref Vo = - Vsat

Vi < Vref Vo = +Vsat

Fig. (1) Circuit Diagram of Zero Crossing Detector Input Output Waveforms

SCHMITT TRIGGER CIRCUIT

Fig. (2) Circuit Diagram of Schmitt Trigger Input Output Waveforms

EXPERIMENT NO.:12

___________________________________________________________________________


57


ZERO CROSSING DETECTOR (ZCD) AND SCHMITT TRIGGER USING OP-AMP.

AIM: To design and study the performance of 1] Zero Crossing Detector and 2] Schmitt Trigger using Op-Amp.


SLNO


1. Power Supply ±12 V / 2 Amp D.C. 012. Function Generator 0 – 3 MHz, 0 – 20 V (p-p) 013. CRO Analog, 30 MHz, Dual Channel 014. Terminal Board 015. Resistance 10 KΩ

91 KΩ100KΩ (all ½ Watt)

020101


PROCEDURE: 1] For Zero Crossing Detector; (a) Connect the circuit as shown in Fig. (1)

(b) Give a continuously varying signal, say sinusoidal or triangular wave to the the inverting terminal of Op-Amp . Let the frequency of signal f = 1 KHz and amplitude Vi = 4 V(p-p)

(c) Connect the non-inverting terminal to ground.

(d) As Vi crosses Vref = 0 Volt each time, output changes its state as shown in the waveform. The output obtained will be a symmetrical square wave with Amplitude at ±Vsat. At each zero crossing of input, the output changes its state hence detecting the zero crossings of Vi and is called Zero Crossing Detector.

2] For Schmitt Trigger; (a) Connect the circuit as shown in Fig. (2)

(b) Connect the D.C. source at input and measure the UTP and LTP, compare them with designed value.

(c) Use a sinusoidal signal of frequency 500 Hz and 5V p-p Amplitude.

(d) Display output rectangular wave on CRO and measure UTP and LTP.

(e) Use X – Y mode and display the Hysterisis curve on CRO, measure UTP and LTP and compare it with the designed values.

(f) Also observe the input and output waveforms on CRO using Triangular wave input.DESIGN: Schmitt Trigger design for given value of UTP and LTP.

___________________________________________________________________________


58


Given UTP = -1.5 V and LTP = 0.5 V

Vcc = +12 V and –VEE = -12 V

VH = V UTP – V LTP

= 0.5 – 1.5 = 2 V

VH = (R1)/ (R1 + R2) [Vsat – (-Vsat)]

2 = (R1)/ (R1 + R2) [12 – (-12)]

2 = (R1)/ (R1 + R2) [24]

2R1 + 2R2 = 24R1

2R2 = 24R1 – 2R1

2R2 = 22R1

R2 = (22 / 2) R1

R2 = 11 R1

If R1 = 10 KΩ then

R2 =110 KΩ (use 100 KΩ + 10 KΩ)

Fig. (3) Transfer Characteristics (Hysterisis Curve)

___________________________________________________________________________


59


Fig. (4) Circuit Diagram of Schmitt TriggerDESIGN: To design a Schmitt Trigger circuit with given values of Hysterisis width VH,

UTP and LTP;

Fig. (5) Transfer Characteristics (Hysterisis Curve) Select – Vsat = -10 V and + Vsat = 10 V + Vcc = 12 V and – VEE = - 12 V

VH = 2 Volt VH = VUTP - VLTP

= - 1 – (-3) = 2 V

2R1 + 2R2 = 20R1

2R2 = 20 R1 – 2R1

2R2 = 18R1

R2 = 9R1 If R1 = 10KΩ then R2 = 90 KΩ Select R2 = 91 KΩ

***********************************************************************PRECISION FULL WAVE RECTIFIER

___________________________________________________________________________


60


Fig. (1) Circuit Diagram of Precision Full Wave Rectifier

Design: a) When Vin > 0 i.e. Vin is positive value.

Vo = (-R / R). (-R/Rin)Vin

Vo =(R/Rin)Vin

b) When Vin < 0 i.e. Vin is positive value. Vo = (1+ R/2R) (2R/3Rin) Vi

Vo = (3R/2R)(2R/3Rin)Vi

Vo =(R/Rin)Vin

If Vo = 5 Volts and Vin = 100 mV

Select R=100 KΩ Then Rin= (R) (100) (10 -3 ) 5

= (100) (10 3 )(100)(10 -3 ) 5 Rin = 2000 Ω = 2 KΩ ≈ 2.2 KΩ

Rin = 2.2KΩ

EXPERIMENT NO: 13

PRECISION FULL WAVE RECTIFIER

___________________________________________________________________________


61


AIM: Design an Op-Amp Circuit for;

1) To get an DC pulsating output of 5 Volts from a source of 100 mV,

2) To test the result for different values of input frequencies.


SLNO


1. Power Supply ±12 V / 2 Amp D.C. 012. Function Generator 0 – 3 MHz, 0 – 20 V(P-P) 013. CRO Analog, 30MHz, Dual Channel 014. Terminal Board 015. Resistance 100 KΩ

2.2 KΩ *(all ½ Watt)0401

6. CRO Probe -- 037. I.C. Op-Amp µA741 028. Diode 1N4007 029. Patch cords, Connecting Wires,etc.

PROCEDURE:

1) Rig-up the circuit as shown in Fig. (1).

2) Connect the Function Generator at the input with sinusoidal signal of frequency 1 KHz and 100 mV amplitude.

3) Observe the output on CRO.

4) Measure the amplitude and frequency of the output wave.

5) Draw the waveforms, both input and output.

6) Repeat the above procedure for different value of input frequencies.

TABULAR COLUMN:

For R=100 KΩ , Rin = 2 KΩ i.e. Gain A = 100 / 2 = 50SL NO

Vi(p-p)

in VoltsFREQUENCY

in HzVo(p-p)

in Volts

___________________________________________________________________________


62


1.2.3.4.5.6.

100mV 1 KHz 5V

WAVEFORMS:

Fig. (2) Input and output waveforms of Precision Full Wave Rectifier

RESULT: ________________

___________________________________________________________________________


63


***************************************************************************IC 723 VOLTAGE REGULATOR

___________________________________________________________________________


64


Fig. (1) IC LM723 PIN DETAILS

a) Low Voltage Regulator using IC 723 for Vo = 5V, IL = 100mA

Fig. (2) Circuit Diagram for Low Voltage Regulator using IC 723 for Vo = 5V, IL = 100mA.

EXPERIMENT NO: 14

IC 723 VOLTAGE REGULATOR

AIM: To design and test the IC 723 Voltage Regulator for the given specifications;

a) Low Voltage Regulator using IC 723 for Vo = 5 V, IL = 100mA ,

___________________________________________________________________________


65


b) High Voltage Regulator using IC 723 for Vo = 15 V, IL = 100mA


SLNO


1. Power Supply 0 – 30 V / 2 Amp D.C. 012. Voltmeter (or Digital Multimeter) 0 – 20 V D.C. 013. Ammeter D.C. 0 – 200 mA 014. DRB(Decade Resistance Box) -- 015. Terminal Board -- 016. Capacitors 0.1 µF,

100 pF (all Ceramic) 0101

7. Resistors 39 Ω680 Ω1 KΩ1.2 KΩ2.2 KΩ 2.7 KΩ *(all ½ Watt)

010101010101

8. I.C. LM 723 019. Patch cords, Connecting Wires,etc.

a) Low Voltage Regulator using IC 723 for Vo = 5V, IL = 100mA

PROCEDURE:

1) Connect the circuit as shown in the Fig. (1). 2) Vary Vin in steps of 1 Volt from 10 Volts to 25 Volts and note down the Output Voltage (output Voltage is 5 Volts). 3) Plot the graph of Vo verses Vi and find Sv.

RESULT: _________________

DESIGN OF LOW VOLTAGE REGULATOR:From the data sheet;Vref = 7 Volts, Cref = 0.1µF, Vo = 5 VoltsRSE = 0.6 / I limit, I limit = 15 mA =0.6 /15 mA = 40 Ω

RSE = 40 ΩVo = Vref (R2/R1+R2) = (7.0) (R2/R1+R2)5(R1+R2) = 7R2

2.5R1= R2

___________________________________________________________________________


66


If R1 = 1KΩ,R1 =1 K Ω

R2 = 2.5(R1) = 2.5(1 KΩ) = 2.5 KΩ ≈ 2.7 KΩSelect

R2 = 2.7 KΩ

R3 = R1R2/R1+R2 = (1 KΩ) (2.7 KΩ) / (1 KΩ) + (2.7 KΩ)

= 0.729 KΩ ≈ 680 ΩR3 =680 Ω

TABULAR COLUMN: Line Regulation Load regulation

IL = ----- Const. Vin = ----- Const.SL NO

Vin

In VoltsVo

In VoltsSL NO

RL

in ΩIL

in mAVo

In Volts

% Line Regulation = ______________ % Load Regulation = _____________

LINE REGULATION LOAD REGULATION

Fig. (3) Fig. (4)

Calculate Sv (Voltage stability Factor) = at constant IL ---------------

b) High Voltage Regulator using IC 723 for Vo = 15 V, IL = 100mA

PROCEDURE:

1) Connect the circuit as shown in the Fig. (5).

2) Vary Vin in steps of 1 Volt from 18 Volts to 30 Volts and note down the Output Voltage (output Voltage is 15 Volts).

3) Plot the graph of Vo verses Vi and find Sv.

___________________________________________________________________________


67

Vin in Volts

Vo

inVolts

IL in mA

Vo

inVolts


DESIGN OF HIGH VOLTAGE REGULATOR:

From the data sheet;

Vref = 7 Volts, Cref = 0.1µF, Vo = 15 Volts

RSE = 0.6 / I limit, I limit = 15 mA = 0.6/15mA = 40 Ω

RSE = 40 Ω

Vo = 15 Volts

Vo = Vref(1)+(R1/R2)

15 = 7(1) + (R1/R2)

15 – 7 = 7R1/R2

8R2 = 7R1

1.142R2 = R1

If R2 = 2.2 KΩ

R2 = 2.2KΩR1 = 1.142R2

= 1.142(2.2KΩ)

R1 = 2.7KΩ

And R3 = (R1.R2)/(R1 + R2) = 1.21 KΩ

i.e R3 =1.2KΩ

b) High Voltage Regulator using IC 723 for Vo = 15V, IL = 100mA

___________________________________________________________________________


68


Fig. (5) Circuit Diagram for High Voltage Regulator using IC 723 for Vo = 15V, IL = 100mA.TABULAR COLUMN: Line Regulation Load Regulation

IL = ----- Const. Vin = ----- Const.SL NO

Vin

In VoltsVo

In VoltsSL NO

RL

in ΩIL

in mAVo

In Volts

% Line Regulation = __________ % Load Regulation = __________

LINE REGULATION LOAD REGULATION

Fig. (6) Fig. (7)

Calculate Sv (Voltage stability Factor) = at constant IL ---------------

RESULT: _________________

___________________________________________________________________________


69

Vin in Volts

VoinVolts

IL in mA

VoinVolts


***************************************************************************R-2R DAC

___________________________________________________________________________


70


Fig. (1) Circuit Diagram of a DAC using R-2R Network

DAC specifications:1. Resolution of DAC:

Resolution is measured as the smallest incremental change in the analog outputVoltage obtained from the DAC. Resolution depends on the number of Digital inputs (no. of bits). Resolution is often expressed as the number of bits of the inputs to the DAC. More the number of bits better is the resolution.

Full Scale Analog O/P VoltageR = -------------------------------------

2N - 1N is the No. of digital inputs.

100% R = ----------- or R = 2N

2N – 12. Linearity:

This term indicates how linearly the analog output from a DAC increases as the Digital input (Binary) are changed in a proper binary number sequence from all ‘0’ inputs to all ‘1’ inputs.

DESIGN: To design 4-Bit R-2R DAC Op-Amp Voltage follower acts as a Buffer stage. Do, D1, D2 and D3 are Digital inputs may be low (0) or High (1). VR (0) = 0 VR (1) = VR = Reference voltage can be selected depending on maximum Analog output voltage required.If the Digital Inputs are obtained from a Digital IC Trainer then fix VR = +5 V The Analog Vo for a 4 bit DAC is given by

If VR = +5 Volts

Then

EXPERIMENT NO.: 15

R – 2R DAC

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AIM: a) To design and test R -2R DAC using Op-Amp. b) To measure Resolution of DAC.


SLNO


1. Power Supply ± 12 V / 2 Amp D.C. 012. Terminal Board 013. Digital IC Trainer Kit 014. Digital Voltmeter (or Digital Multimeter) 0 – 30 V D.C. 015. CRO Analog, 30MHz, Dual Channel 015. Resistor 1 KΩ (1/2 Watt) 156. I.C. µA 741 017. Patch cords, Connecting Wires,etc.

PROCEDURE:

1] Connect the DAC circuit using R – 2R ladder network as shown in Fig. (1) 2] To measure minimum or least output Vomin: Set all digital inputs to logic 0 i.e. Do = D1 = D2 = D3 = 0 then Vo = 0 theoretically and verify it practically. Suppose if the inputs from digital trainer has minimum of 0.2 V which is logic 0 then Vomin = (0.2 / 24) [8 + 4 + 2 + 1] Vomin = 0.125 V Instead of Vomin = 0 V, we have Vomin =0.125 V. 3] To measure Resolution of DAC: Resolution is defined as smallest incremental change or it is 1 LSB. Let D3 = D2 = D1 = 0 and set LSB D0 = 1

Vo = (VR / 24) [0 +0 + 0 + 1] = 5 / 24 = 0.2083 V R = 0.2083 V theoretically Verify it practically measuring the value at Vo using Digital Voltmeter or Digital multimeter. 4] To measure full scale output voltage: Full scale output voltage is obtained by setting all the inputs to logic high. i.e. D3 = D2 = D1 = + 5 V Vomax = (VR / 24) [8 + 4 + 2 + 1] = (5/24)15 = 3.125 V The theoretically calculated value is verified by measuring practically. 5] Vary the digital input D3, D2, D1 and Do from 0000 to 1111 and note down the output of the Op-Amp. Tabulate the reading in the tabular column.

TABULAR COLUMN:

Decimal Digital Theoretical Experimental Vo0 0 0 0 0 01 0 0 0 1 0.20833

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2 0 0 1 0 0.41663 0 0 1 1 0.6254 0 1 0 0 0.8335 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 1

10 1 0 1 011 1 0 1 112 1 1 0 013 1 1 0 114 1 1 1 015 1 1 1 1 3.125

RESULT: ____________________

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***************************************************************FLASH TYPE ADC

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TRUTH TABLE:

ANALOGINPUT

Vi

COMPARATOR OUTPUT

C1 C2 C3

DIGITALOUTPUT

ACTIVE LOWB’ A’

ACTIVE HIGH

OUTPUT B A

0 < Vi < 1V

1V < Vi < 2V

2V < Vi < 3V

3V < Vi < 5V

1 1 1

0 1 1

0 0 1

0 0 0

1 1

1 0

1 0

0 0

0 0

0 1

1 0

1 1

EXPERIMENT NO.: 16

FLASH TYPE ADC

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AIM: To design and test flash type ADC


SLNO


1. Power Supply +5 V / 2 Amp D.C. 012. Terminal Board 013. Digital IC Trainer Kit 014. Voltmeter (or Digital Multimeter) 0 – 10 V D.C. 015. Resistor 1 KΩ 056. Potentiometer 10 KΩ (1/2 Watt) 017. I.C. LM 324 018. I.C. 74LS147 019. Patch cords, Connecting Wires,etc.

PROCEDURE:

1] Connect the circuit as shown in Fig. (1) 2] Set the different values of Vi using Potentiometer. 3] Analog Vi is measured by using D.C. Voltmeter or Digital Multimeter

4] For different values of Vi observe the digital outputs as shown in truth table.

RESULT: _____________________

***************************************************************************

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QUESTION BANK

ANALOG ELECTRONICS LAB

III Semester B.E. (ELECTRONICS & COMMUNICATION ENGINEERING) Sub Code : ECL37 IA :

25 Hrs/Week : 03 Exam Hours : 03

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Total Hrs. : 42 Exam Marks : 50

1] Design a RC coupled single stage BJT amplifier and determine the gain-frequency response, input and output impedances.

2] Design a BJT Darlington Emitter follower and determine the gain, input and output impedances.

3] Design a BJT Voltage series feed back amplifier and determine the gain, frequency response, input and output impedances with and without feed back.

4] Design a LM384 / TBA2020 IC-based Power amplifier and determine the Power gain and efficiency.

5] Design and testing the performance of BJT-RC Phase shift Oscillator for fo = 1 KHz.

6] Design and test the performance of FET Hartley Oscillators for RF range fo = 100 KHz.

7] Design and test the performance of FET Colpitt’s Oscillators for RF range fo = 100 KHz.

8] Design and test the Single ended diode clipping circuits.

9] Design and test the Double ended diode clipping circuits.

10] Design and test the diode peak detection circuit.

11] Design and test of clamping circuits for specific needs: Positive clamping / Negative clamping.

12] Construct and test Op-Amp circuit to obtain the following functions; (i) Inverting amplifier (ii) Non-inverting amplifier (iii) Voltage follower.

13] Construct and test Op-Amp circuit to obtain the summer functions;

14] Construct and test Op-Amp circuit to obtain the following functions; (i) Integrator and (ii) Differentiator for square wave inputs.

15] Design and test using Operational amplifiers for the performance of; (i) ZCD and (ii) Schmitt Trigger for different Hysterisis values.

16] Test the performance of Full wave precision rectifier using Operational Amplifier.

17] Design and test the Voltage regulator using IC 723 to meet the following specifications; a) Vo = 5 Volt, IL = 100mA and b) Vo = 15 Volt, IL = 100mA.

18] Design a 4 Bit DA Converter using R-2R Ladder Network to obtain Resolution of about 0.2V and full scale o/p of 6.25V. Demonstrate the operation of the Circuit and the Analog o/p Voltage for all the input combinations and tabulate the Results.

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19] Design and test of flash type ADC using Operational amplifier.

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A E Lab manual

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