E L S E V I E R Materials Science and Engineering B29 ( 1995 ) 54-57

MATERIALS SCIENCE &

ENGINEERING

B

A complementary III-V heterostructure field effect transistor technology for high temperature integrated circuits

Craig Wilson a, Anthony O'Neill a, Steven Baier b, James Nohava b '~ University of Newcastle upon Tyne, Electrical and Electronic Engineering Department, Merz Court,

Newcastle upon Tyne NE I 7R U, UK I'Honeywell Technology Center, 10701 L yndale A venue South, Bloomington, MN 55420, USA

Abstract

A complementary III-V heterostructure field effect transistor (CHFET) has been developed which employs a high aluminium mole fraction aluminium gallium arsenide (Al..75GaAs) interfacial layer between the gate metallization and the indium gallium arsenide In0.25GaAs channel. This produces a quasi-insulating gate structure which reduces the gate leakage current. Experimental and simulation data have been used to show the potential of the CHFET up to temperatures of 500 °C. Computer modelling has also been used to study the role of the heterostructure component parts, which has revealed the relative importance of each material in the successful operation of high temperature electronic devices and facilitated the prediction of further device improvements.

Keywords: Heterostructures; High temperature; Gallium arsenide

1. Introduction

The interest that currently exists in device technolo- gies that will operate at elevated temperature stems from industrially driven requirements such as in gas, oil and geothermal exploration, harsh environment intelli- gent sensors, jet engine, space and automobile tech- nology (for example Ref. [1 ]). Conventional silicon (Si) integrated circuits (ICs), which dominate comple- mentary device technology, are commonly accepted as failing at around 250°C. Gallium arsenide (GaAs) based technology potentially offers improved high temperature performance by virtue of its wider energy band gap. The potential of high temperature I I I -V technology has already been experimentally demon- strated [2,3]. However, the device structure of a bulk GaAs metal -semiconductor field effect transistor (M ES F ET) leads to premature failure with tempera- ture [4,5] owing to excessive gate leakage in forward and reverse bias.

A I I I -V based complementary heterostructure field effect transistor ( C H F E T ) has been developed with an Al~wsGaAs/In02.~GaAs/GaAs structure, which is suit- able for commercial digital ICs [6]. This device has been shown experimentally to operate at temperatures

up to 500 °C [7J. In this paper we present modelling results for the high temperature n channel CHFET, with the aim of understanding the high temperature operation of the device.

2. Device structure

A schematic of the n and p channel C H F E T is given in Fig. 1. All epitaxial layers are grown undoped using molecular beam epitaxy. Digital ICs based on this device structure operate in an analogous way to Si complementary metal oxide semiconductor ICs. The metal/Alo.75GaAs/Ino.25GaAs structure produces a quasi-insulating gate as there is both a Schottky barrier gate and a substantial heterojunction barrier between the A10.75GaAs (energy band gap Eg~2 .07 eV at 300 K) and the In025GaAs (Eg ~ 1.06 eV at 300 K). An Si delta-doped layer is used to control the threshold voltage of the device (nominally + 0.3 V and - 0.3 V for n and p channels respectively). Fabrication is based on a standard self-aligned GaAs H F E T process. The gate metallization was a refractory metal (WSi). An InGe-based metallization (known for its good high temperature behaviour) was used for the ohmic

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C. Wilson et al. / Materials Science and Engineering B29 (199.5) 54-57 55

~-CMnr~ FET pCMr~4 F E ' r

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cat ng Ga~ S~bs~ (a/

~E--250 A No 7 s G a A ~ b a m e r ~ - ~ l ~ A In0~ s G e ~ , s c t ~ n n e l

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Fig. 1. (a) Schematic diagram of the n and p channel CHFET. The devices have 0.7 Mm channel lengths and an A1075GaAs / In()25GaAs/GaAs heterostructure. Complementary devices are separated by oxygen implants. (b) Simulated conduction band energy from the gate into the device (n channel, Vg = 0.0 V).

contacts. The IC had two levels of gold off-substrate interconnects. Device isolation is provided by the 10~ff~ cm semi-insulating substrate and oxygen isola- tion between adjacent FETs.

3. Device modelling of high temperature characteristics

Device modelling was carried out using two-dimen- sional physically based finite element simulation tool, BlaZE [8], with non-isothermal capability. R o o m tempera ture (25°C) empirically derived data for doping levels and Schottky barr ier height were used for the modelled device. The band offset discontinuity at both heterojunctions was assumed to be in the ratio 60% to 40% for the conduct ion and valence bands respectively. Fig. 2 gives a compar ison of the simulated and experimental subthreshold characteristic of an n channel C H F E T at 25 °C, showing close agreement.

Simulation of the device was then pe r fo rmed at elevated tempera tures up to 500°C (with no further empirical changes). Genera l material parameters (energy band gap, carrier statistics and mobilities, for example) were varied by generally accepted expressions [9]. T h e height of the meta l - semiconduc-

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i ~ l l l l ~ l l l l l l l l ~ i l l i ~ l l l l l

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Gate Voltage (V)

Fig. 2. Comparison of simulated and experimental subthreshold characteristics for the n channel CHFET at room temperature (25 °C) at a drain voltage of 2.0 V.

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1.0 1.5 2.0 2.5 3.0 3.5 4.0 1000FFemperature (l/K)

Fig. 3. Simulated drain subthreshold leakage current as a function of reciprocal temperature (equivalent Celsius tempera- ture is given at the top). Experimental values indicate the close- ness of results. Results are shown at V d = 2.0 V, V~ = - 1.0 V.

tor gate Schottky barr ier was assumed to vary by the same level as the energy band gap of the semiconduc- tor [10], that is, reduced by approximately 3.6 × 10 -4 eV K-1. This resulted in excellent agreement between the simulated and experimental results. Fig. 3 compares the drain subthreshold leakage current as a function of reciprocal t empera ture for both sets of

56 ('. Wilson et al. / Materials S('ience and Engineering B29 (199,5) 54-57

data. This drain subthreshold current comprises of gate leakage current.

Experimental performance of the n channel C H F E T was significantly better than experimental data for a comparable bulk GaAs n channel MESFET. For example peak transconductance was at least 100 mS mm--~ higher for the C H F E T over the entire tempera- ture range to 500°C. The C H F E T also displays perfectly satisfactory 1- V curves at 400 °C. At temper- atures over approximately 200 °C, however, the drain subthreshold leakage current of the C H F E T is of the same order of magnitude as for the MESFET. This is worse than expected for a GaAs-based heterojunction device at these temperatures {11]. The modelled characteristics show that the high drain subthreshold leakage stems from the gate (which is confirmed by Fig. 4, the current flow plot of the device with Ve = - 1.0 V and V,~ = 2.0 V at 500 °C), which illustrates the flow of current from gate to positive drain.

4. Heterostructure material layer operation

4.1. AIGaAs layer

The A1075GaAs top layer is known to reduce the forward gate leakage current by producing a quasi- insulating effect [12]. This enables the C H F E T to maintain a peak extrinsic t ransconductance ge, of 100 mS mm ~ up to forward gate voltages of 0 .7V at 500°C. As noted above, however, one of the main limiting factors of the high temperature C H F E T performance is reverse gate leakage. In order to gain

, 5

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: L ,

I cn{)th (Micror/,:

Fig. 4. C u r r e n t f low (a rb i t r a ry uni ts ) wi th in the n C H F E T in the off s ta te ( V,~ = 2.0 V, V,~ = - 1.0 V ) at 500 °C. T h e f low f r o m ga te to d ra in is c lear ly visible.

agreement of the 25 °C simulations to experiment, the room temperature effective Schottky gate barrier height for electrons was set at 0.54 eV. This is con- siderably lower than the expected experimental value of approximately 1.0 eV and suggests an alternative source of gate leakage not previously identified. The authors are, at present, investigating the cause of this leakage and future enhancement of the device struc- ture. The solution of this problem will lead to an n channel C H F E T which is capable of higher tempera- ture operation typified by Fig. 5. The simulations suggests that an improvement in drain subthreshold leakage current of between 2 and 3 orders of magni- tude is possible at 500 °C. A transition in gradients is now evident as the gate current no longer limits drain subthreshold leakage below approximately 150 °C.

4.2. InGaAs layer

The relatively narrow energy band gap In0.>~GaAs layer provides an area of carrier confinement at both room and elevated temperatures (Fig. 6). This is parti- cularly important as temperature is elevated, because higher energy carriers moving into the buffer layer can reduce the F E T performance in terms of, for example, transconductance. A potential problem with this layer at elevated temperatures results from an increased level of carriers when in a nominally depleted state, as a result of the narrow band gap. Simulations have shown that an increase in the energy band gap of the InGaAs

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1000/Temperature

Fig. 5. Simu|atcd drain subthreshold current as a funct ion o f reciprocal temperature fo r the n -CFIFET with the cal ibrated effect ive S ch o t t k y b a r r i e r he ight of 0 .54 eV and wi th 1.00 eV. Resu l t s a re s h o w n at V d = 2.0 V, V~ = - 1.0 V.

C. Wilson et al. / Materials Science and Engineering B29 (1995) 54-57 57

oo

c ) c_)

cs

tion. T h e device currently per forms well at tempera- tures above 300 °C and with additional improvements , as suggested by modelling, has the potential to provide digital IC functions to 600 °C. Further modelling work is required for the p channel C H F E T and studies of other I I I - V material variants. Further experimental work is required to establish the cause of a lower effective reverse barr ier height than expected and to study the inclusion of a back side A I G a A s buffer.

References

[ c n g t h ( M ~ c r o n s )

Fig. 6. Logarithmic plot of electron concentration within the device at 300 °C in the on state ( V d = 2.0 V, V~ = 2.0 V).

layer by 30% would not reduce the drain subthreshold current at 300 °C, but would result in a reduction in drive current by 17% and a comparab le reduction in transconduction, both as a result of reduced channel definition, i.e. the band gap of the I n G a A s layer is not the limiting high tempera ture factor of the C H F E T .

4.3. G a A s layer

T h e G a A s buffer layer aids the confinement of carriers in the I n G a A s channel by providing a hetero- junction barr ier of approximate ly 0.25 eV on the back side of the I n G a A s channel. To further increase this effect a second A I G a A s layer can be placed between the I n G a A s channel and the G a A s buffer. Modelling has shown that the subthreshold drain leakage current can be reduced by up to half an order of magnitude at elevated tempera tures by insertion of such a layer [13]. This layer has the added benefit of increasing isolation between devices.

5. Conclusion

The high t empera tu re per formance of the n channel C H F E T has been investigated by numerical simula-

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