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714 IEEE TRANSACTIONS ON POWER ELECTRONICS. VOL. I. NO. 4, OCTOBER 1992

A Compact DC-to-DC Power Converter for Distributed Power Processing

David S . Lo, Senior Member, IEEE, Christopher P. Henze, and Joseph H. Mulkern

Abstract-This paper presents a compact (55 W/in3), efficient (86% power train), 1 MHz switch-mode, dc-to-dc power con- verter contained in a 2 in by 2 in by 0.25 in, 1 in3 package. It also describes the interleaved forward topology, steady-state analysis, switch transitions, capacitor substrate, planar printed-wiring-board transformer, packaging, electrical per- formance, power loss analysis, thermal analysis, reliability, and efficiency and power density improvements.

I. INTRODUCTION HIS paper presents the results of an exploratory de- T velopment of a compact, efficient, l MHz switch-

mode, dc-to-dc power converter for on-card applications in distributed power processing systems. It utilizes pulse- width modulation (PWM) at a constant frequency of 1 MHz (2 MHz ripple frequency) and zero-voltage resonant transition (ZVRT) switching.

The interleaved forward topology developed for this power converter is described along with its breadboard experimental results, steady-state analysis, and switch transitions. Also described are the design, fabrication, and characterization of a capacitor substrate; a low-profile, printed-wiring-board transformer; and a gate drive cir- cuit, an analog controller, and a bias power circuit.

The power converter is contained in a l-in3 (2 in by 2 in by 0.25 in high) package. The input voltage is from 50 to 60 Vdc and the output voltage is regulated at 5.2 Vdc. It has achieved an output power density of 55 W/in3. The overall efficiency is 83 % including the power train circuit as well as all the supporting circuits. The power train ef- ficiency alone is 86%. The packaging approach, electrical performance, power loss analysis, thermal analysis, reli- ability prediction, and efficiency and power density im- provement recommendations are described. All parts were derated to military standards.

11. TOPOLOGY The interleaved forward topology shown in Fig. 1 was

developed for this power converter. Despite its flyback appearance, it is called a forward topology because its voltage transfer function is the same as the buck-derived

Manuscript received June 6, 1990; revised February 4, 1992. D. S. Lo and J. H. Mulkern are with the Paramax Systems Corporation,

A Unisys Company, St. Paul, MN 55164-0525. C. P. Henze was with the Unisys Defense Systems, Inc., St. Paul, MN

55164-0525. He is now with the Schott Corporation, Wayzata, MN 55391. IEEE Log Number 9202484.

Fig. 1. Interleaved forward topology.

topology shown Section 111. It has two parallel power stages a and b that are driven with 180" phase shift. When S,, is on, energy is delivered to Cp and Lpa from the input; when SI, and S,, are on, energy is passed on to C, at the output. The case is the same for stage b except for a 180" phase shift. A switching frequency of 1 MHz per side is used that produces a 2-MHz ripple frequency. The max- imum on-time for the power switches S2, and s2, is lim- ited to less than 500 ns so that overlapping conduction occurs for the synchronous rectifier switches S3, and $36.

An interleaved forward topology is inherently more ef- ficient than a conventional topology without interleaving and ZVRT in this low-voltage high-current application. It utilizes constant frequency PWM control and is suitable for ZVRT switching to minimize switching losses [l]. The overlapping of the interleaved rectified output currents re- duces the output rectification loss, the ripple current, and allows the use of a high-voltage low-value, ceramic ca- pacitor at the input side. However, it requires a complex drive circuit with controllable timing sequences for its six FET switches. Furthermore, the high ac ripple currents in the primary circuits required for ZVRT switching in- crease the conduction losses.

In the forward converter, the primary side capacitor is connected in series with the primary winding of the trans- former that limits the switch voltage rating to the input voltage. In addition, the primary side capacitor is com- mon to both the interleaved sides. It is alternately con-

0885-8993/92$03.00 0 1992 IEEE

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LO er al.: A COMPACT DC-TO-DC POWER CONVERTER FOR DISTRIBUTED POWER PROCESSING

10 20 30 40 50 mi m w m ( w e ~

Fig. 2. Efficiency of breadboard interleaved forward converter.

nected to the input source, which allows the capacitor to replenish its stored energy from the input. The output power is delivered by both the interleaved sides via the common capacitor during the transformerhnductor charge and discharge times. It reduces the current magnitude and thus reduces losses. An interleaved forward converter breadboard has been built and investigated at various switching frequencies, input voltages, loads and switch timing sequences.

The effect of switching frequency on the power con- verter operation is complex. A higher frequency will re- duce the size of the capacitor, inductor, and transformer but increase the core loss and switching loss. Every power converter has a unique optimum switching frequency that is a function of the detailed circuit design, component, packaging technology, etc. The optimum switching fre- quency for the experimental breadboard circuit was found to be in the vicinity of 1 MHz. The switching frequency of 1 MHz was then used in all the experiments.

The relative turn-on time of the power and floating and rectifier switches is critical for ZVRT switching, and thus efficiency. In general, the power switch is turned on 100 ns after the floating and rectifier switches are turned off. The floating and rectifier switches are turned on 25 ns after the power switch is turned off.

At one of the optimum operating conditions, a power train efficiency of 89% was obtained from a breadboard implementation as shown in Fig. 2. The input was 55 V and the output was regulated at 5.2 V. The primary in- ductance of the transformer was 4 pH and the switching frequency was 1 MHz. The high efficiency is attributed to the components used, physical layout, and unique topol- ogy developed. The waveforms observed were consistent with the steady-state analysis described in Section 111.

111. STEADY-STATE ANALYSIS As previously described, the interleaved forward to-

pology consists of two identical sections. For conve- nience, one-half of the topology of Fig. 1 is redrawn in Fig. 3 for steady-state analysis. The topology uses three FET switches, primary and secondary side filter capaci- tors, and a two-winding transformer (or energy storage inductor). In this analysis it is assumed that the capacitors

~

715

Fig. 3 . Forward topology.

are large enough so that the voltage is approximately con- stant over a switching interval, the transformer windings are coupled with a coupling coefficient of unity, and the FET switches are ideal. Furthermore, it is recognized that multiple output voltages could be obtained through the addition of windings, switches, and capacitors, however, only the single-output voltage version is considered in this analysis.

Floating switch SI and the synchronous rectifier switch S3 are driven with the same drive signal such that they are either both on or both off as shown in Fig. 4(a). Power switch S2 is driven such that when switches SI and S3 are off, the power switch S, is on. Because ideal switches are assumed, the switching intervals are instantaneous and occur simultaneously. In practice, break-before-make switching with a short but finite switching interval is adopted in the implementation of ZVRT switching [l] .

The topology has two states as shown in Fig. 5. In Fig. 5(a) the power switch S2 is on, allowing the current in the primary winding ZLp and the charge in the primary side filter capacitor C, to increase while the output current Z,,, is totally supported by the output filter capacitor Cs. In Fig. 5(b) the floating and rectifier switches SI and S3 are on allowing energy to transfer from the primary side of the circuit to the secondary side to support the load.

The voltage across the primary inductor winding VLp must have an average of zero over one switching interval if the circuit is operating in steady state:

(Vi,, - nVo,JDT - nVo,,(l - D)T = 0

Vino = ~lV,,,t

where T is the switching period, D is the fractional duty ratio of the power switch S2, and n is the normalized turn ratio of primary to secondary transformer windings. The voltage transfer function of (1) is the familiar result for a buck-derived topology. Hence, the present topology is considered as a forward topology.

The average current in the output capacitor C, must be zero in steady state. When the power switch S2 is on, the output capacitor must supply the total load current I,,,. When the floating and synchronous switches SI and S3 are on, the current must reverse in the output capacitor C, to

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716 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. I, NO. 4, OCTOBER 1992

m * m Because the average capacitor current must be zero, the - - s, SlLSj secondary current Is may be found to be

( r ) s w k c h c o n t m l ~ -Dlout + ( 1 - D)(ls - lout) = 0

(2) lout Is = - 1 - D

and during floating and synchronous switch conduction ' d o -bin +J--+J--t lout

Isc = - - lout 1 - D

Fig. 4. Forward topology waveforms

using (1)

The output current lout is shown in Fig. 4(d) and the sec- ondary current Is is shown in Fig. 4(e).

It is assumed that the current in the primary winding of the transformer lLp consists of three components. One component is magnetizing current lLp, mag that results from application of voltage across the primary winding by the power switches and is independent of the output load cur- rent. The second component is the secondary current, which is reflected to the primary side during SI and S3 conduction ILp, The third component is the input cur- rent contribution during S2 conduction lLp,2.

The magnetizing current is determined by the voltage applied to the transformer primary winding, the winding inductance, the switch duty ratio and the switching pe- riod. During power switch S2 conduction, the peak-to- peak swing in magnetizing current during S, conduction is

vi" - nvout DT. (5 ) - LP

ILP,mag - T!)fTk VL P

The be found peak-to-peak using the current same method during SI and S3 conduction can

ILP,mag = !?& (1 - D)T. (6)

If the circuit is operating in steady-state conditions, ( 5 ) and (6) must be equal. This can be verified by setting ( 5 )

LP (b)

Fig. 5. Forward topology states. (a) Switch S, on, switches SI and S, o f f . (b) Switches SI and S, on, switch Sz off.

the output current lout:

lsc = -Zout (for S2 conduction). A- &wt

ILP,1-3 - - n n ( l - 0)' (7)

For floating and synchronous switch conduction, the out- put capacitor current lsc is equal to the difference between the secondary current Is and the output current lout:

(for SI and S3 conduction).

The load current contribution to the primary current ing S2 conduction Z L p , , is found by considering the input current that must flow during S2 conduction to support the output current. Using ( 1 ) and the conservation of energy, lsc = Is - lout

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LO et al.: A COMPACT DC-TO-DC POWER CONVERTER FOR DISTRIBUTED POWER PROCESSING I11

the input and output currents are related that

rearranging (8)

The average of load current contribution to the primary current during S2 conduction ILp, over one switching cycle must be equal to the input current Zin

(9)

The primary winding magnetizing current I , , mag of ( 5 ) or (6) has a triangular wave shape as shown in Fig. 4(f). The load current contribution of (7) during SI and S3 conduc- tion is shown in Fig. 4(g) and the load current contribu- tion of (10) during S2 conduction is shown in Fig. 4(h). Note that ILp, of (10) will remain constant even after S2 is off due to the large inductance in the primary winding. The resulting primary current ILp waveform is shown in Fig. 4(i) by combining Fig. 4(f), (g), and (h).

If there is no output current, the magnetizing current is the only current in the primary winding and must have an average value of zero. Therefore, in the unloaded condi- tion, the primary current waveform will have positive and negative peaks of equal amplitude. Furthermore, it should be noted that to obtain ZVRT switching, the magnetizing current must have a peak-to-peak amplitude greater than twice the load current contributions to the primary induc- tor current ILp.

The forward topology just described is different from the conventional isolated buck-derived topology because only a single magnetic element is used. This single mag- netic element acts as both the inductor and the trans- former. Furthermore, ZVRT switching on the primary side is easily implemented in this topology because the transformer feeds current into the junction point of the two primary side switches. If a very high magnetic cou- pling coefficient is provided, ZVRT switching can also be obtained on the rectifier switch S3.

When this forward topology as shown in Fig. 3 is ex- tended to an interleaved forward topology as shown in Fig. 1, two forward-power processing cells are connected in parallel and operated with a 180” phase shift. The input capacitor and primary side filter capacitor are common to both circuits. If the power switch duty ratio is restricted to values of 50% or less, the output side filter capacitor may be eliminated because the primary side filter capac- itor is always connected to the output through one or both of the rectifier circuits. In general, the “interleaving” scheme may be extended to any number of forward type power processing circuits.

A steady-state analysis of the interleaved version of the forward topology is not presented in this paper, however, a brief description of the operation, including some circuit waveforms, is shown in [2]. In general, the interleaved forward topology may be analyzed in the same fashion; and for a duty ratio of exactly 50% the waveforms for one section of the interleaved forward topology are similar to those of Fig. 4. For duty ratios of less than 50%, the pri- mary current waveforms during the off-time (1-D) por- tions of the switching cycle are modified by the current sharing action of the paralleled power stages. In practice, there is transformer leakage inductance, winding, and switch resistance, which, along with a finite capacitance, will lead to a ramping load current waveform. The wave- form in an actual interleaved circuit is difficult to deter- mine, however, in a well-designed circuit with small leakage inductance and resistance, the ramping current does not present a problem.

IV. SWITCH TRANSITIONS To achieve ZVRT switching, the forward interleaved

circuit requires a small but finite blanking interval be- tween switching. During this interval, all three switches (power, floating, and rectifier) on the same side of the interleaved circuit are in the off state. The FET’s will not experience a voltage higher than the input voltage Vi,, however, the switches will be subjected to a combined current of both the ripple current in the primary winding and the dc bias current corresponding to the load.

During the blanking time after the power switches are turned off, the positive current in the primary winding will charge the capacitance of the switching FET’s to create zero voltage across the floating and rectifier switches, to allow zero voltage switching. Similarly, when the floating and rectifier switches are turned off, the power switches are not turned on until after a short blanking time. During the blanking time, the negative current in the primary winding will discharge the capacitance of the FET’s to create zero voltage across the power switches for zero voltage switching. To ensure the presence of the negative current in the primary circuit, the magnetizing current in primary circuit should be designed to have a peak-to-peak magnitude greater than twice the full load dc primary cur- rent. The magnetizing current has a triangular waveform as shown in Fig. 4(f), symmetrical with respect to zero current at no load. This waveform is independent of the load but will shift upward to the positive region when the load is increased. When the load current exceeds the limit just specified, the triangular waveform will move above the zero current line. Hence, there will be no negative current available for discharging the output capacitor across the power switch.

It should be noted that the floating and rectifier switches are connected in parallel through the transformer. If the power transformer is tightly coupled and if the gates are driven simultaneously, ZVRT switching occurs for the synchronous rectifier as well. Since the drain to source

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/ IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7, NO. 4, OCTOBER 1992

voltage excursion for the synchronous rectifier is twice the output voltage, it would appear that ZVRT switching in the synchronous rectifier contributes to only a slight reduction in losses. However, ZVRT switching in the synchronous rectifier provides a slow and controlled cur- rent turn-off preventing reverse recovery losses in the body diode, which is significant in reducing power losses.

Leakage inductance on the primary side will not affect the ZVRT switching but will reduce the effectiveness of the filtering function of the capacitor Cp. This is because the leakage inductance is connected in series with C p . Leakage inductance on the secondary side will also not affect the ZVRT switching but becomes part of the output filter.

Effectiveness of ZVRT switching will be diminished at increased output current resulting in a slightly lower ef- ficiency. As load current increases, the current in the pri- mary windings takes on a positive dc bias. The magnitude of the negative peak current, which occurs as the floating switch is turned off, is reduced. This causes the resonant transition to “slow down” as shown in the falling edge of the power switch drain waveforms of Fig. 6. If the blanking interval is not long enough, the power switch will turn on with a nonzero voltage and a switching loss will occur. It should be kept in mind that these switching losses are primarily the result of dissipatively discharging the switch (and other node) capacitances. If the voltage is reduced to half of its initial value, three-fourths of the capacitor energy has been losslessly removed. Therefore, to obtain a broad efficiency curve, it may be desirable to operate with some switching losses at high load.

Switching losses may also occur on the “fast edge” of the waveforms of Fig. 6 as the load power is increased. These losses will occur if the gate turn-off transition on the power switch is not sufficiently fast. During the start-up transient, energy stored in the primary winding will gradually build up the voltage across C, to its steady- state value from both sides of the circuit. Because the zero-voltage switching conditions are not yet established, the switches will experience losses. However, the dura- tion is short, the loss will be small.

There is also a possibility of saturating the power trans- formers during initial application of input power. Satu- ration may occur if the rise time of the input voltage is shorter than the period of resonant frequency of primary inductance Lp and the primary side filter capacitance C,, and if the duty ratio D is relatively large. This is because the primary current ZLp increases rapidly during the on-time of the power switch S, but decreases slowly dur- ing the on-time of the floating switch SI when the voltage across the primary side filter capacitor C, is nearly zero. In addition, ZVRT switching will be lost during the tran- sition from the SI turn-off to the S, turn-on if the primary current ZLp does not reach an appropriate negative value at the end of the on-time of SI. Saturation can be avoided by providing a soft-start with a ramp time much greater than the resonant period of Lp and Cp.

Fig. 6. Experimental power switch drain waveforms. The turn-off transi- tion is shortened with increasing load current while the turn-on transition is lengthened.

V. SUPPORTING CIRCUITS A. Gate Drive

The gate drive circuit for one side of the interleaved forward converter is shown in Fig. 7. The TSC430 drivers are used because they provide gate transitions that are fast enough to allow ZVRT switching at 1 MHz. Gate rise and fall times of 5-10 ns have been obtained using the TSC430 to drive IRFC120 and IRFC130 FET dies. Schottky diodes are used to prevent reverse bias substrate currents from causing a catastrophic latch-up in the TSC430s.

The power switch is driven directly from the TSC430 with a waveform that varies from approximately 0 to Vbias. Both the floating switch and the synchronous rectifier are driven with a two-to-one step-down transformer. The transformer is wound on a small ferrite toroid core. A two-to-one step-down turns ratio is used to maintain the gate transition times and because the power lost in charg- ing and discharging the gate capacitor is reduced by a fac-

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LO et al.: A COMPACT DC-TO-DC POWER CONVERTER FOR DISTRIBUTED POWER PROCESSING

CO

Fig. 7 . Gate drive circuitry for one-half of the interleaved forward con- verter.

+5V FEEDBACK

_.. 7 Fig. 8. Closed-loop PWM control circuitry that also generates the appro-

priate blanking intervals for ZVRT switching.

tor of 4. The floating switch drive waveform is dc restored and reaches a positive value of approximately 0.5Vbias. Because the on-state gate voltage is a factor of two lower than that for the power switch, the floating switch has a larger conduction loss resulting from an increased on-resistance.

An increased conduction loss could not be tolerated in the synchronous rectifiers. For reducing these losses, the gate drive waveform is given a dc offset. The bias level is chosen so that off-state gate voltage is greater than zero and approximately 1 .O-1.5 V less than the threshold volt- age of the synchronous rectifier FETs. A major source of power losses in the gate drive circuit is the internal losses of TSC430s operating at 1 MHz. A single TSC430 oper-

119

ating at a supply voltage of 11.2 Vdc with a 1-MHz input signal and an open circuit output dissipates 130 mW.

B. Control Circuit The control circuit is shown in Fig. 8. A UC1825 PWM

controller is used to generate the basic feedback-con- trolled switch drive waveforms. A closed-loop band width of 80 kHz was obtained using the internal UC1825 error amplifier and simple single-pole compensation and volt- age-mode control. The primary goal in developing a closed-loop controller for this application was to provide the blanking intervals needed for ZVRT switching with a minimum component area and a minimum power loss

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7. NO. 4, OCTOBER 1992 720

V bias +11 VDC

TI r

Fig. 9. Internal bias power circuitry for powering the control and gate drive circuits.

overhead. This was done so that the assembled experi- mental dc-dc converter would be a complete circuit, re- quiring only an input power source to produce regulated output power, to accurately demonstrate output power density and efficiency capabilities.

Blanking intervals are added to the control waveforms using a four gates of a hex Schmitt trigger inverter (54LS14) and diode coupled R-C delay networks. The power switch control signal, which is a “narrowed” ver- sion of the UC1825 signal, is generated by delaying the rising edge of the UC1825 signal. The falling edge of the UCl825 signal is used without a delay to define the power switch turn-off edge. The floating switch and synchronous rectifier control signal is generated using the delayed fall- ing edge of the UC1825 signal, and the undelayed rising edge of the UC 1825 signal.

These blanking intervals are independently adjustable. For the experimental work, a blanking interval (as mea- sured at the FET gates) of 30 ns was used between power switch turn-off and floating switch turn-on, and a blanking interval of 120 ns between floating switch turn-off and power switch turn-on. The interleaved forward converter is relatively insensitive to a mismatch in blanking inter- vals because the two sides of the converter are combined using the inductance of the primary windings.

C. Bias Power Circuit Bias power is provided by two-turn windings in each

power transformer as shown in Fig. 9. A bootstrap tran-

sistor off the input voltage provides start-up power until the converter reaches steady-state operation. At that time, the bootstrap transistor is back-biased and does not dis- sipate any power.

VI. CAPACITOR AND TRANSFORMER For compact packaging, a planar capacitor array sub-

strate with a dimension of 0.8 in by 1.8 in by 0.07 in was designed and fabricated using the stable X7R ceramic ma- terial in cooperation with Sprague Multilythic Division [3]. The capacitor array has six capacitors with low equiv- alent series resistances (ESR), low equivalent series in- ductances (ESL), a 600-Vdc breakdown voltage at room temperature, and a 110-pF /in3 density. Multiple capaci- tors are formed in the substrate using the metalization pat- terns as the multilayer device is fabricated. A material with a high dielectric constant is used between metal lay- ers to produce a large capacitance per unit volume. The embedded capacitors are electrically connected to the sur- face of the substrate using metalized vias. Circuit com- ponents were mounted on the capacitor substrate using standard thick film hybrid techniques.

A planar transformer core with dimensions of 1.25 in by 0.5 in by 0.18 in has been developed [2]. The rectan- gular configuration was chosen to accommodate the pack- age and ease of fabrication. The dimensions were de- signed for an acceptable, uniform magnetic flux density and mechanical strength. High-frequency low-loss MN8CX ferrite was used. A multilayer printed-wiring- board having three windings for primary, secondary, and bias power was used for transformer windings. These windings fill the core window efficiently and exhibit tight and consistent magnetic coupling. Because the conductors are flat, the skin effect is minimized. The measured trans- former characteristics agree with the designed values as shown in Table I.

VII. PACKAGING An experimental converter has been contained in a 2-in

by 2-in by 0.25 in package as shown in Fig. 10. The sup- porting circuits such as the gate drive circuit, control cir- cuit, and bias power circuit were designed for efficiency and to be small for packaging similar to the capacitor sub- strate and planar transformer. The layout was based on the available space and heat dissipation. Special attention was made to choose the wire size and route to minimize the interconnect resistance and inductance. An infrared monitoring device was used to identify the hot spots.

The converter layout is symmetrical with each half of the interleaved power circuit located on either side of the center line. Two planar power transformers are mounted along the outer edges of the package. Two smaller sub- strates, mounted in the lower comers of the package, con- tain an additional output filter inductor as well as a ca- pacitor and a rectifier for bias power. Because there was available space, additional inductors were used to reduce

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LO er al.: A COMPACT DC-TO-DC POWER CONVERTER FOR DISTRIBUTED POWER PROCESSING 12 1

TABLE I PLANAR TRANSFORMER

TURNS RATIO 4 : 1 : 2 FOR PRIMARY, SECONDARY. AND BIAS WINDINGS WITH A 14-Mr~ AIR GAP

Measured Calculated

Magnetizing inductance (with other windings open)

L primary = 4.08 p H L secondary = 0.26 pH L bias = 1.09 pH

Leakage inductance (with other windings shorted)

L primary = 0.09 pH L secondary = 0.01 pH L bias = 0.1 pH

Resistance including leads R primary = 38 mQ (at 1 A) R secondary = 3 mQ (at 1 A) R bias = 45 mQ (at 0.5 A)

C primary to secondary = 433 pF C primary to bias = 42 pF C secondary to bias = 35 pF

Capacitance at 100 kHz

4.13 pH 4.13/4* = 0.26 p H 4.13/22 = 1.03 p H

0.074 pH 0.0046 pH

4 x 8 mQ = 32 mQ 0.25 x 8 mQ = 2 Mfl 2 x 27m0 = 54mQ

460 pF

Fig. 10. Experimental 55-W dc-dc converter contained in a 2-in by 2-in by 0.25 in package.

output EMI. Note that the output inductors are not a part of the power supply topology.

A capacitor array substrate mounted in the center of the package contains the power train circuit, the gate drive circuit, and the control circuit. The multilayer, ceramic, capacitor array substrate contains six embedded capaci- tors. Three of the substrate capacitors with values of 2.0, 5.0, and 4.0 pF are used for input, primary, and output filtering, respectively. The three smaller substrate capac- itors of 0.2 pF each are added to the output filter section of this circuit. The embedded capacitors are electrically

connected to the edges of the substrate using metalized vias. A multiple layer metalization and dielectric pattern on the top of the capacitor substrate was made for mount- ing various components. A large ground plane layer is used to accommodate the high return currents and to pro- vide shielding.

The high voltage (100 V) primary side FET’s for float- ing and power switches are mounted near the input power terminals on the edges of the capacitor substrate. The IRFC120 dice that have a 300-ma on-resistance and a 100-Vdc breakdown voltage are used for all four primary

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122 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7. NO. 4, OCTOBER 1992

side switches. A conductive epoxy mounting technique is used for the drain connection and conventional wire bond techniques are used for the gate and source connections, with multiple 5-mil wire bonds used for the source.

The synchronous rectifier FET’s are mounted near the center of the package along the edge of the capacitor array substrate. The rectifiers used are experimental FET’s de- veloped by General Electric [4] for synchronous rectifier applications. The devices provided by GE have a 12-15 mil on-resistance and a breakdown voltage of 25-30 Vdc. Two rectifier FET’s are connected in parallel on each side. Each device, however, has its own set of windings in the power transformer. This was done to ensure current shar- ing and to provide multiple high-current paths for the sec- ondary output connections.

The rectifier FET devices are mounted to the substrate using a unique “solder bump” technique for the gate and source connections. The drain lead is directly connected to the power transformer winding using a copper conduc- tor soldered at both ends. This mounting technique pro- vides substantially reduced interconnect resistance and in- ductance than previous techniques using a conventional wire bond approach. The reduction of parasitic resistance and inductance in the output circuit is critical to maintain- ing efficiency in a high-current power converter operating at 1 MHz. The gate drive circuit is mounted on the inte- rior surface of the capacitor substrate. The two small to- roids near the center of the power train circuit are used for isolation in driving the floating switch and the syn- chronous rectifier FET’s.

The control circuit was assembled on a separate sub- strate for ease of testing and alteration during initial de- velopment of the prototype. For example, the blanking intervals were altered several times to obtain a maximum efficiency. The control substrate is mounted on the sur- face of the capacitor substrate near the output terminals. The control circuit artwork could be applied directly to the top surface of the capacitor substrate rather than using a separate substrate.

VIII. DISCUSSION The maximum overall efficiency of the power con-

verter, as packaged, is 83% at an output of 44 W (Fig. 11). Power train efficiency alone is 86% (Fig. 12), which is 3% lower than the 89% obtained from the breadboard. This discrepancy is attributed primarily to the relatively high on-resistance of the IRFC120s, compared to that of the IRFC130s used on the breadboard, and the extra mounting lead resistance. The IRFC120s were used in the package because of the limited available space. A broad efficiency curve has been obtained; at an output power of 25 W, the efficiency is 80% and 86%, respectively, for the overall and power train circuit. An output power as high as 60 W has been obtained.

An output voltage ripple of approximately 2 % is shown in Fig. 13. This waveform was obtained by connecting

Fi % t; 8o

gl 75

6 % 70

f 65

15 6o 0 5 10 15 20 25 30 35 40 45 50 55 60

OUTPUT POWER ( W A m )

Fig. 1 1. Overall efficiency

90

85

80

WWER TRAIN 75

EFFICIENCY IN % 70

65

OUTPUT POWER (WAl-rS)

Fig. 12. Power train efficiency.

Fig, 13. Output ripple and noise voltage measured at the load. Gate drive waveform included for reference.

the load to the converter through a short length of twisted pair wire and placing a 1-pF capacitor in parallel with the load. This was done to simulate the effects of mounting the converter on an electronic module with capacitive ground and voltage planes and is believed to be represen- tative of the actual differential mode output noise. The photo was taken without a cover on the converter pack- age.

Circuit losses were examined at an output current of 8 A, for an output power of 41.6 W. The input power was measured at 50.1 W, for an overall efficiency of 83 % . A loss of 8.5 W occurs in the circuit. Note that these losses include the power train losses as well as all the supporting

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LO er al.: A COMPACT DC-TO-DC POWER CONVERTER FOR DISTRIBUTED POWER PROCESSING

circuit supply power and the FET drive power. The re- sults of an analysis of circuit losses with present and pro- jected data are shown in Table I1 [2].

The projected data corresponding to an overall effi- ciency of 90% are expected by making the following changes: An analog ASIC [5] controller specifically for 1 MHz, ZVRT switching would reduce the controller power from 0.8 to 0.3 W. A specifically designed gate driver (without the capability of driving very large FET’s as the TSC430s) would reduce the gate drive power from 1 .O to 0.6 W. The losses in the bias power circuit will also be reduced from 0.2 to 0.1 W if the bias current is reduced.

When similar sized FET’s with low on-resistance such as the GE experimental devices [4] are used in the pri- mary and secondary sides, the converter is expected to reduce the primary side switch losses from 1.6 to 0.9 W and secondary side rectifier losses from 0.8 to 0 .3 W. The power transformers could use 3-oz copper PWB for the windings instead of the present 2-oz winding to drop the winding losses from 0.6 to 0.4 W for each transformer. If a better core material such as TDK H7F were used, it would reduce the core losses from 0.5 to 0.3 W for each transformer. The total losses for two transformers could be reduced from 2.2 to 1.4 W. Use of better core material would similarly reduce the output inductor losses from 0.7 to 0.4 W. Interconnection losses could be reduced from 0.8 to 0.5 W by using a thicker ground plane on the capacitor substrate, as well as by using large connecting wires and a package specifically designed for power ap- plications.

The present converter with the recommended improve- ments could be contained in a package of 1.75 in by 1.75 in by 0.225 in [6]. If the present power level of 55 W is maintained, the output power density would be increased from 55 to 80 W/in3. A three-dimensional thermal anal- ysis was performed and an acceptable maximum junction- to-package base temperature rise of 13.84”C was ob- tained. When the package is attached to a cooling fixture and operated at 50 W output, the power converter hottest- component-temperature is stabilized at 50°C. There is no measurable difference in efficiency at 50°C and room temperature.

Reliability predictions have been performed for the packaged power converter using the hybrid reliability model from MIL-HDBK-2 17E. The predictions were made at various ambient rail temperatures from 30 to 90°C in the Airborne, Uninhabited, Attack (Aua) and Airborne, Uninhabited, and Fighter (Auf) environments shown in Fig. 14. At an ambient temperature below 60°C for the Aua environment and 50°C for the Auf environment, the mean time between failure (MTBF) is better than 200,000 h. The MTBF of the packaged power converter could be increased by using the established reliability (ER) ce- ramic capacitors (CKR versus the present CK) and by in- tegrating the control substrate into a monolithic circuit that could be directly attached to the capacitor substrate.

Further investigation into the thermal expansion char-

~

123

TABLE I1 POWER Loss SUMMARY

Measured Present Projected

(W) (W)

Supporting circuits Control circuit FET gate drive Bias rectifier

Subtotal

Power train circuits Primaly-side FET’s Secondary-side FET’s Power transformers Output inductors Interconnect losses

Subtotal

Unidentified losses Total losses Power train efficiency Overall efficiency

0.8 1 .o 0.2 2.0 -

1.6 0.8 2.2 0.7

6.1

0.4 8.5

86 % 83 %

0.3 0.6 0.1 1 .o

0.9 0.3 1.4 0.4 0.5 3.5 0.4 4.9

92 % 90 %

-

-

w ~ ~ o o ~ m m a o r n Rail T s m m (C)

hmolnmulhh.bLd~umhblrd -*e@ w w

Fig. 14. Power converter mean time between failure (MTBF)

acteristics of the components used in the hybrid due to the large substrate size may be needed to ensure a highly re- liable operation over wide temperature ranges and the ex- pected temperature fluctuations in various applications. The addition of current-limiting and overvoltage protec- tion capabilities would enhance the functional reliability of the overall design by reducing the chance for cata- strophic modes of failure.

Another compact power converter contained in one cu- bic inch was fabricated to study the trade-offs between the efficiency and the output power. Since only a limited number of GE rectifier switches with the low on-resistance (12-15 mQ) are available, FMP 40N05 FET’s with an on-resistance of 66 mQ were used. However, eight FMP 40N05s instead of four GE dice were used to ensure rea- sonable low-output circuit resistance. The extra space re- quired was compensated by placing the control circuit board outside the package.

When the primary inductance is decreased from 4 to 3 pH, an output power of 80 W has been obtained. The decrease in primary inductance increases the primary magnetizing current. This allows a greater output current to be produced before ZVRT switching is lost. However,

I

724 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7, NO. 4, OCTOBER 1992

W j , ! , ! , ! , ! , ! , ! , ! $ J 0 10 20 30 40 50 60 70 80

Output Power (Watts)

Fig. 15. Power train efficiency of dc-dc converter contained in another package with 3 pH primary inductance.

the losses in the primary circuit are increased. The power train efficiency versus output power is shown in Fig. 15.

IX. CONCLUSIONS An experimental 55-W dc-dc converter was developed

with a power density of 55 W/in3 and an overall effi- ciency of 83 % . The power train efficiency alone was 86%. It has been projected, based on experimental data, that the overall efficiency can be increased to 90%. The present converter with the recommended improvements can be placed in a smaller package to increase the output power density from 55 to 80 W/in3.

REFERENCES

David S . Lo (M’68-SM’72) received the Ph.D. degree in electrical engineering from the Univer- sity of Minnesota, Minneapolis-St. Paul, in 1962.

From 1962 to 1964 he was with the Honeywell Research Center, Minneapolis, MN. Since 1964 he has been with the Paramax Systems Corpora- tion, A Unisys Company, St. Paul, MN. He has been working on various magnetic, optical, and semiconductor materials and devices, and most recently on switch-mode dc to dc power convert- ers. He is also an adjunct professor at the Univer-

sity of Minnesota.

Christopher P. H e m e received the B.S.. M.S. and Ph.D. degrees in electrical engineering from the University of Minnesota, Minneapolis-St. Paul, in 1981, 1984, and 1986.

In 1981 he joined Unisys Corp. as a research and development engineer. Mr. Henze’s research activities included the development of low- and medium-power dc-dc power converters using zero- voltage resonant transition switching, high-den- sity hybrid packaging, planar magnetics and quantized duty ratio digital control, as well as the

development of high-power factor ac-dc power conditioners. In 1990 Dr. Henze joined the Schott Corp. as a staff electrical engineer and is devel- oping high-current and high-density switch-mode power converters for su- percomputer applications. Dr. Henze has nine patents with several others pending in the field of power electronics.

C. P. Henze, H. C. Martin, and D. W. Parsley, “Zero-voltage switch- ing in high frequency power converters using pulse width modula- tion,” in Proc. IEEE Applied Power Electronics Conf. (APEC) Feb.

C. P. Henze, D. S. Lo, and J . H. Mulkern, “Interleaved forward con- verter using zero-voltage resonant transition switching for distributed power processing,” companion publication of the 1989 Proc. Virginia Power Electronics Center (VPEC) Power Electronics Seminar, third paper, Sept. 1989, pp. 1-18. D. S. Lo and C. P. Henze, “Development of a dc-to-dc power con- verter for distnbuted power processing,” in Proc. IEEE Applied Power Electronics Con$ (APEC), March 1989, pp. 413-422. C. S. Korman, “Advanced low voltage power MOS FET’s for efficient synchronous rectification,” companion publication of the Proc. 1989 Virginia Power Electronics Center (VPEC) Power Electronics Semi- nar, first paper, Sept. 1989, pp. 1-43. M. K. Nalbant and W. R. Davis, “FB3480 new high speed current mode control IC master chip,” in Proc. IEEE Applied Power Elec- tronics Con$ (APEC), March 1989, pp. 151-158. C. P. Henze, D S. Lo, J. H. Mulkern, and L. P. Spar, “VHSIC advanced power supply,” final report (WRDC-TR-89-5050), Jan. 1990 Request for report should be addressed to WRDC \ ELEL, WPAFB OH 45433-6543.

1988, pp. 33-40.

Joseph H. Mulkern received the M.S. degree from the University of Minnesota, Minneapolis- St. Paul, in 1988.

From 1980 to 1984 he worked on helicopter avionics for Speny Flight Systems in both Phoe- nix and Albuquerque, NM. Following this he de- signed air traffic control equipment in Minneapo- lis-St. Paul. He has been employed by Paramax Systems Corp., A Unisys Company, since 1988, working on various high-density switch mode power supplies for airborne equipment, including

a very high speed integrated circuit (VHSIC) program spopsored by the U S. Air Force. He has published four papers and has two patents awarded with three others pending.