Yung-Shih Hsiung and Michael S-C Lu

Department of Electrical engineering and Institute of Nano engineering & Micro System NTHU

Reporter-Vivek Hegde

Course Lectured By- Dr.Cheng-Hsien Liu

A CMOS CAPACITIVE PRESSURE SENSOR CHIP FOR FINGER PRINT DETECTION

OutlineWhy CMOS Capacitive pressure SensorConceptDevice FabricationArchitectureExperimentConclusion

Why CMOS capacit ive pressure sensor?

Biometric uses whorl ,loop and arc patterns of finger print Ridge.

In optical-Photographed image is stored for subsequent identification

Piezoresitive uses wheat stone bridge and sensors are more sensitive to temperature

Concept

Detect Different pressure induced by ridges and valleys of finger printBecause of difference in the contact area on the surface ,capacitance also varies.

Device fabrication

Architecture

Circular Membrane radios is 20 µm and four support beams on the sides are 8 m μlong and2 m wide. The total size of a μsensing pixel by inclusion of the surrounding anchor area is 65×65 m2μ

Architecture

Constant Current Source is used to Charge Sensing Capacitor

Capacitor potential is Periodically reset by transistor Switch.8x32 Signals are Sequentially measured through shared

buffer via Decoder Control.O/P Signal is processed by External 14-Bit A/D ConverterCapacitance Change with respect to the uniform pressure

applied to the membrane

ArchitectureArchitecture of Sensor array and the in-pixel capacitive sensing circuit

Schematics of Current Source

Constant Current Source

Experiment

Simulated and measured force-displacement curves.

Measured output waveforms from different sensing membranes before pressure was applied

Capacitance change vs applied pressure

Measured value and Simulated values are close to each other

Measured capacitance changes of the array by: (a) applying a pressure on the right side of the chip;(b) pressing part of the finger tip on the chip.

Shows successful detection of ridges and valleys

ConclusionCapacitive Pressure Sensor array is presented for finger print

detectionSensor development take advantage of multiple metal layer

and fast electronics provided by the sub micro meter CMOS process

Post CMOS fabrication can be conducted at the chip levelIs almost insensitive to temperature variations

Question ?