A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to ... · A 74.9 dB SNDR 1 MHz Bandwidth 0.9...

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW

Delta-Sigma Time-to-Digital Converter

Using Charge Pump and SAR ADC

Anugerah Firdauzi, Zule Xu,

Masaya Miyahara, and Akira Matsuzawa

Tokyo Institute of Technology, Japan

2

IEEE ISCAS 2016

Outline

• Introduction

• Circuit design

– Charge-pump

– Time-domain feedback

– SAR ADC as quantizer

• Performance summary

• Conclusion

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

3

IEEE ISCAS 2016

Time to Digital Converter

• Measuring time difference between electrical events


Em

itte

r

Ab

so

rbe

r

+

Particle detector in

High Energy PhysicsPositron Emission Tomography

Laser

Detector

Object

Laser range finder

Phase

Detector

Digital

Filter

Counter

Fref Fout

DCO

All Digital PLL

T2T1

T1

T2

γ

TDC

γ-detector

TDC

TDCTDC

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IEEE ISCAS 2016

TDC Prior Arts

• Flash / delay-line

Simple

Technology-limited resolution

• Pipeline

High resolution

Require a linear time amplifier

Inter-stage mismatch


[R. Staszewski, RFIC ‘04] [M. Lee, VLSIC ‘07]

Delay line

TADelay line

CK1

CK2

LogicDout

Coarse Fine

td td

Thermal to binary encoder

CK1

CK2

Dout

td

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IEEE ISCAS 2016

ΔΣ TDC Prior Arts

• Gated Ring Oscillator

Breaking the technology-

limited resolution

Dead-zone issue

• Switched Ring Oscillator

No dead-zone issue

Always running VCO → high

power


[M.Z. Straayer, JSSC ‘09] [A. Elshazly, JSSC ‘14]

Differentiator

Out

Clr

Tin

GROSRO

Differentiator

Out

Clr

VH VL

Tin

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IEEE ISCAS 2016

Voltage-domain TDC

• Time-to-voltage followed by analog-to-digital conversion

More relaxed technology-constrained resolution

High resolution ADC is required


PFD

UP

DN

CK1

CK2 C

Dout

ADC

CLR

• Typical implementationo Charge-pump + SAR ADC

[Z. Xu, CICC ‘13]

o Charge-pump + ΔΣ ADC

[M.B. Dayanik, ESSCIRC ‘15]

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IEEE ISCAS 2016

Mixed-domain ΔΣ TDC

• Gm-cell as integrator + time-domain feedback

Simplified ADC design

Power-starving integrator

Only for positive input


[M. Gande, VLSIC ‘12]

Tin

Tdtc C

Σ Gm

DoutCounter

ADC

DTC

Фfast

Tdtc

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IEEE ISCAS 2016

Proposed Mixed-domain ΔΣ TDC

• Integrator implementation by charge

preservation

Compact design

Low power

Differential input


PFD

UP

DN

CK1

CK2 C

DoutADC

DTC

Time

sub

Δ TVC and Σ

Low-

resolution

ADC

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IEEE ISCAS 2016

Charge-pump as Integrator

• Bottom-plate sampling

– Reduces charge injection

– Prevents charge-pump’s current mismatch


CK1

CK2

UP

DN

Vo

Tin

Td

ΔVo

D Q

R

D Q

R

CK1

CK2

Td

UP

DN

ICP

Vo

ICP

Cint

S1

S2 S1

S2

samplingconversion

sampling𝜟𝑽𝒐 = 𝑰𝐂𝐏 . 𝑻𝐢𝐧 /𝑪𝐢𝐧𝐭

CK1

CK2

UP

DN

Vo

Tin

Td

ΔVo

D Q

R

D Q

R

CK1

CK2

Td

UP

DN

ICP

Vo

ICP

Cint

S1

S2 S1

S2

samplingconversion

sampling

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IEEE ISCAS 2016

Charge-sharing Phenomenon


• Op-amp can

reduce charge-

sharing before and

after sampling

CK1

CK2

UP

DN

2 3

VO

1

Cint

+-

VO

ICP

ICP

VM

ICP

VDD/2VO

Cint

Cint

+-

VO

ICP

ICP

VM

CPN

VO

Cint

Cint

+-

VO’

ICP

ICP

VM

CPN

ICP

CPN

VO -ΔVOVDD/2

Cint

CPN

CPP

CPP

spilled

charge

spilled

charge

1. Before sampling 2. Sampling 3. Sampling finish

equal

charge

equal

charge

CPP

CPP

VDD/2

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IEEE ISCAS 2016

Pseudo Diff. Charge-pump

• Op-amps provide an

isolated CMFB voltage

from the actual

sampled voltage


VOP VONVMRM RM

Cint CCM1 Cint

VOP

Cint

VMRM RM

CCM1

+-

VON

Cint

+-

VMP VMN

Q Q

UP

DN

DN

UP

VBP,CMFB

VOP VON

VM

VCP

VCN

VBN

VBP

VCM

+-

+-

VMP VMN

DN

UP

UP

DN

VCUP

VCD

P

VCUN

VCD

N

RM RM

Ф2 Ф1CMFB

Cint Cint

CCM2 CCM1

Ф1 Ф2

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IEEE ISCAS 2016

Time-domain Feedback

• Using delay-line Digital-to-Time Converter (DTC)

• Input is delayed based on TDC’s output


TIN DIN

TOUT

…

DTC Time subtraction method

OUT>0 →delay CK1

OUT<0 →delay CK2

CK1

CK2

TIN

TIN-TOUT>0

TIN-TOUT<0

Positive input Negative input

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IEEE ISCAS 2016

Proposed ΔΣ TDC Architecture


0

1

Dout > 0

CK1

0

1

Dout < 0

CK2

UP

DN

ICP

ICP

+

+

Vinp

Vdacn

-

-Vinn

Vdacp

CintDTC

DTC

UP

DN

z-1

SA

R L

og

ic

Dout P

FD

4-bit SAR ADCΔ TVC and Σ

CDAC

CDAC

Cint

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IEEE ISCAS 2016

TDC Noise Analysis

• Thermal noise and quantization noise are

the dominant noise sources


65

70

75

80

85

90

2 3 4 5 6 7

SN

DR

(d

B)

Quantizer size (bit)

-100

-95

-90

-85

-80

2 3 4 5 6 7

No

ise p

ow

er

(dB

)

Quantizer size (bit)

Thermal noise

dominates

Quantization

noise dominates

Total noise

Thermal noise

Quantization

noise

without thermal noise

Cint = 2 pF

1 pF

0.5 pF

0.25 pF

with

thermal

noise

Cint = 0.5 pF

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IEEE ISCAS 2016

SAR ADC Quantizer

• SAR ADC: low power, low complexity, moderate speed

• Separated CDAC and charge-pump capacitor

Reduce disturbance to sampled charge

Smaller CDAC cap for faster conversion


Vrefp

Vrefn

SAR

Lo

gic

CDAC

CuCu2N-1Cu …

Vin

Dout

Vdac +-

+-

CK CK

Voutp

Voutn

CK

VinnVdacn Vinp Vdacp

[M. Miyahara, A-SSCC ‘08]

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IEEE ISCAS 2016

Performance Summary

• 830 kHz 2.4nspp input at 1 MHz bandwidth, 200 MHz

sampling freq.


-100

-80

-60

-40

-20

0

0.1 1 10 100

No

rmalized

PS

D (

dB

)

Frequency (MHz)

FBW

0

20

40

60

80

-80 -60 -40 -20 0

SN

DR

(d

B)

Input amplitude (dBFS)

20 dB/dec

SNDR = 74.9 dB

ENOB = 12.1 bit

17

IEEE ISCAS 2016

Core Layout Implementation

• Core area:

0.017 mm2


12

1 μ

m

142 μm

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IEEE ISCAS 2016

Performance Comparison

JSSC

’09

JSSC

‘14

CICC

‘13

ESSCIRC

‘15

VLSIC

‘12This*

ΔΣ TDC Type GRO SRO GSROCP+

ΔΣ ADC

CP+

Gm-C

CP+

SAR

Filter order 1st 1st 2nd 3rd 3rd 1st

CMOS (nm) 130 90 65 65 130 65

Sampling (MHz) 50 500 400 270 90 200

Bandwidth (MHz) 1.0 1.0 4.0 1.0 2.8 1.0

SNDR (dB) 95.0 63.1 80.4 N/A 67.0 74.9

Integ. noise (fsrms) 80 315 148 176 866 269

Resolution (ps)** 0.28 1.09 0.51 0.61 3.00 0.63

Power (mW) 21.0 2 6.55 8.4 2.58 0.9

FoM (fJ/conv)*** 227 860 96 N/A 250 99

Area (mm2) 0.04 0.02 0.05 0.055 0.425 0.017


*Transistor-level simulation

**Resolution = 12 × integrated noise

***FoM = Power/(2 × bandwidth × 2 (SNDR-1.76)/6.02)

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IEEE ISCAS 2016

Conclusion

• A mixed time and voltage domain TDC is

proposed

• Charge-pump is used both as VTC and

integrator to achieve low power

performance

• The ΔΣ implementation allows a good TDC

resolution while only using a low bit SAR

ADC as quantizer


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IEEE ISCAS 2016

Acknowledgement

• This work was partially supported by MIC,

STARC, HUAWEI, Mentor Graphics for the

use of the AFS Platform, and VDEC in

collaboration with Cadence Design

Systems, Inc.


A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW

Delta-Sigma Time-to-Digital Converter

Using Charge Pump and SAR ADC

Anugerah Firdauzi, Zule Xu,

Masaya Miyahara, and Akira Matsuzawa

[email protected]

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to ... · A 74.9 dB SNDR 1 MHz Bandwidth 0.9...

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