A 40–67GHz Power Amplifier with 13dBm PSAT and 16% PAE

in 28nm CMOS LP

J. Zhao, M. Bassi, A. Bevilacqua*, A. Ghilioni, A. Mazzanti

and F. Svelto

University of Pavia, Italy

*University of Padova, Italy

2

Power Amplifier Design Trade-Off

• Demand for broadband operation• Radar Imagining, Gbps Wireless, Chip-to-Chip Links

• Bandwidth trades with Gain and Efficiency

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 2

Bandwidth

EfficiencyGain

3

•Power Amplifier Design Challenges

•Output Matching Network

• Interstage Matching Network

•Measurement Results

•Conclusions

Outline

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 3

4

• Active Stages • High output power: large Ci2 and Co2

• Class AB biasing: high efficiency but low gm

• Investigating high-order matching networks is key

Power Amplifier Design Challenges

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 4

Keeping

high GBW

challenging

5

• Handle large parasitic capacitors

• Wideband impedance matching

• Minimize insertion loss

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP

Matching Network Targets

5

6

• Simple topology and low losses

• Two peaking frequencies:

• L2 used to control the bandwidth

• ZIn ≈ RL within band

1 3

21 1 3 3

1 1, 1 L H L

L L

LL C L C

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP

Candidate Matching Network

6

7

• Transformer for differential to single-ended conversion

• L2S implemented by the parasitic inductor of the trace connecting pads to the transformer

• Impedance scaling required for large output power

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 7

Output Matching Network

30 40 50 60 70 8020

25

30

35

Frequency [GHz]

|Vo

ut/

Iin

| [d

B]

Q=100 Q=30 Q=10

30 40 50 60 70 8022

24

26

28

30

32

Frequency [GHz]

|Vo

ut/

Iin

| [d

B]

Q=10

8

• Limited inductor Q leads to asymmetric frequency response

• Coupled resonator can be conveniently tuned to minimize in-band ripple

Decreasing Q Increasing L1/L3

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 8

In-Band Ripple Minimization

1

3

( )

( )

T H

T L

Z L

Z L

9

• L resonates CO and CI at center frequency

• Explicit resistor RE increases bandwidth but decreases gain

• Larger MIn required to restore gain level at the cost of increased power consumption

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 9

Traditional Interstage Matching Network

10

• Inductively coupled resonator features better GBW than simple LC network

• For the same gain and bandwidth, this property is exploited to scale down the size of input transistor by n≈2

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 10

Coupled Resonator Based Network

10

• Norton transformation further reduces the size by t≈1.5 while keeping the same GBW

• nt≈3 times smaller power consumption in the input stage than the traditional approach

• Use of transformer simplifies routing and biasing

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 11

Interstage Matching Network

11

• Neutralization increases stability but also Qin

• Inductive degeneration decreases Qin to achieve wideband input matching and enhances linearity

• Mutual coupling facilitates layout routing and reduces inductors length

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 12

Input Matching Network

113

• Design targets• P1dB > 10 dBm, Bandwidth > 20 GHz

• Gain > 10 dB, PAE > 10%

40um/28nm 200um/28nm

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 13

Complete PA Schematic

G

S

G

G

S

G

13

ST 28nm CMOS LP, chip area: 0.34 mm2

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 14

Chip Microphotograph620 μm

540

μm

14Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 15

Measured S-Parameters

30 35 40 45 50 55 60 65 70-60

-50

-40

-30

-20

-10

0

10

20

Frequency [GHz]

S-P

ara

mete

rs [

dB

]

S21

S11

S22

S12

30 40 50 60 7010

0

101

102

103

Frequency [GHz]

K

30 40 50 60 7020

30

40

50

60

70

80

90

100

Gro

up D

ela

y [ps]

14Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 16

K-Factor and Group Delay

K >10 and |∆|<1 in measured frequency band

Group delay variation < ± 4ps from 47-67GHz

K-Factor

Group Delay

15

PSAT≈13.3dBm, P1dB≈12dBm, PAE=16%, Pdc=104mW @ 50GHz

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 17

Large Signal Performances at 50GHz

-15 -10 -5 0 5-5

0

5

10

15

20

Input Power [dBm]

Pout

[dB

m]

/ G

ain

[dB

] /

PA

E [

%]

Pout Gain PAE

40 42 44 46 48 500

5

10

15

20

Frequency [GHz]

P1dB [

dB

m]/

PS

AT [

dB

m]/

PA

Ep

eak [

%]

P1dB

PSAT PAE

16Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 18

Large Signal Performances vs Frequency

Uniform PSAT and P1dB from 42-50GHz

17

Largest bandwidth with state-of-the-art efficiency and output power

ReferenceTech.

& Vdd

Gain

[dB]

BW

[GHz]

GBW

[GHz]

PSAT

[dBm]

P1dB

[dBm]

PAE

[%]

Frac.

BW [%]

JSSC 11 65nm / 1.8V 16 21.0 133 13.0 8.0 8.0 35

JSSC 10 65nm / 1V 16 9.0 57 11.5 n.d. 15.2 15

RFIC 10 45nm / 2V 20 13.0 130 14.5 11.2 14.4 22

RFIC 11 65nm / 1.2V 18 12.5 99 9.6 n.d. 13.6 21

This Work 28nm / 1V 13 27.0 121 13.0 12.0 16.0 51

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 19

Performance Summary and Comparison

18

• Matching networks are key to design broadband PAsat mm-waves while keeping high efficiency

• A methodology for wideband and compact matchingnetworks was proposed

• A two-stage one-path PA with 13dBm PSAT, 16% PAE,and 27 GHz BW in 28nm CMOS was demonstrated

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP 20

Conclusions

Thank You!

Zhao et al., A 40-67GHz PA with 13dBm Psat and 16% PAE in 28nm CMOS LP