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A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for Analog TV Applications

Sang-Pil Nam, Yong-Min Kim, Dong-Hyun Hwang, Hyo-Jin Kim, Tai-Ji An, Jun-Sang Park, Suk-Hee Cho, Gil-Cho Ahn, and Seung-Hoon Lee

Dept. of Electronic Engineering, Sogang University, Seoul, Korea : hoonlee@sogang.ac.kr

Abstract— This work proposes a 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC optimizing power consumption and chip area for analog TV (NTSC/PAL) applications. The proposed DAC employs a 2-step (6b-4b) split-capacitor array with the VCM-based switching method for high power efficiency and small chip area. Additionally, a range-scaling technique is employed for a rail-to-rail input signal swing. The comparator accuracy is improved by offset cancellation techniques in the first-stage pre-amp. The prototype ADC in a 0.11um CMOS technology demonstrates the measured DNL and INL within 1.07LSB and 1.66LSB, respectively. The ADC shows a maximum SNDR of 54.4dB and a maximum SFDR of 69.8dB at 10MS/s, respectively. The ADC with an active die area of 0.25mm2 consumes 2.3mW at a 1.2V and 10MS/s.

Keywords- analog-to-digital converter (ADC); range-scaling; split-capacitor array; VCM-based switching; analog TV

I. INTRODUCTION For typical color encoding methods of analog broadcasting

systems, there are national television system committee (NTSC) type used in Republic of Korea (ROK) and Japan, and phase-alternating line (PAL) type used in Europe. In particular, analog-to-digital converters (ADCs) with a resolution of 10b and a sampling rate of several MS/s are necessarily required as an essential key building block converting analog video input signals, encoded as NTSC or PAL type, into digital output signals. The ADCs for analog TV (NTSC/PAL) applications are also in demand to process single-ended analog input signals.

Of various ADC architectures, the pipeline, algorithmic, delta-sigma, and successive-approximation register (SAR) topologies have been commonly employed to achieve a resolution of over 10b. However, the reduced output impedance due to a short channel-length effect from scaling down CMOS technologies makes it extremely challenging to design a high-gain amplifier, which is the core circuit of the pipeline, algorithmic, and delta-sigma ADCs. On the other hand, the SAR ADC based on digital circuits uses only one comparator without inter-stage amplifiers. As a result, the SAR ADC architecture is well suitable for advanced CMOS technologies [1-3].

II. PROPOSED SAR ADC ARCHITECTURE The proposed 10b 1MS/s-to-10MS/s SAR ADC for analog

TV (NTSC/PAL) applications consists of a digital-to-analog converter (DAC), a comparator, a digital logic circuit, on-chip

current and voltage references, and an on-chip clock generator, as shown in Fig. 1. The range-scaling scheme is employed to properly handle a single-ended input range of 1.2VP-P without additional circuits with complicated algorithms. The DAC, a major functional circuit block of the SAR ADC, employs a 2-step (6b-4b) split-capacitor array with the VCM-based switching method [4] and uses two unit capacitors in series (CU/2) to act as a minimum unit capacitor for high power efficiency and small chip area. The offset-cancellation technique for high comparator accuracy is applied to the first-stage pre-amp. The digital blocks, such as the SAR logic and control logic, are optimized to reduce both power consumption and chip area further. On the other hand, the noise due to a disturbance of power supply is reduced by implementing the proposed ADC as a fully differential circuit structure, even if dealing with single-ended input signals. As a result, the proposed SAR ADC processes the single-ended input signals without the degradation of performance.

Fig. 1. Proposed 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC.

III. CIRCUIT IMPLEMENTATION

A. Proposed Range-scaling Scheme for a Rail-to-rail Single-ended Input Signal Swing In the conventional SAR ADC, when processing single-

ended input signals, the input signal swing is considerably limited by a lack of headroom margin at the pre-amp in the comparator [5-6], and thus may lead to a poor peak signal-to-noise ratio (SNR). To overcome this degradation of performance, a rail-to-rail input signal swing is highly required in the single-ended SAR ADC.

This work was supported by Dongbu HiTek, the Ministryof Knowledge, Economy, Korea, under the University ITRCprogram supervised by the National IT Industry PromotionAgency (NIPA-2012-H0301-12-1007), and the Basic ScienceResearch Program through the National Research Foundationfunded by the Ministry of Education, Science and Technology(2012-000-2297). 978-1-4673-2990-3/12/$31.00 ⓒ2012 IEEE - 124 - ISOCC 2012

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In [7], the p-type and n-type differential pre-amps connected in a parallel manner are proposed for a rail-to-rail input signal swing. Although this technique using two types of pre-amps is possible to extend an input signal range to the power rails, power dissipation and chip area are increased by the additional pre-amp and the performance of the SAR ADC is limited by an offset mismatch between the two pre-amps.

This paper proposes a range-scaling scheme to process a rail-to-rail input signal swing without any additional circuits, as shown in Fig. 2. The conventional single-ended SAR ADC samples the input signal to an overall sampling capacitor (CS), as shown in Fig. 2(a). Consequently, the pre-amp in the comparator suffers from a lack of headroom margin caused by a wide signal swing range. However, the proposed range-scaling scheme attenuates an input signal of 1.2VP-P to an internal signal of 0.6VP-P by sampling the input signal on only the most significant bit (MSB) capacitor (24CU) corresponding to a half of a sampling capacitor (CS/2), as shown in Fig. 2(b). The remaining half of the sampling capacitor (CS/2) is reset to a common-mode voltage (VCM). As a result, the pre-amp in the comparator has a sufficient dynamic voltage headroom even with a rail-to-rail input signal swing.

(a)

(b)

Fig. 2. DAC of the single-ended SAR ADC during the sampling phase : (a) the conventional scheme and (b) the proposed range-scaling scheme.

B. Various Circuit Design Techniques to Minimize Power Dissipation and Chip Area in the DAC The proposed DAC employs a 2-step (6b-4b) split-

capacitor array and a VCM-based switching method in order to remove the MSB capacitor (25CU), achieving low power dissipation and small chip area. Additionally, two unit capacitors in series (CU/2) to act as a minimum unit capacitor are implemented to eliminate 23CU, as shown in Fig. 3.

Fig. 3. Proposed DAC with various circuit design techniques.

In the case of the proposed DAC with a 2-step (6b-4b) split-capacitor array, the upper 6b are decided by the right capacitor array of the attenuation capacitor (CA), while the lower 4b are decided by the left capacitor array of the attenuation capacitor (CA). The MSB capacitor of the proposed 2-step (6b-4b) split-capacitor array is reduced from 29CU to 24CU when compared with a conventional binary-weighted capacitor array. Thus, the 2-step (6b-4b) split-capacitor array is very helpful regarding low power consumption and small chip area of the proposed ADC. On the other hand, although the attenuation capacitor (CA), 1.1427CU, is not a multiple of the unit capacitor (CU), the capacitor mismatch can be minimized by using appropriate layout techniques enclosing all capacitors with other metals for an identical environment and parasitic capacitance [8].

Recently, the set-and-down switching method and the VCM-based switching method are mainly employed to minimize the chip area of the DAC [4], [9]. The set-and-down switching method removes the MSB capacitor by determining the MSB bit without an additional switching operation after sampling the input signal. However, the input common-mode voltage variations of the comparator and the clock feed-through depending on the input signal are caused by sampling the input signal through the top plate of the sampling capacitors.

In contrast, the VCM-based switching method fundamentally removes the input common-mode voltage variations by sampling the input signal through the bottom plate of the sampling capacitors. The MSB capacitor is also eliminated by directly comparing the sampled input signal with the common-mode voltage (VCM) during the conversion phase.

In this work, the gate-bootstrapping switch is employed to minimize the non-linear distortion of sampled inputs caused by the on-resistance variations of sampling switches [10]. The size ratio of the capacitors and switches in the input sampling network is carefully designed to achieve an accuracy exceeding 10b at a low supply voltage.

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C. Offset-cancellation Technique in a Comparator A simple latch-based comparator without a pre-amp has

been recently reported to reduce power consumption in SAR ADCs [11-12]. In this case, output codes corresponding to a full-scale input signal are not generated by an undesired latch offset. Therefore, calibration techniques are required in order to minimize the latch offset [13]. However, most calibration techniques not only make the circuits complicated, but also increase power consumption and chip area.

Conversely, the proposed comparator consists of a two-stage pre-amp and a latch without additional calibration circuits, as shown Fig. 4. Particularly, the two-stage pre-amp minimizes the latch offset. The offset of the first-stage pre-amp is also removed by the offset-cancellation technique, while the offset of the second-stage pre-amp hardly affects the performance of the SAR ADC due to the division by the gain of the first-stage pre-amp. Furthermore, the reset switch is implemented in the output stage of the second-stage pre-amp to eliminate the effects of the pre-amp output from the previous phase.

Fig. 4. Proposed comparator with offset cancellation technique.

IV. MEASUREMENT RESULTS The prototype 10b 1MS/s-to-10MS/s ADC is implemented

in a 0.11um CMOS technology as shown in Fig. 5. The ADC with an active die area of 0.25mm2 dissipates 2.30mW including on-chip current and voltage references, and 1.64mW excluding on-chip current and voltage references, at 10MS/s and a supply voltage of 1.2V. The measured differential non-linearity (DNL) and integral non-linearity (INL) are within 1.07LSB and 1.66LSB, respectively, as shown in Fig. 6. As plotted in Fig. 7, the measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 54.4dB and 69.8dB, respectively, at 10MS/s with a sinusoidal single-ended input signal of 1.2VP-P and 1MHz. The measured SNDR and SFDR with different sampling frequencies up to 10MS/s are illustrated in Fig. 8. The SNDR and SFDR in Fig. 9 are measured with input frequencies, which increase up to double of the Nyquist frequency, at 10MS/s. Overall, the SNDR and SFDR are maintained above 53.8dB and 64.7dB, respectively. Also, the dynamic performance has no difference between the single-ended input signal and the differential input signal. The performance of the prototype ADC is summarized in Table I.

Fig. 5. Chip photograph of the proposed 10b 1MS/s-to-10MS/s SAR ADC.

Fig. 6. Measured DNL and INL of the prototype ADC.

Fig. 7. Measured FFT spectrum of the prototype ADC.

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Fig. 8. Measured SNDR and SFDR versus sampling frequency.

Fig. 9. Measured SNDR and SFDR versus input frequency.

TABLE I. PERFORMANCE SUMMARY OF THE PROTOTYPE ADC

V. CONCLUSION This work proposes a 10b 1MS/s-to-10MS/s 0.11um

CMOS SAR ADC for analog TV (NTSC/PAL) applications. The DAC employs a 2-step (6b-4b) split-capacitor array with the VCM-based switching method and uses two unit capacitors in series (CU/2) as a minimum unit capacitor for high power

efficiency and small chip area. In addition, a range-scaling scheme is applied to properly handle a rail-to-rail input signal. The offset-cancellation technique in the first-stage pre-amp improves the comparator accuracy. A fully differential circuit structure is also employed to remove the noise caused by a disturbance of power supply, even if dealing with single-ended input signals. The prototype ADC shows a maximum DNL and INL within 1.07LSB and 1.66LSB, respectively. The ADC shows a maximum SNDR of 54.4dB and a maximum SFDR of 69.8dB at 10MS/s, respectively. The ADC with an active die area of 0.25mm2 consumes 2.30mW including on-chip current and voltage references, and 1.64mW excluding on-chip current and voltage references, at 10MS/s and a 1.2V supply voltage.

ACKNOWLEDGMENT This work was supported by Dongbu HiTek, the Ministry

of Knowledge, Economy, Korea, under the University ITRC program supervised by the National IT Industry Promotion Agency (NIPA-2012-H0301-12-1007), and the Basic Science Research Program through the National Research Foundation funded by the Ministry of Education, Science and Technology (2012-000-2297).

REFERENCES [1] M. Yip, and A. P. Chandrakasan, "A resolution-reconfigurable 5-to-10b

0.4-to-1V power scalable SAR ADC," in ISSCC Dig. Tech. Papers, Feb. 2011, pp. 190-192.

[2] T. G. R. Kuntz, C. R. Rodrigues, and S. Nooshabadi, "An energy-efficient 1MSps 7uW 11.9fJ/conversion step 7pJ/sample 10-bit SAR ADC in 90nm," in Proc. ISCAS, May 2011, pp. 261-264.

[3] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. De Groot, "A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion step," in ISSCC Dig. Tech. Papers, Feb. 2012, pp. 472-474.

[4] Y. Zhu, et al., "A 10-bit 100-MS/s reference-free SAR ADC in 90nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, Jun. 2010.

[5] S. Mortezapour, and E. K. F. Lee, "A 1-V, 8-bit successive approximation ADC in standard CMOS process," IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 642-646, Apr. 2000.

[6] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, "A 0.5-V 1-uW successive approximation ADC," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261-1265, Jul. 2003.

[7] H. C. Hong, and G. M. Lee, "A 65-fJ/conversion-Step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2161-2168, Oct. 2007.

[8] Y. J. Cho, K. H. Lee, H. C. Choi, S. H. Lee, K. H. Moon, and J. W. Kim, "A calibration-free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS pipeline ADC with high-matching 3-D symmetric capacitors," in Proc. CICC, Sep. 2006, pp. 485-488.

[9] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, "A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS process," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009, pp. 236-237.

[10] A. M. Abo, and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.

[11] Y. Chen, S. Tsukamoto, and T. Kuroda, "A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS," in Proc. ASSCC, Nov. 2009, pp. 145-148.

[12] M. V. Elzakker, et al., "A 1.9uW 4.4fJ/conversion-step 10b 1MS/s charge-redistribution ADC," in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 244-246.

[13] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, "A 10b 50MS/s 820uW SAR ADC with on-chip digital calibration," in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 384-385.

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