A 10 bit,100 MHz CMOS Analog-to-Digital Converter

Outline

IntroductionHigh Speed A/D Converter ArchitecturesProposed A/D Converter ArchitectureCircuit Design and SimulationsPrototype Chip Test ResultsConclusionResearch Plan

Applications of High Speed High Resolution A/D Converter

High frequency digital data communicationWaveform acquisition instrumentsMedical ImagingVideo Signal Processing

Increasing DSP complexity in communications systems

High Resolution High Speed CMOS A/D Converters

Fully Parallel(Flash) A/D Converter

Conceptually most straightforward

1. Highest possible speed

2. Resolution: 8-10bits Disadvantages

1. 2 comparators requires

So, Hardware complexity grows

exponentially with resolution

2. Large power dissipation and

input capacitance

Two-Step A/D Converter

Less hardware complexity than Flash type Digital error correction is possible Disadvantages:

Requires inter-stage amplifier

(longer conversion time) Requires multiple clocks per conversion

Multi-Stage Pipeline A/D Converter

Well-suited to CMOS, as residue amplifier has built-in S/H May repeat same blocks in cascade Approximately linear hardware cost with resolution Limitations:

1. Residue amplifier settling is speed bottleneck

2. Linearity determined by input S/H and residue formation

Parallel Pipelined A/D Converter

Conversion rate increases with the number of channels Input S/H must acquire singal at full Nyquist bandwidth Performance ultimately limited by:

1. Timing skews and jitter between channels

2. Mismatch in gain, offset and full scale between channels

Effect of Sampling Timing Offset in Parallel Pipelined A/D Converter

SNR with gain mismatch 2 channel pipeline ADC

Design Specification

10 bit resolution 100 MHz conversion rate Fully Differential Implementation 1.0V input full scale 1.0m n-well CMOS technology with linear capacitance option 1.0 W power dissipation 2-channel 3-stage pipelined architecture 4 bit/stage conversion Parallel Pipeline Switch Cap. Residue Amplifier Resistor Ladder DAC On-chip clock buffer

Detail Block Diagram of Architecture

Timing Diagram of S/H, 4-bit ADDA, and RA

Schematic of Non-resetting S/H

Equivalent to two resetting S/H Following stage can obtain the valid data for full period(10ns) Disadvantage:

Ch and Cd increase a time constant

Simulated Dynamic Performance of S/H

4-bit AD-DA Block Diagram

Residue Amplifier

Gain of 2 Residue Amplifier: Generate a residue (subtract DAC output from S/H output) Reduce inter-channel offect Offset Cancellation Scheme

Gain of 4 Residue Amplifier: Reduce inter-channel offset Offset Cancellation Scheme Compensation capacitor added ot stabilized loop when

sampling

Digital Circuit in ADC

Clock Generation Circuit

Measured SNDR,THD,and SFDR at 500 KHz input

Measured Signal / (Noise+Distortion) at 4, 50 & 95 MHz Sampling rate

Power Dissipation

Total power dissipation

= 1.1W @ 95MS/s

Floor Plan of A/D Converter

Layout Design Issues: Clock distribution Reduce the Offset in

Residue Amplifier

Summary of A/D Characteristics

Conclusions

10-bit resolution95MS/s conversion rate1m n-well CMOS technology with linear capacitor op

tionSpurious tones are less -65db after simple on chip offse

t cancellation1.2W power dissipation @ single 5VDigital error correctionFirst 10-bit, 100MS/s CMOS ADC

Research Plan

Investigate further effects of architecture on SFDRHope to design 14bit linear input S/H capable of 2.5

MHz or higher clock rate

Considerations: Nonlinearity in interstage of ADC

(For example: Offset, Gain, Carpacitor and

Resistor mismatch, Timing mismatch ..)