8284 Manual

COE305 LAB Manual

Khaled A. Al-Utaibi

Copyright c©2013, University of Hail, Hail, Saudi Arabia. All rights reserved.http://www.uoh.edu.sa

http://www.uoh.edu.sa

Contents

Preface • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • iii

1 Introduction to Proteus VSM (Part I) • • • • • • • • • • • • • • • • 1

1.1 Proteus Virtual System Modeling (VSM) 1

1.2 Overview of the ISIS Editor 3

1.3 Design Example 6

1.4 Schematic Entry of the Modulo-5 Binary Counter 7

2 Introduction to Proteus VSM (Part II) • • • • • • • • • • • • • • • • 17

2.1 Design Example 17

2.2 Frequency Divider by 5 with a 50% Duty Cycle 18

2.3 Schematic Entry of the Frequency Divider Circuit 19

3 Clock Generator 8284A • • • • • • • • • • • • • • • • • • • • • • 25

3.1 Pin Functions of the 8284A Clock Generator 25

3.2 Operations of the 8284A Clock Generator 27

3.3 Schematic Entry of the 8284A Clock Generator 28

4 8086 Basic Connections • • • • • • • • • • • • • • • • • • • • • • 35

4.1 Pin Functions of the 8086 Microprocessor (Minimum Mode) 35

4.2 Basic Connections of the 8086 Microprocessor (Minimum Mode) 39

4.3 Testing the 8086 Microprocessor 40

5 Designing the Bus System • • • • • • • • • • • • • • • • • • • • • 47

5.1 Bus Buffering and Latching 47

ii

5.2 Testing the Bus System 49

6 Designing the Memory System • • • • • • • • • • • • • • • • • • 57

6.1 8086 Memory Mapping 57

6.2 Designing the Memory System 57

6.2.1 Testing the Memory System 63

7 Designing a Parallel I/O Port• • • • • • • • • • • • • • • • • • • • 69

7.1 8086 I/O Mapping 69

7.2 Designing a Simple 8-Bit Parallel Port 71

7.2.1 Testing the I/O Port 73

Appendix • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 75

Preface

This LAB Manual is intended to guide computer engineering students to design and fa-

bricate an 8086-based microcomputer system. The manual consists of a set of experiments

for gradually designing, assembling and testing a single-board 8086-based microcomputer

system. Through the gradual construction process, students will gain knowledge and ex-

perience in circuit design, wire-wrapping and soldering techniques, board design and parts

layout, static and dynamic testing, programming, use of test equipment for analysis and

troubleshooting, and data acquisition. Upon completion of the project, the student will

have constructed a fully functional single-board 8086-based microcomputer with a fully-

demultiplexed and buffered bus system, a 32KB memory system, a simple 8-bit parallel

input/output (I/O) port.

The students will also be exposed to common I/O peripheral devices such as the 8251A

Universal Synchronous/Asynchronous Receiver/Transmitter (USART), the 8255A Program-

mable Peripheral Interfaces (PPI), the 8253 Programmable Interval Timer (PIT), and the

8259A Programmable Interrupt Controller (PIC). The LAB manual provides a set of design

and programming experiments to teach the students how interface these I/O peripheral de-

vices to the 8086-based microcomputer system and use assembly programming to operate

them.

The LAB manual include the following set of experiments :

1. Introduction the Proteus Virtual System Modeling (VSM) - Part I.

2. Introduction the Proteus Virtual System Modeling (VSM) - Part II.

3. The 8284A Clock Generator.

4. Basic Connections of the 8086 Microprocessor.

iv Preface

5. Designing a Fully-Demultiplexed and Buffered Bus System.

6. Designing a 32KB Memory System.

7. Designing a Simple 8-Bits Parallel I/O Port.

8. Programming and Testing the 80806-Based Microcomputer System.

9. Interfacing and Programming the 8255A Programmable Peripheral Interfaces (PPI).

10. Interfacing and Programming the 8253 Programmable Interval Timer (PIT).

11. Interfacing and Programming the 8259A Programmable Interrupt Controller (PIC).

Sincerely,

Khaled A. Al-Utaibi

January 2013

1 — Introduction to Proteus VSM (Part I)

LAB Objectives

The aim of this LAB experiment is to familiarize students with the techniques required

to design and simulate digital circuits using Proteus Virtual System Modeling (VSM)

software package. The experiment is design to guide the students through the process of

designing, editing and simulating a simple modulo-n counter circuit using the schematic

editor ISIS. The LAB covers basic schematic editing topics such as placing and wiring up

components, and then moves on to circuit testing using virtual modeling and simulation.

1.1 Proteus Virtual System Modeling (VSM)

Proteus Virtual System Modeling (VSM) software offers the ability to co-simulate both

high and low-level micro-controller code in the context of a mixed-mode SPICE circuit

simulation. It combines mixed mode SPICE circuit simulation, animated components and

microprocessor models to facilitate co-simulation of complete micro-controller based designs.

With VSM, it is possible to develop and test such designs before a physical prototype is

constructed. The designer can interact with the design using on screen indicators such

as LED and LCD displays and actuators such as switches and buttons. The simulation

takes place in real time, e.g., a 1GMHz Pentium III can simulate a basic 8051 system

clocking at over 12MHz. Proteus VSM also provides extensive debugging facilities including

breakpoints, single stepping and variable display for both assembly code and high level

language source.

2 Introduction to Proteus VSM (Part I)

Schematic Entry

Proteus VSM uses ISIS schematic capture software to provide the environment for design

entry and development. The ISIS software combines ease of use with powerful editing tools.

It is capable of supporting schematic capture for both simulation and PCB design. Designs

entered in to Proteus VSM for testing can be net-listed for PCB layout either with Proteus

PCB Design products or with third party PCB layout tools. ISIS also provides a very high

degree of control over the drawing appearance, in terms of line widths, fill styles, fonts, etc.

These capabilities are used to provide the graphics necessary for circuit animation.

Circuit Simulation

The Proteus VSM includes the ProSPICE which is an established product that combines

uses a SPICE3f5 analogue simulator kernel with a fast event-driven digital simulator to

provide seamless mixed-mode simulation. The use of a SPICE kernel allows the designer to

utilize any of the numerous manufacturer-supplied SPICE models now available and around

6000 of these are included with the package.

Proteus VSM includes a number of virtual instruments including an Oscilloscope, Logic

Analyzer, Function Generator, Pattern Generator, Counter Timer and Virtual Terminal as

well as simple voltmeters and ammeters.

The Advanced Simulation Option allows the designer to take detailed measurements

on graphs, or perform other analysis types such as frequency, distortion, noise or sweep

analyses of analogue circuits. This option also includes Conformance Analysis - a unique

and powerful tool for Software Quality Assurance.

Co-Simulation of Micro-controller Software

The most important feature of Proteus VSM is its ability to simulate the interaction between

software running on a micro-controller and any analog or digital electronics connected to it.

The micro-controller model sits on the schematic along with the other elements of pro-

duct design. It simulates the execution of designer object code (machine code), just like a

real chip. If the program code writes to a port, the logic levels in circuit change accordingly,

and if the circuit changes the state of the processor’s pins, this will be seen by the program

code, just as in real systems.

The VSM CPU models fully simulate I/O ports, interrupts, timers, USARTs and all other

peripherals present on each supported processor. The interaction of all these peripherals

with the external circuit is fully modeled down to waveform level and the entire system is

therefore simulated.

The VSM can simulate designs containing multiple CPUs by placing two or more pro-

cessors on a schematic and wire them together.

Source Level Debugging

Whilst Proteus VSM is unique in its capability to run near real time simulations of complete

micro-controller systems, its real power comes from its ability to perform these simulations

in single step mode. This works just like any software debugger, except that as the user single


step the code, he can observe the effect on the entire design - including all the electronics

external to the micro-controller.

Diagnostic Messaging

Proteus is equipped with comprehensive diagnostic or trace messaging. This allows the

designer to specify which components or processor peripherals that are of interest at any

given time and receive detailed textual reporting of all activity and system interaction. This

is invaluable as a debugging aid, allowing the designer to locate and fix problems in both

software and hardware much faster than he could when working on a physical prototype.

Peripheral Model Libraries

In addition to the microprocessor models for each supported family, and literally thousands

of ’standard’ models for passives, TTL/CMOS, memories, etc. Proteus VSM is equipped

with a comprehensive library of embedded peripheral models, from alphanumeric and gra-

phical LCD displays, through DC, BLCD and servo motors to Ethernet controller chips.

1.2 Overview of the ISIS Editor

To start the ISIS program, click on the Start button and select Programs, Proteus 7 Profes-

sional and then the ISIS 7 Professional option (See Figure 1.1). The ISIS schematic editor

will then load and run.

The ISIS editor consists of three main areas as shown in Figure 1.2 :

1. The Editing Window : acts as a window on the drawing - this is where you will

place and wire-up components.

2. Object Selector : lists objects inserted into the Editing Window and allows you to

select new objects to be inserted from the ISIS library.

3. Overview Window : In normal use, the Overview Window displays an overview of

the entire drawing - the blue box shows the edge of the current sheet and the green

box the area of the sheet currently displayed in the Editing Window. However, when

a new object is selected from the Object Selector the Overview Window is used to

preview the selected object

Editing Modes

The ISIS provide several editing tools (or modes) to facilitate schematic editing. These

tools can be selected from the left bar menu. Figure 1.3 list the editing tools and their

corresponding icons for your reference during this experiment.

Zooming

There are several ways to zoom in and out of areas of the schematic :

– Point the mouse where you want to zoom in and out of and roll the middle mouse

button (roll forwards to zoom in and backwards to zoom out).


Figure 1.1 – Starting the ISIS editor.

Figure 1.2 – ISIS schematic capture window. (1) Editing Window, (2) Object

Selector, and (3) Overview Window.


Figure 1.3 – Editing modes.


– Point the mouse where you want to zoom in or out of and and press the F6 or F7

keys respectively.

– Hold the SHIFT key down and drag out a box with the left mouse button around

the area you want to zoom in to. We call this Shift Zoom

– Use the Zoom In, Zoom Out, Zoom All or Zoom Area icons on the toolbar (See Fi-

gure 1.4).

Figure 1.4 – Zoom icons.

Visual Aids of the Design

ISIS provides two main ways to help you see what is happening during the design process.

Objects are encircled with a dashed line or twitched when the mouse is over them and mouse

cursors will change according to function. Essentially, the object-twitching scheme tells you

which object the mouse is over (the hot object) and the mouse cursor tells you what will

happen when you left click the mouse on that object. A summary of cursors used, together

with their actions, is provided in Figure 1.5.

Figure 1.5 – Cursor description.

1.3 Design Example

In this experiment we will design a a modulo-5 binary counter which counts (0, 1, 2, 3, 4, 0, 1, 2, . . . , etc).

This counter can be implemented using a 4-bit binary counter with asynchronous reset

input. The modulo-5 count is achieved by gating the outputs of the 4-bit binary coun-

ter (Q3Q2Q1Q0) through an "AND" gate and connecting it to the asynchronous reset


input MR such that the counter is cleared when the count reaches 5 (Q3Q2Q1Q0 =

0101). Note that, the binary value 0101 can be distinguished from lower binary counts

(0000, 0001, 0010, 0011, 0100) by the values of Q2 and Q0 together. Thus, as shown in Fi-

gure 1.6, the asynchronous reset input of the counter is connected to Q2Q0.

Exercise 1.1 List the binary counts for a modulo-3 counter and show how to gate the outputs of the

4-bit binary counter to implement this modulo counter. Repeat the exercise for modulo-4, modulo-6,

and modulo-7 counters.

CLK

CLK1

Q03

Q14

Q25

Q36

MR2

COUNTER4

74LS393

1

2

3

AND2

74LS08

Q0

Q1

Q2

Q3

Figure 1.6 – Modulo 5 binary counter.

1.4 Schematic Entry of the Modulo-5 Binary Counter

This section will guide through the design process of the modulo-5 binary counter shown in

Figure 1.7.

Figure 1.7 – Schematic of the modulo-5 binary counter.

The first thing we need to do is to get the components from the libraries that we need

in our schematic.


Selecting Components from the Library

You can select components from the library in one of three ways :

– Click on the Library drop-down menu in the ISIS menu bar, and then click on Pick

Device/Symbol as shown in Figure 1.8(a).

– Click on the P button at the top left of the Object Selector as shown in Figure 1.8(b).

– Right click the mouse on an empty area of the schematic and select Place → Component

→ From Libraries from the resulting context menu as shown in Figure 1.8(c).

(a) (b) (c)

Figure 1.8 – Selecting Components. (a) library menu, (b) parts button, (c) place

menu.

Either one of these three methods will cause the Device Library Browser dialogue form

to appear (See Figure 1.9). For reference, the following is a list of all the components we

will need for our design :

74LS393

74LS08

MINRES100R

LED-RED

There are several ways in which we can find and import components from the libraries

into the schematic :

– You can enter a device name "74LS393" directly into into the Keywords field on the

Device Library Browser dialogue form.

– You can search for a device type such as "resistor" in the library browser.

– You can search for a device by selecting a device category such as "TTL 74LS series"

from the Category List Box.


Figure 1.9 – Device library browser.

Placing Objects on the Schematic

Having selected the devices we need the next thing is to actually place them on the drawing

area - the Editing Window - and wire them together.

To place the selected device on the drawing area, you can do the following :

– Click the "OK" button in the library browser to get back to the drawing area.

– Left click on the schematic to enter placement mode.

– Move the mouse to the desired location for the device.

– Left click the mouse again to "drop" the device and commit placement.

Often we need to move devices or blocks of circuitry after placement. The procedure for

this should be familiar to most users ; we need to select the object(s) we want to move, left

depress the mouse, drag to the new location and finally release the mouse to drop.

We can select an object in ISIS in several ways as detailed below :

– Choose the Selection Mode (See Figure 1.3 and then left click on the object.

– Right clicking the mouse on an object will both tag the object and present a context

menu containing available actions on that object.

– Draw a "tagbox" around the object by depressing the left mouse button and dragging

the mouse to form a box encompassing the object to be selected. This is the technique

that should be used for moving multiple, connected objects or blocks of circuitry.

Exercise 1.2 Referring to Figure 1.7, place the following components into the Editing Window : one

4-bit binary counter (74LS393), four 100Ω resistors (MINRES100R), four light-emitting diodes (LED-

RED), and one "AND" logic-gate (74LS08).

To place the clock generator, choose the Generator Mode from the left menu bar and then

select DCLOCK from the Generators list box as shown in Figure 1.10(a). Similarly, you

can place the ground terminal by choosing the Terminals Mode and then select GROUND

from the Terminals list box as shown in Figure 1.10(b).

Changing Properties of a Device

When a component is placed on the drawing area, we can modify its properties either by

double clicking the component object or by right clicking on the component and selecting

"Edit Properties". The Properties window contains a number of characteristics (if available

or applicable depending on the component type) such as : component name, type, value,


(a) (b)

Figure 1.10 – Placing components using Editing Modes. (a) clock generator, (b)

ground terminal.

data sheet, PCB layout, etc. As an example, consider the Properties window of the resistance

"R3" in the modulo-5 counter schematic as shown in Figure 1.11. In this window, you can

modify the resistance name, value, model type, or PCB package.

Figure 1.11 – Properties window for a resistance component.

Exercise 1.3 Check the properties of the components you have placed in Exercise 1.2 and modify their

names according to Figure 1.7.

Wiring Up

There are three main techniques used to make wiring a circuit :

1. Modeless Wiring : there is no "wiring mode" in ISIS - wires can be placed and edited

at any time, without the need of entering a dedicated wiring mode prior to placement.

2. Follow-Me Wire Auto-routing : after starting to place a wire, the proposed route of

the wire will follow the movement of the mouse orthogonally to the termination point

of the wire.


3. Live Cursor Display : the cursor will change as a visual indicator when wiring to

show when a wire can be placed, when a wire can be terminated and when a wire is

being placed.

The basic procedure for placing a wire between two pins is given below :

– Move the mouse over the first pin to be connected - the cursor will change to a green

pen as shown in Figure(a).

– Left click the mouse and then move it until it is over the second pin to be connected.

The wire will follow the mouse and the cursor / pen is white during wiring as shown

in Figure(b).

– Left click the mouse again to commit the connection and place the wire as shown in

Figure(c).

(a) (b) (c)

Figure 1.12 – wring up.

The procedure for wiring onto an existing wire is almost identical but there are a couple

of items to note :

– You cannot directly start a connection from an arbitrary point on a wire.

– When you terminate the connection on another wire a junction dot will be placed

automatically to complete the connection as shown in Figure.

Figure 1.13 – Wiring onto an existing wire.

Exercise 1.4 Referring to Figure 1.7, wire up the components you have placed in Exercise 1.2.

Making Connection with Terminals

In the case of large circuits, using direct connections between different components of the

circuit usually results in many wire cluttering. This may result in connection errors and

makes it difficult to understand, debug or modify the design. The solution to this problem

is to use terminals for connection. Figure 1.14 shows how to wire up the modulo-5 counter

using terminals. We can name the terminals in any fashion we liked but sensible names

make the schematic more legible and easy to understand. Essentially what we are doing


by labeling a terminal is making a connection to a terminal with the same name without

placing a physical wire between the two objects.

Figure 1.14 – Modified schematic of the modulo-5 counter using terminals for

connection.

The Power and Ground terminals are the special type of terminals. Although there is

no reason not to label them ; an unlabelled power terminal is assigned to the VCC net and

an unnamed ground terminal will be assigned to net GND.

You can insert a terminal into the drawing area by choosing Terminal Mode then selecting

DEFAULT from the Terminals list box as shown in Figure 1.15. You change the orientation

of the terminal using the rotate and mirror buttons from the left bar menu.

Figure 1.15 – Terminals selection.

To change the terminal name, double click on the terminal point and enter an appropriate

name in the "Edit Terminal Label Window" as shown Figure 1.16.


Figure 1.16 – Editing terminal label.

Exercise 1.5 Referring to Figure 1.14, modify your schematic for modulo-5 counter replacing direct

connections with terminals and labeling them appropriately.

Power Connections

ISIS supports a powerful scheme for making power connections implicitly, thus vastly re-

ducing the number of wires on the schematic. Almost all relevant components in ISIS have

their power pins hidden (not visible on the schematic). It is important to remember that in

such cases the name of the power and ground pins are set to VCC and GND by default.

To change these default values, you can use the component Properties Window as shown in

Figure 1.17.

Figure 1.17 – Edit power connections default.

Component Labels and Annotation

You should see that all the components you have placed have both a unique reference and a

value. The reference is set by a feature of ISIS called "Real Time Annotation" which can be

found on the Tools Menu and is enabled by default. Basically, when enabled, this feature

annotates components as you place them on the schematic, saving you the time and effort

of doing this manually.


You have full control over the position and visibility of component labels - you can

change the values, move the position or hide information that you feel is unnecessary. The

discussion below details how to manipulate component labels on a per component basis.

If you zoom in on any resistor you have placed you will see that ISIS has labeled it

with a unique Reference (e.g. R1) and also with a Value (e.g. 100). You can edit both

these fields and their visibility via the Edit Component dialogue form. You can launch this

dialogue form by double clicking the left mouse button over the resistor (or using one of the

alternative methods discussed previously). From the resulting dialogue form you can edit

both the component reference name and its value (in this case, the resistance). You can

also, show or hide these two properties as highlighted in Figure 1.18.

Figure 1.18 – Choose to hide or show references and values

Block Editing

ISIS editor allows you to copy, move, rotate or delete a group (block) of selected components.

This action is called block editing which can be performed by first drag a box around the

required group of components (e.g. devices and wires), and then applying the required

editing from Block Editing menu as shown in Figure 1.19.

Figure 1.19 – Block editing.

Simulating the Modulo-5 Counter

After completing the schematic editing of the modulo-5 counter, we can simulate design by

clicking on the Play button at the bottom of the Editing Widow as shown in Figure 1.20.

If there are no errors in your design, then you will notice that the LEDs are blinking


Figure 1.20 – Run simulation.

to reflect the modulo-5 count. You can check the Simulation Log by double clicking on

the Simulation Log Status to right of the simulation buttons as shown in Figure 1.21. The

Simulation Log window displays compilation status and errors.

Figure 1.21 – Simulation log.

For demonstration purpose, let’s change the power pin name from the default value VCC

to another name say "V" as illustrated in Figure 1.22.

Figure 1.22 – Change power pin default.

When we run the simulation again, the compiler displays an error on the Simulation Log

as shown in Figure 1.23.

Exercise 1.6 Referring to Figure 1.14, modify the design of the modulo-5 counter into modulo-3 counter

and simulate the resulting counter.


Figure 1.23 – Simulation errors.

2 — Introduction to Proteus VSM (Part II)

LAB Objectives

The this LAB experiment builds on the previous experiment to introduce more advance

topics in schematic editing and system simulation using using Proteus Virtual System

Modeling (VSM). The experiment is design to guide the students through the process

of designing, editing and simulating a frequency-divider circuit based on the modulo-n

counter designed in the previous experiment. The LAB covers more advance schematic

editing and simulation topics such as multiple design sheets and virtual instruments.

2.1 Design Example

In this experiment, we will design an odd frequency divider with 50% duty cycle. A frequency

divider, also called a clock divider, is a circuit that takes an input signal of a frequency,

fin, and generates an output signal of a frequency : fout = fin/n where n is an integer.

Figure 2.1 shows an example of the output of a frequency divider with fin = 8kHz and

n = 4. The duty cycle of a clock signal is the percentage of the time the signal is high in

one clock cycle. For example a clock signal with a 60% duty cycle is high during 60% of its

cycle and low for the remaining 40% as illustrated in Figure 2.2.

The frequency divider circuit that we are going to design will divide the input frequency

by 5 with a 50% duty cycle. This circuit will designed based on the modulo-5 binary counter

that we have implemented in the previous experiment.

18 Introduction to Proteus VSM (Part II)

fin = 8 kHz

fout = 2 kHz

Tin = 1/fin = 0.125 x 10-3

seconds

fout = fin/n = 8/4 = 2kHz, Tout = 1/fout = 0.5 x 10-3

seconds

Tin

Tout

Figure 2.1 – The output of a frequency divider with fin = 8kHz and n = 4.

T

60% 40%

Figure 2.2 – Example of a clock signal with 60% duty cycle.

2.2 Frequency Divider by 5 with a 50% Duty Cycle

Conceptually, the easiest way to create an odd frequency divider circuit with a 50% duty

cycle is to generate two reference clocks fx and fy at half the desired output frequency

(i.e. fx = fy = fin/2) with a constant 90 deg phase difference between the two reference

clocks. You can then generate the output frequency by exclusive-ORing the two waveforms

together. Because of the constant 90 deg phase offset, only one transition occurs at a time

on the input of the exclusive-OR gate, effectively eliminating any glitches on the output

waveform.

The two reference clocks with 90 deg phase difference can be generated with the help

of a modulo-n counter. The first reference clock fx is set high with the rising edge of the

clock whenever the count equals 0, whereas the second reference clock fy is set high with

the falling edge of the clock whenever the count equals ⌈n/2⌉. As an example, consider the

timing diagram of a frequency divider by 5 shown in Figure 2.3. The first reference clock fx

is set high with the rising edge of the clock on count equals 0. On the other hand, the second

reference clock fy is set high with falling edge of the clock on count equals ⌈5/2⌉ = 3.

In order to create an odd frequency divider (e.g. divide by 3, 5, 7, . . . , etc.) with a 50%

duty cycle using the previously described approach, we can apply the follow procedure (See

Figure 2.4) :

1. Create a modulo-n counter that counts from 0 to (n−1), where n is the natural number

by which the input reference clock is supposed to be divided (n is an odd number).

2. Take two JK flip-flops, x and y, and connect their inputs as follows :

(a) Jx = Kx = (Count == 0)

(b) Jy = Ky = (Count == ⌈n/2⌉)


fin

0 1 2 3 4 0 1 2 3 4

fout

fx

fy

Figure 2.3 – Timing diagram of a frequency divider by 5 with 50% duty cycle.

3. Connect the clock inputs of the two flip-flops as follows :

(a) CLKx = fin

(b) CLKy = fin

4. Exclusive-OR the outputs of the two flip-flops (fx and fy) to generate the output

frequency (i.e. fout = fx ⊕ fy).

CLK5

Q01

Q12

Q23

Q34

MOD_5_COUNTER

MOD5CNTR

J3

Q5

CLK1

K2

Q6

S4

X74LS113

J3

Q5

CLK1

K2

Q6

S4

Y74LS113

VCC

Fin

1 2

NOT

74LS04

1

2

13

12

NOR3

74LS27

1

2

3

AND2

74LS08

1

2

3

XOR2

74LS386

Fout

Figure 2.4 – Frequency divider by 5 with 50% duty cycle.

Exercise 2.1 Show how to design a frequency divider by 3 with 50% duty cycle using modulo-3 binary

counter and two JK flip-flops. Repeat the exercise for frequency divider by 4, 6 and 7.

2.3 Schematic Entry of the Frequency Divider Circuit

In this section, we will design the frequency divider by 5 with 50% duty cycle. It is common in

larger designs to split the schematic into multiple sheets. This serves both to reduce clutter

on the schematic and also to organize the design into logical blocks. ISIS fully supports this


methodology and we have arranged our tutorial design into two sheets in order to cover the

relevant procedures. The work we have done so far to design the modulo-5 counter has been

to complete the first sheet. The second part of our design (i.e. designing the logic for the

two reference clocks) will be done on a separate sheet.

Adding Sheets to a Design

To add a new sheet to the schematic we simply invoke the command from the Design menu


Figure 2.5 – Add new design sheet

Next we will enter the reference clocks circuit shown in Figure 2.6 into the new design

sheet. Note that in order to connect two terminals in two separate design sheets, you need

to assign the same name to both terminals.

Figure 2.6 – Schematic of the reference clocks.


Circuit Analysis using Virtual Instruments

In this experiment, we need to use an oscilloscope device to compare the input and output

frequencies of the frequency divider circuit. To insert an oscilloscope choose Virtual Mode

then select OSCILLOSCOPE from Instruments List Box as shown in Figure 2.7.

Figure 2.7 – Inserting an oscilloscope.

Now, we run the simulation and observe the input and output frequencies on the os-

cilloscope as shown in Figure 2.8. If the oscilloscope window does not pop-up when you

run the simulation, then you need to open it manually by right clicking on the oscilloscope

component and then select "Digital Oscilloscope".

Figure 2.8 – Comparing the input and output frequencies of the frequency

divider using the oscilloscope.

We will refer to Figure 2.9 to illustrate the usage of the oscilloscope. This oscilloscope

consists of three main parts : (1) input channels, (2) display scree and (3) control panels.


Figure 2.9 – Illustrating different parts of the oscilloscope.

The considered oscilloscope has four input channels labeled A, B, C and D as shown in

Figure 2.6. You can trace a given signal by connecting its terminal (or wire) to one of the

four channels.

The trace signals connected to the input channels of the oscilloscope will be displayed

on the screen. The x-axis of the screen represents time, while the y-axis represents voltage.

The control panels consist of a trigger control, horizontal control and channel control

(one for each channel).

The trigger control panel, as illustrated in Figure 2.10, provides the user with the follo-

wing control functions :

– Change the position the horizontal reference line.

– Specify signal display type : analog (AC) or digital (DC).

– Complement the input signals display.

– Enable/disable continuous tracing of input signals.

– Enable/disable one-shot tracing of input signals. This option works for periodical

signals only, and it will freeze the display so the user can perform any required analysis

for the input signal.

– Enable/disable cursors. When this control is enabled, a cursor can be inserted by

clicking on any place on the display screen. When a cursor is inserted it will display

the time measure between the vertical reference line and the inserted cursor.

– Focus the display by selecting the main source of input channels. This is useful when

displaying signals with large difference in their frequencies which my distort the display.

The horizontal control panel, as illustrated in Figure 2.11, provides the user with the

following control functions :

– Change the position of the signal trace on the x-axis.


Change signal display from analog to digital and vise versa

Complement signal

Enable/disable continuous tracing of input signals

Enable/disable one shot tracing of input signals (for periodical signals)

Enable/disable cursors

Select main input channel

Position the horizontal reference line

Figure 2.10 – Trigger panel functions.

– Change time division scale which allows the user to zoom-in or zoom-out on the x-axis.

Change the position of the signal trace on the x-axis

Change time division scale

Figure 2.11 – Horizontal panel functions.

The channel control panel, as illustrated in Figure 2.12, provides the user with the

following control functions for the specified channel (A, B, C or D) :

– Change the position of the signal trace on the y-axis

– Change the type of signal display : analog (AC), digital (CD), ground (GND) or turn

the signal off (OFF).

– Complement the signal trace.

– Combine two signals (A + B or C + D) in one signal trace by adding their amplitudes.

– Change voltage division scale which allows the user to zoom-in or zoom-out on the

y-axis.

Exercise 2.2 Referring to Figure 2.6, complete the reference clocks circuit on the new design sheet, run

the simulation and with the help of your instructor learn how to utilize the oscilloscope to compare the

input and output frequencies.


Change the position of the signal trace on the y-axis

Change the type of signal display

Complement the signal trace

Add two signals

Change voltage division scale

Figure 2.12 – Channel panel functions.

3 — Clock Generator 8284A

Objectives

1. Discuss the pin configurations and operations of the 8284A clock generator.

2. Start the first phase of designing a single-board 8086-based microcomputer system.

This phase involves making the basic connections of the 8086 microprocessor in mi-

nimum mode and interfacing the 8284A clock generator.

3.1 Pin Functions of the 8284A Clock Generator

The 8284A is an integrated circuit designed specifically for use with the 8086/8088 micro-

processors. This circuit provides the following basic functions or signals : clock generation,

RESET synchronization, and READY synchronization.

Figure 3.1 illustrates the pin-out of the 8284A clock generator. The functions of these

pins are briefly discussed in next paragraphs (refer to the 8284A data sheet for more details).

AEN1 and AEN2

Address Enable (AEN) is an active LOW signal serves to qualify its respective bus Ready

Signal (RDY 1 or RDY 2). AEN1 validates RDY 1 while AEN2 validates RDY 2. The two

AEN signal inputs are useful in system configurations which permit the processor to access

two multi-master system busses. In non-multi-master configurations, the AEN signal inputs

are tied true (LOW).

26 Clock Generator 8284A

8284A

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

CYNC

PCLK

AEN1

RDY1

READY

RDY2

AEN2

CLK

GND

VCC

X1

X2

ASYNC

EFI

F/C

OSC

RES

RESET

Figure 3.1 – 8284A pin diagram.

RDY1 and RDY2

Bus Ready (Transfer Complete) RDY is an active HIGH signal which is an indication from

a device located on the system data bus that data has been received, or is available RDY 1

is qualified by AEN1 while RDY 2 is qualified by AEN2.

ASYNC

Ready Synchronization Select (ASY NC) is an active LOW input which defines the synchro-

nization mode of the READY logic. When ASY NC is LOW, two stages of READY syn-

chronization are provided. When ASY NC is left open or HIGH, a single stage of READY

synchronization is provided.

READY

READY is an active HIGH output signal which is the synchronized RDY signal input.

READY is cleared after the guaranteed hold time to the processor has been met.

X1 and X2

Crystal Inputs (X1 and X2) are the pins to which a crystal is attached. The crystal frequency

is 3 times the desired processor clock frequency. Note that if the crystal inputs are not used

X1 must be tied to V CC or GND and X2 should be left open.

F/C

Frequency/Crystal Select (F/C) is an input used as a strapping option. When strapped

LOW, F/C permits the processor’s clock to be generated by the crystal. When F/C is

strapped HIGH, CLK is generated for the EFI input.

EFI

External Frequency Input (EFI) is strapped HIGH, CLK is generated from the input

frequency appearing on this pin. The input signal is a square wave 3 times the frequency

of the desired CLK output.Frequency/Crystal Select (F/C) is an input used as a strapping

3.2 Operations of the 8284A Clock Generator 27

option. When strapped LOW, F/C permits the processor’s clock to be generated by the

crystal. When F/C is strapped HIGH, CLK is generated for the EFI input.

CLK

Processor Clock (CLK) is the clock output used by the processor and all devices which

directly connect to the processor’s local bus. CLK has an output frequency which is 1/3 of

the crystal or EFI input frequency and a 1/3 duty cycle.

PCLK

Peripheral Clock (PCLK) is a peripheral clock signal whose output frequency is 1/2 that

of CLK and has a 50% duty cycle.

OSC

Oscilloscope Clock (OSC) is the output of the internal oscillator circuitry. Its frequency is

equal to that of the crystal.

RES

Reset Input (RES) is an active LOW input signal which is used to generate RESET . The

82C84A provides a schmitt trigger input so that an RC connection can be used to establish

the power-up reset of proper duration.

RESET

RESET is an active HIGH output signal which is used to reset the 80x86 family processors.

Its timing characteristics are determined by RES.

CSYNC

Clock Synchronization (CSY NC) is an active HIGH input signal which allows multiple

8284A chips to be synchronized to provide clocks that are in phase. When CSY NC is

HIGH the internal counters are reset. When CSY NC goes LOW the internal counters are

allowed to resume counting. CSY NC needs to be externally synchronized to EFI. When

using the internal oscillator CSY NC should be hardwired to ground.

VCC and GND

Power (VCC) and Ground (GND) input pins. A 0.1µF capacitor between V CC and GND

is recommended for decoupling.

3.2 Operations of the 8284A Clock Generator

The 8284A clock generator has three main functions : (1) clock generator, (2) RESET logic,

and (3) READY synchronization.


Clock Generator

The 8284A can derive its basic operating frequency from one of two sources : (1) an external

frequency source connected to the EFI pin, and (2) a quartz crystal connected to X1 and

X2. The control input F/C is used to select one of these sources. The crystal frequency

should be selected at three times the required CPU clock. The 8284A generates three clock

signals : OSC, CLK and PCLK. The OSC has the same frequency as the crystal (or the

external frequency) and can be used to test the clock generator or as and external frequency

input to other 8284A chips. The CLK is 1/3 the frequency of the crystal (or the external

frequency) with a 33% duty cycle designed to drive the 8086 processor directly. The PCLK

is a peripheral clock signal whose output frequency is 1/2 that of the CLK with 50% duty

cycle.

RESET Logic

The 8284A generates an active HIGH signal (RESET ) which is used to reset the 8086

microprocessor. This signal must be held high for at least 50µs in order to guarantee a

correct reset of the microprocessor. This requirement can be achieved using a simple RC

circuit as will be explained later in this experiment.

READY Synchronization

The READY signal is used by slow devices (memory or I/O peripherals) to request the

processor to extend the bus cycle to allow these device to finish reading/writing from/to

the bus. The 8284A generates a READY signal that is synchronized with the CPU clock.

For this project, READY synchronization is not required.

3.3 Schematic Entry of the 8284A Clock Generator

In this section, we will start building the first phase of our 8086-based microcomputer

system. This phase involves two main tasks : (1) connect the 8284A to generate the required

clock signal and reset logic for the 8086 microprocessor, and (2) make the basic connections

of the 8086 microprocessor necessary to run the 8086 in minimum mode. The first task

will be accomplished in this experiment, while the second part will be deviated to the next

experiment.

Interfacing the Crystal Circuit to the 8284A

Start the ISIS schematic editor and place the following components on to the Editing Win-

dow :

– 8284A (clock generator)

– Crystal (dummy crystal)

– MINRES510R (two 510Ω resistors)

Connect the components as shown in Figure 3.2 and set the frequency of the crystal to

15KHz. Note that this frequency is just for simulation purposes (in real implementation a

crystal of 15MHz is used).


Figure 3.2 – Crystal interface to the 8284A clock generator.

Save your design as "8284A_StudentID.DSN", where "StudentID" is your academic ID.

Exercise 3.1 Run the simulation and determine the frequency and duty cycle of the three clock outputs :

OSC, CLK and P CLK

Interfacing the Reset Circuit to the 8284A

On the same design sheet place the following components and connect them as shown in

Figure 3.3 :

– BUTTON (SPST Push Button)

– RESISTOR (Analog resistor primitive)

– CAPACITOR (Capacitor primitive)

– 1N4001 (Silicon Rectifier, Maximum Recurrent Peak Reverse Voltage 50V , Maximum

Average Forward Rectifier Current 1.0A)

Figure 3.3 – Reset circuit of the 8284A clock generator.


Edit the properties of the capacitor and change the capacitance value to 10µF and the

initial conditions to IC = 0V as shown in Figure 3.4. Similarly, edit the properties of the

resistor and change the resistance value to 10KΩ.

Figure 3.4 – Setting properties of the capacitance in the reset circuit.

Calculating the Minimum Reset Time Mathematically

As indicated before, the RESET signal must be held high for at least 50µs in order to

guarantee a correct reset of the microprocessor. Equivalently, we should make sure that the

the time required for the RES signal to go from logic 0 to logic 1 on power-on (or after

pushing the reset button) is at least 50µs. This requirement can be achieved by using the

reset circuit discussed above with properly selected values for the resistor and capacitor.

The reset time is determined by the capacitor charging timing which can be calculated using

the following RC charging formula :

Vc = Vs(1 − exp−t/RC) (3.1)

Where,

– Vc is the voltage across the capacitor,

– Vs is the supply voltage,

– t is the elapsed time since the application Vs, and

– RC is the time constant of the RC charging circuit .

Exercise 3.2 Using the RC charging formula, calculate the duration of the reset signal assuming that

the minimum high voltage of the 8284A is 2.5V (i.e. Vc = 2.5V ) .

Measuring the Minimum Reset Time Using Analog Analysis

In this part of the experiment, we will measure the minimum reset time (i.e. the charging

time of the capacitor) using analog analysis.

Choose the Graph Mode and then select ANALOG analysis from the list box and place

it on the Editing Window as shown in Figure 3.5.

Choose the Voltage Probe Mode and then select ANALOG probe from the list box and

connect it to the output of the reset circuit as shown in Figure 3.6. Note that in order to

perform the analog analysis, you need to disconnect the line from the RES of the 8284A.


Figure 3.5 – Inserting an analog analysis window.

Figure 3.6 – Inserting analog voltage probe.


Double click the title-bar of the Analog Analysis Window to open the Prospice Window

as shown in Figure 3.7. Click on the "Add Trace" button and then select the voltage probe

signal Vc as illustrated in the figure.

Figure 3.7 – Inserting a trace signal into Prospice window.

Click on the "Edit Graph" button to open the Edit Transient Graph Window as shown

in Figure 3.8. Modify "stop time" to 200ms and uncheck the "initial DC solution" box as

illustrated in the figure.

To complete the analog analysis click on the "Simulate Graph" button as shown in

Figure 3.9. The analog analysis simulation shows that the capacitor charge will reach 2.5V

after 69.5ms as illustrated in the figure.

Exercise 3.3 Compare the minimum reset time calculated in Exercise 3.2 with the minimum reset time

measured using analog analysis.

Clock and Reset Terminals

The final step in schematic entry of the 8284A is to add two terminals to the schematic :

CLK and RESET as shown in Figure 3.10. The purpose of these terminals is allow the

clock signal and reset logic to be connected to the 8086 design sheet which will be added to

our project in the next LAB experiment.


Figure 3.8 – Edit transient graph.

Figure 3.9 – Analog analysis simulation.


Figure 3.10 – Adding CLK and RESET terminals to the 8284A schematic.

4 — 8086 Basic Connections

Objectives

1. Discuss the minimum mode pin configurations of the 8086 microprocessor.

2. Continue the first phase of designing a single-board 8086-based microcomputer sys-

tem by making the basic connections of the 8086 microprocessor in minimum mode.

4.1 Pin Functions of the 8086 Microprocessor (Minimum Mode)

Figure 4.1 illustrates the pin-out of the 8086 microprocessor. The 8086 is a 16-bit micropro-

cessor with a 16-bit data bus. As shown in the pin-out, The 8086 uses time multiplexing for

the address lines, data lines, and some status and control lines (i.e. AD0-AD15, A19/S6-

A16/S3, and BHE/S7 ).

Next we briefly explain the function, and in some cases the multiple functions, of each

of the 8086 microprocessor’s pins when operated in minimum.

AD15-AD0

Address/Data Lines (AD15-AD0) are input/output lines constituting the time multiplexed

memory/IO address lines (during bus cycle T1), and data lines (during bus cycle T2, T3,

TW , and T4).

A19/S6-A16/S3

Address/Status Lines (A19/S6-A16/S3) are output lines constituting address and status

lines. During T1, they provide the four most significant address lines for memory operations.

36 8086 Basic Connections

1

2

3

4

5

6

7

8

9

40

39

38

37

36

35

34

33

32

GND

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

VCC

AD15

A16/S3

A17/S4

A18/S5

A19/S6

BHE/S7

MN/MX

RD

10AD6

11

12

13

14

15

16

17

18

19

AD5

AD4

AD3

AD2

AD1

AD0

NMI

INTR

CLK

20GND

31

30

29

28

27

26

25

24

23

HOLDA

WR

M/IO

DT/R

DEN

ALE

INTA

TEST

22 READY

21 RESET

8086HOLD

Figure 4.1 – 8086 pin diagram.

4.1 Pin Functions of the 8086 Microprocessor (Minimum Mode) 37

During I/O operations these lines are LOW. During memory and I/O operations, status

information is available on these lines during T2, T3, TW and T4.

BHE/S7

Bus High Enable/Status (BHE/S7) is an output signal that is used together with A0 during

T1 to enable even byte D7-D0 alone, odd byte D15-D8 alone or both as shown in Table 4.1.

The S7 status information is available during T2, T3, and T4.

Table 4.1 – Byte selection in 8086

BHE A0 Byte(s) Selected

0 0 Both bytes (D15-D0

0 1 Odd byte (D15-D8)

1 0 Even byte (D7-D0)

1 1 None

RD

Read Strobe (RD) is an active LOW output signal which indicates that the processor is

performing a memory or I/O read cycle.

READY

READY is an input signal representing the acknowledgment from the addressed memory or

I/O device that it will complete the data transfer. This input is controlled to insert WAIT

states into the timing of the microprocessor. If the READY pin is placed at a logic 0, the

microprocessor enters into WAIT states and remains idle. If the READY pin is placed at a

logic 1, it has no effect on the operation of the microprocessor.

The READY signal from memory/IO is synchronized by the 8284A clock generator which

will be discussed in the next section.

INTR

Interrupt Request (INTR) is a level triggered input signal used to request a hardware

interrupt. It is sampled during the last clock cycle of each instruction to determine if the

processor should enter into an interrupt acknowledge operation. If INTR is held high when

IF = 1, the 8086 enters an interrupt acknowledge cycle (INTA becomes active) after the

current instruction has completed execution.

TEST

TEST input is examined by the "Wait" instruction. If the TEST input is LOW execution

continues, otherwise the processor waits in an "Idle" state. This pin is most often connected

to the 8087 numeric coprocessor.


NMI

Non-Maskable Interrupt NMI is an input signal similar to INTR except that the NMI

interrupt does not check to see if the IF flag bit is a logic 1.

RESET

RESET is an input signal that causes the processor to immediately terminate its present

activity and restart. The signal must become a logic 1 no later than four clocks after system

power is applied and to be held high for at least 50µs.

CLK

Clock (CLK) is an input signal that provides the basic timing signal to the microprocessor.

The clock signal must have a duty cycle of 33% (high for one-third of the clocking period

and low for two-thirds) to provide proper internal timing for the 8086.

MN/MX

Minimum/Maximum mode (MN/MX) input pin selects either minimum mode or maximum

mode operation for the microprocessor. If minimum mode is selected, the MN/MX pin must

be connected directly to +5.0V .

M/IO

Memory/IO (M/IO) is an output signal used to distinguish a memory access from an I/O

access.

WR

Write (WR) is an active LOW output signal used to indicate that the processor is performing

a write memory or write I/O cycle, depending on the state of the M/IO signal.

INTA

Interrupt Acknowledge (INTA) is an active LOW output signal which is generated as a

response to the INTR input pin.

ALE

Address Latch Enable is an output signal used to indicate that the 8086 address/data bus

contains address information. This address can be a memory address or an I/O port number.

DT/R

Data Transmit/Receive (DT/R) is an output signal used to indicate that the microprocessor

data bus is transmitting (DT/R = 1) or receiving (DT/R = 0) data. This signal is used to

enable external data bus buffers.

4.2 Basic Connections of the 8086 Microprocessor (Minimum Mode) 39

DEN

Data Bus Enable (DEN) is an active low output signal which can be used to activate

external data bus buffers.

HOLD

HOLD is an active HIGH input signal used to request a direct memory access (DMA). If

the HOLD signal is a logic 1, the microprocessor stops executing software and places its

address, data, and control bus at the high-impedance state. If the HOLD pin is a logic 0,

the microprocessor executes software normally.

HLDA

Hold Acknowledge (HLDA) is an active HIGH signal used to indicate that the 8086 micro-

processors have entered the hold state.

4.2 Basic Connections of the 8086 Microprocessor (Minimum Mode)

The the basic connections of the 8086 processor required for minimum mode operation are

shown in Figure 4.2. Notice that the RESET pin is connected to GND and the CLK pin is

left unconnected. In the final design, these two pins will be connected to the corresponding

pins in the 8284A. However, for the time being will leave them connected this way because

the simulation model of the 8086 provides an internal clock as will as an internal memory.

This allows us to test our design in every phase of the project without the need to interface

the 8086 microprocessor to any peripheral device such as the 8284A clock generator or

memory modules.

Figure 4.2 – Basic connections of the 8086 microprocessor (minimum mode).

Start a new design project and place the 8086 microprocessor component on the Editing

Window. Then, make the basic wiring of the 8086 microprocessor as shown in Figure 4.2.


Exercise 4.1 Refer to the pin functions of the 8086 microprocessor described in Section 4.1 and the

basic connections given in Figure 4.2. Then, complete Table 4.2 indicating what is connected to each

one of the listed pins (GND or V CC) and the justification of the these connections.

Table 4.2 – Basic connections of the 8086 microprocessor (minimum mode)

.

8086 Pin Connection Justification

READY V CC The microcomputer system to be designed is a simple one

that does not require using ready logic to request extra

extra bus cycles. Therefore, this pin is placed is placed

at logic 1, so that it has no effect on the operation of

the microprocessor.

INT R

HOLD

T EST

NMI

MN/MX

4.3 Testing the 8086 Microprocessor

In this section, we will test our 8086 microprocessor using the following procedure :

1. Write a very simple assembly code.

2. Compile and link the assembly code to generate the executable file.

3. Load the executable file into the internal memory of the 8086 simulation model.

4. Run the simulation model of the 8086.

5. Monitor the execution of the loaded code by applying DC Analysis on certain pins of

the 8086 microprocessor.

A Simple Test Program

In this part, we will write an assembly code that will continuously outputs an 8-bit binary

count on port 22H. Using a text editor type the assembly code shown in Program 4.1 and

save it as "counter.asm".

Program 4.1 A Simple Test Program

01 ; assembly code to generate an 8-bit binary counter on port 22h.

02 .MODEL SMALL

03 .8086

04 .STACK

05 .CODE

06 .STARTUP

07 MOV AL, 0

08 COUNTER_LOOP:

09 OUT 22H, AL

10 INC AL

11 JMP COUNTER_LOOP

12 .DATA

13 END


Compiling An Assembly Code for the 8086 Simulation Model

In order to load assembly code into the internal memory of the 8086 simulation model, it

must be compiled to generate programs in ’.BIN’, ’.COM’ and ’.EXE’ formats without the

standard Run-Time Libraries (RTL). This is because programs will be running on the 8086

model without the presence of an IBM PC BIOS or MS-DOS.

In this project, we will use the "MASM32" assembler (www.masm32.com) to compile

our assembly programs. The following commands will be used to generate ’.EXE’ format

without RTL :

ml /c /Zd /Zi program_name.asm

link16 /CODEVIEW program_name.obj, program_name.exe,,, nul.def

Note that the "program_name.asm" file should reside in the "bin" directory of the

"MASM32" assembler, otherwise the full path of assembly file should be specified in the

above commands.

Exercise 4.2 Compile the assembly code in Program 4.1 which you have edited as "counter.asm" to

generate the executable file "counter.exe".

Loading An Executable Code into the 8086 Simulation Model

To load the executable file into the internal memory of the 8086 model, double click on the

8086 component to open its properties as shown in Figure 4.3. Edit the properties of the

model as follows :

1. From "Program File" navigation box, search for your executable file and load it into

the internal memory of the 8086 model.

2. From "Advanced Properties" drop list box, select "Internal Memory Size" and change

the memory size to any value of your choice (say 100).

3. click "OK" button to save your settings.

Figure 4.3 – Load program into internal memory of the 8086 model.


Digital Analysis of the 8086 Signals

If we run the simulation at this stage, the 8086 model will emulate the execution of the

loaded program as in a real microprocessor. Since our microcomputer systems is not yet

complete, we will use digital analysis to verify the correctness of our design.

We will start by adding voltage probes to the following output control pins of the 8086

model (See Figure 4.4) :

– Address Latch Enable (ALE)

– Read (RD)

– Write (WR)

– Memory/IO (M/IO)

Figure 4.4 – Adding voltage probes to control pins of the 8086 model.

Next, we add voltage probes to the least significant address/data bus lines AD0 − AD7

as follows :

1. Choose Terminal Mode and then select BUS from Terminals List Box as shown in

Figure 4.5.

2. Place the BUS terminal on the Edit Window and then connect it to the address/data

lines AD[0..15] of the 8086 model as shown in Figure.

3. Double click the BUS terminal to open its properties and enter AD[0..15] into the

label text box as shown in Figure 4.7.

4. Add 8 terminals labeled (AD0, AD1, . . . , AD7) and connect them to voltage probes


Finally, we add a Digital Analysis Window as shown in Figure 4.9. The Digital Analysis

Window is identical to the Analog Analysis Window which we have used in the previous

experiment. The only difference between the two windows is the type of signals they can

handle (i.e. digital or analog signals).


Figure 4.5 – Select bus terminal.

Figure 4.6 – Connecting a bus terminal to the address/data lines of the 8086

model.

Figure 4.7 – Editing the bus terminal label.


Figure 4.8 – Adding terminals and voltage probes for address/data lines AD0 −

AD7.

Figure 4.9 – Adding a digital analysis window.


Exercise 4.3 Following the the procedure used in Experiment 3 to set the Analog Analysis Window,

perform the following step :

– Add all voltage probes shown in Figure 4.8 to the Digital Analysis Window.

– Set "stop time" to 1ms.

– Leave the "initial DC solution" box checked.

– Run the simulation.

After completing Exercise 4.3 you should get the signal trace shown in Figure 4.10. The

active regions of this trace correspond to the bus cycles of one instruction from our program

which is the I/O instruction "OUT 22H, AL" as it is the only one accessing the data bus.

On the other hand, floating (inactive) regions in the trace correspond to other instructions

which are internal to the 8086 model and do not affect the control signals or the data bus.

Figure 4.10 – Digital analysis trace

Figure 4.11 shows 4 bus cycles corresponding to the I/O instruction. As illustrated in

this figure, the control signals behave as follows :

– ALE is active in T1 of each bus cycle.

– RD is always floating as the instruction is not reading data from the bus.

– WR is active LOW from T2 to T4 as the instruction is writing data to the bus.

– M/IO is always active LOW as the instruction is accessing an IO port rather than a

memory.

Also, it is clear from the figure that the address/data lines (AD7−AD0) are behaving as

expected. During T1 they carry the address of the port which is 22H = 0010_0010 (shown

in blue). In T2 and T3, they carry data which is 8-bit binary count (shown in green). For

the rest of T4 these lines are floating or high-impedance (shown in red).


T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

CLK

ALE

RD

WR

M/IO

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

Bus Cycle Bus Cycle Bus Cycle Bus Cycle

0

1

0

0

0

1

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

0

0

00

1

0

0

0

1

0

0

address data float address data float data floataddress data floataddress

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

0

0

0

0

Figure 4.11 – Illustration of 4 bus cycles corresponding to the I/O instruction.

5 — Designing the Bus System

Objectives

The aim of this LAB experiment is to design the second phase of our microcomputer

system by interfacing the 8086 to a fully-demultiplexed and buffered bus system.

5.1 Bus Buffering and Latching

Before the 8086 microprocessor can be used with memory or I/O interfaces, it time multi-

plexed address/data and address/status lines must be demultiplexed. Another requirement

is to buffer these lines to allow driving other components in the system. Note that, the maxi-

mum fan-out of any 8086 pin is 10. Therefore, the system must be buffered if it contains

more than 10 other components.

This section provides the detail required to demultiplex the buses and illustrates how

the buses are buffered for very large systems.

Bus Demultiplexing

The 8086 microprocessor has 16 data lines and 20 address lines. The 8086 uses time mul-

tiplexing for the address, data, and some status lines. The 8086 generates the addresses

A0 − A15 on lines AD0 − AD15 and A16 − A19 on lines A19/S6 − A16/S3 during T1. This

event is indicated by a bus control signal ALE. During T2, T3, and T4 the microprocessor

uses the AD0 − AD15 to transfer data (i.e. as data bus).

Demultiplexing of the AD lines requires latching of the addresses by using some inte-

grated latches such as the 74LS373 octal latch. The latched addresses will then be used as

address bus during clock cycles T2, T3, and T4.

48 Designing the Bus System

The 74LS373 octal latch (refer to the data sheet in the Appendix) is a simple level-

triggered D flip-flops with two control lines : Output Control (OC) and Latch Enable (G).

As long as the Latch Enable (G) is high, the outputs of the D flip-flops follow their inputs.

When G goes low, the flip-flops latch (save) the input signals. The Output Control line (OC)

can be used to place the eight latches in either a normal logic state (HIGH or LOW logic

levels), or a high-impedance state.

Figure 5.1 illustrates the 8086 microprocessor and the components required to demulti-

plex its buses. In this case, three 74LS373 transparent latches are used to demultiplex the

address/data lines AD15 − AD0, address/status lines A19/S6 − A16/S3 and BHE/S7.

These transparent latches become transparent whenever the Address Latch Enable signal

(ALE) becomes a logic 1, passing the inputs to the outputs. After a short time, ALE re-

turns to its logic 0 condition, which causes the latches to latch (save) the inputs at the time

of the change to a logic 0. In this case, the A19 − A0 and BHE are stored in the three

latches yield a separate address bus. These address connections allow the 8086 to address

1M byte of memory space.

Figure 5.1 – 8086 fully demultiplexed bus.

Exercise 5.1 Complete the design of the 8086-based microcomputer system form previous experiment

by including the fully-demultiplexed bus system shown in Figure 5.1.


Bus Buffering

If more than 10 components are attached to any bus pin, then the entire 8086 system must

be buffered. The demultiplexed pins (i.e. address bus A19 − A0 and BHE) are already

buffered by the 74LS373 latches. Thus, we need to buffer the data bus D15 − D0 and the

three control bus signals M/IO, RD and WR.

Since the data bus is bi-directional, we need to use bi-directional 3-state buffers such as

the 74LS245 Tri-State Octal Bus Transceiver. On the other hand, the control bus signals

are uni-directional signals (i.e. originating from the CPU to the peripheral devices). Hence,

we need to use uni-directional buffers such as the 74LS244 Octal Buffer.

The 74LS245 octal buffer (refer to the data sheet in the Appendix) is a bi-directional

bus transceiver. The device allows data transmission from the A bus to the B bus or from

the B bus to the A bus depending upon the logic level at the direction control (DIR) input.

The enable input (G) can be used to disable the device so that the buses are effectively

isolated (i.e. on high-impedance state).

The 74lS244 octal buffer (refer to the data sheet in the Appendix) is a uni-directional

buffer. The device allows data transmission from the A bus to the Y . The enable inputs

(1G and 2G) can be used to disable the device so that the buses are effectively isolated (i.e.

on high-impedance state).

The fully buffered bus system, as shown in Figure 5.2, uses two types of buffers : 74LS245

and 74LS244. The 74LS245 buffers are used to buffer the data bus D15−D0. These buffers

are controlled by two control signals form the 8086 : (1) DT/R which controls the direction

of the data flow, and (2) DEN which enable/disable the data bus.

Exercise 5.2 Complete the design of the 8086-based microcomputer system form previous experiment

by including the fully-demultiplexed and buffered bus system shown in Figure 5.2.

5.2 Testing the Bus System

In this part of the experiment, we will test our bus system using digital analysis while the

8086 model is running very simple I/O read and write operations. For this purpose, we will

write two assembly programs and add few connections to our schematic in order to test

bus read and write cycles. Since our I/O system is not implemented yet, we can not test

the read and write operations at the same time. Therefore, we will test bus read and write

cycles using two different configurations as will be explained next.

Testing the Bus Read Cycle

Testing the bus read cycle involves the following steps :

1. Add a simple hard-coded input port as shown in Figure 5.3. This port will input the

value 9CH through low byte of the data bus D7 − D0.

2. Write an assembly code (see Program 5.1) to read one byte from I/O port address

72H. Note that you can use any even port number as the data will be read through

the even byte of the data bus. Also, note that the program ends with an infinite loop


Figure 5.2 – 8086 fully buffered bus.


because programs running on the 8086 model do not include DOS functions such as

the program termination function.



5. Add voltage probes to monitor address, data and control signals as shown in Figure 5.4.

Note that a reference clock of 5MHz need to be added because we have access to the

internal clock of the 8086 model.

6. Add a digital analysis window and include all signals to be monitored as shown in

Figure 5.5.

7. Run the digital analysis simulation.

Figure 5.3 – A simple hard-coded input port with a value of 9CH.

Program 5.1 A Simple I/O Read Program

01 ; assembly code to read one byte from port 72h.

02 .MODEL SMALL

03 .8086

04 .STACK

05 .CODE

06 .STARTUP

07 IN AL, 72H

08 ENDLESS_LOOP:

09 JMP ENDLESS_LOOP

12 .DATA

13 END

After completing your design according to the previous procedure, you should obtain

a timing diagram similar to the one shown in Figure 5.6. This timing diagram shows a

complete and correct bus read cycle which reads the value 9CH from port address 72H. The

behavior of each monitored signals in this diagram is explained as follows :

– The ALE signal is active in first clock cycle T1.


Figure 5.4 – Probes to monitor address, data and control signals during an 8086

bus read cycle.

Figure 5.5 – Digital analysis window for an 8086 bus read cycle.


– The DT/R is LOW during T1 − T4 to set the direction of the data flow from the I/O

device to the CPU.

– The DEN is set LOW during T2 − T4 to enable the data bus.

– The port address 72H is latched on the address lines A7 − A0 at the end of T1.

– The address/data lines AD7 − AD0 carry the address during T1, float during T2 and

carry the hard-coded input data 9CH during T3 − T4.

Figure 5.6 – Result of the digital analysis of an 8086 bus read cycle.

Testing the Bus Write Cycle

Testing the bus write cycle involves the following steps :

1. Delete the hard-coded input port which we used to test the bus read cycle.

2. Write an assembly code (see Program 5.2) to output one byte of value 9CH to I/O

port address 72H.



5. Replace voltage probes used to monitor address, data and control signals during the

testing of the bus read cycle with the ones shown in Figure 5.7.

6. Add a new digital analysis window and include all signals to be monitored.



Program 5.2 A Simple I/O Write Program

01 ; assembly code to output one byte of value 9Ch to port 72h.

02 .MODEL SMALL

03 .8086

04 .STACK

05 .CODE

06 .STARTUP

07 MOV AL, 9CH

07 OUT 72H, AL

08 ENDLESS_LOOP:

09 JMP ENDLESS_LOOP

12 .DATA

13 END

Figure 5.7 – Probes to monitor address, data and control signals during an 8086

bus write cycle.

After completing you design according to the previous procedure, you should obtain


complete bus write cycle which outputs the value 9CH to port address 72H. The behavior

of each monitored signals in this diagram is explained as follows :

– The ALE signal is active in first clock cycle T1.

– The DT/R is HIGH during T1 − T4 to set the direction of the data flow from the

CPU to the I/O device.

– The DEN is set LOW during T1 − T4 to enable the data bus. However, this behavior

is not correct as the DEN should be set LOW starting from T2 rather than T1. This

seems to be due to a bug in the 8086 which can be fixed using a simple logic similar

to the one shown in Figure 5.9.

– The port address 72H is latched on the address lines A7 − A0 at the end of T1.


– The data lines D7 − D0 should carry only the output data (i.e. 9CH) during T2 − T4,

and float during T1. However, due to the bug in the DEN signal, the diagram shows

that these lines carry the port address 72H during T1.

Figure 5.8 – Result of the digital analysis of an 8086 bus write cycle.

Exercise 5.3 Adjust your schematic design to fix the bug in the DEN signal by adding a new design

sheet that includes the logic in Figure 5.9. Run the digital analysis simulation and compare the results

with ones obtained before fixing the bug.


D2

Q5

CLK3

Q6

S4

R1

D_FLIP_FLOP

74LS74

OR

OR_2

DENin

DENout

AND

AND_2

DT/R

Clock Generator (5MHz)

Figure 5.9 – A simple logic to fix the bug in the DEN signal.

6 — Designing the Memory System

Objectives

The aim of this LAB experiment is to design the third phase of our microcomputer system

by interfacing the 8086 to a small memory system using SRAM and EPROM memory

chips.

6.1 8086 Memory Mapping

The 8086 microprocessor has 20-bit address lines (A19 − A0) capable of addressing 1MB.

This memory space can be accessed through 16-bit data lines (D15 − D0) during memory

read/write cycles.

Basically, ROM and RAM memory chips are byte organized. Therefore, the 8086 micro-

processor requires a memory module to be organized as two banks (each 8-bit wide) called

the even and odd banks. The ROM memory is used to store resident programs that must

run when the microprocessor system is powered on. The RAM memory is used to store

application programs that are ready to run as well as to provide some reserved locations

for the proper operations of interrupts. The designer must be careful with bank selection

especially when dealing with read/write memories. In this case, byte operations with one

bank must be done while enabling one of the memory banks and disabling the other.

6.2 Designing the Memory System

In this experiment, we will design a memory system consisting of two memory modules as

shown in Figure 6.1. The first module is a 16KB SRAM starting at address 00000H, whereas

58 Designing the Memory System

the second is a 16KB EPROM ending at address FFFFH. The EPROM module is mapped

specifically to this range in the memory space because, on reset, the 8086 microprocessor

begins executing instructions at location FFFF0H. This location is called the boot-strap

and typically contains a jump instruction that transfers execution to a location of the

ROM where a start-up program is stored. In our design, we will use two 6264 (8KB) SRAM

memory chips and two 2764 (8KB) EPROM memory chips. You can refer to the data sheets

of these two chips to familiarize yourself of their pin functions.

RAM

16KB

ROM

16KB

00000H

03FFFH

FC000H

FFFFFH

1MB

Figure 6.1 – Mapping of the ROM and RAM modules into the 8086 memory

space.

Exercise 6.1 Based on the design requirements of the memory system discussed above, answer the

following questions :

1. How to decode the RD, W R and M/IO signals to generate the following memory and I/O read

and write control signals : MEMR, MEMW , IOR and IOW ?

2. How to design the 32KB memory system using full address decoding ?

3. How to design the same memory system using partial address decoding ?

4. Which address decoding approach should we use for our design ? Why ?

5. Which of 8086 address lines are required to address the two modules ?

6. How to distinguish the even and odd banks of the SRAM module ?

7. Is it necessary to distinguish the even and odd banks of the EPROM module ? Why ?

Memory and IO Control Signals (Control Bus Decoder)

The 8086 microprocessor provides three control signals RD, WR and M/IO signals which

can be decoded as shown in Figure 6.2 to generate the required memory and I/O control

signals (i.e. MEMR, MEMW , IOR and IOW ).

Exercise 6.2 Open the bus system design built in Experiment 5 and create a new design sheet with

title "Control Bus Decoder". In the newly created design sheet, draw the schematic of the control bus

decoder shown in Figure 6.3.


RD

M/IO

WR

IOR

MEMR

MEMW

IOW

Figure 6.2 – Decoding memory and I/O read and write signals.

Figure 6.3 – Schematic of the control bus decoder.


Address Decoding

In this project, we will consider partial address decoding because our 8086-based micro-

computer system uses only a small part of the 1MB memory space. It is only necessary to

distinguish two memory modules (i.e. RAM and ROM), and hence, only one address line

is needed for address decoding. Figure 6.4 shows that the two modules differ in the 6 most

significant address lines A19−A14. Thus, we can use any one of these address lines to build

the address decoder (say A19). This decoder, as shown in Figure 6.5, is simply just a single

inverter.

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

RAM

ROM

Address

DecodingAddress

Lines

Figure 6.4 – Address decoding of the RAM and ROM memory modules.

A19

RAM_SELECT

ROM_SELECT

Figure 6.5 – Partial address decoder.

Memory Bank Selection

As you know the RAM module allows write operations that change content of the memory.

Thus, we need to make sure that a write operation will modify the correct memory location.

A proper selection of even and odd banks of the RAM module is an essential requirement

of the memory system design. The 8086 provides a special signal (BHE) that can be used

together with the address line A0 to enable the proper memory bank as shown in Table 6.1.

The logic necessary to select even and odd banks of the RAM module is shown in Figure 6.6.

Table 6.1 – Memory bank(s) selection in 8086

BHE A0 Bank(s) Selected

0 0 Both banks (D15 − D8 and D7 − D0

0 1 Odd bank (D15 − D8)

1 0 Even bank (D7 − D0)

1 1 None

The ROM module, on the other hand, does not require any logic to select the even/odd

banks. This is because the ROM module allows only read operations which are considered as

safe operations. Therefore, both the even and odd banks are enabled during a read operation


A19

A0

BHE

RAM_EVEN

RAM_ODD

Figure 6.6 – Logic to select even/odd banks of the RAM module.

and 8086 will select the required byte(s) from the data bus. An unneeded byte on the data

bus is simply ignored by the processor.

Connecting Address and Data Lines

The complete memory system design is shown in Figure 6.7. As indicated in our design

specifications, each one of memory modules (i.e. RAM and ROM) consists of two 8KB

memory chips. So, each memory chip requires 13 address lines (note that 8K = 23 × 210 =

213). As shown in Figure 6.4, the address lines A13−A1 are used to address each individual

memory bank and A0 is used together with BHE to select even/odd banks. The even bank

chips are connected to the even byte of the processor (D7 − D0), while odd bank chips are

connected to the odd byte (D15 − D8).

A19

A0

BHE

RAM_EVEN

RAM_ODD

8KB

RAM

IO7-IO0

A12-A

0

CS

8KB

RAM

IO7-IO0

A12-A

0

CS

8KB

ROM

IO7-IO0

A12-A

0

CS

8KB

ROM

IO7-IO0

A12-A

0

CS

OE

WE

OE

WE

OE OE

A13-A1

D7-D0 D7-D0D15-D8 D15-D8

MEMR

MEMW

A19ROM_SELECT

Figure 6.7 – The complete memory system design.

Exercise 6.3 Create a new design sheet with title "Memory System" and draw the schematic of the

memory system as shown in Figure 6.8.


Figure 6.8 – Schematic of the complete memory system design.


6.2.1 Testing the Memory System

In this part of the experiment, we will test our memory system using digital analysis while

the 8086 model is running very simple memory read and write operations. For this purpose,

we will write two assembly programs and add few connections to our schematic in order to

test memory read and write cycles. For simplicity, the RAM and ROM modules will be test

separately as will be explained in the two next subsections. However, testing both modules

require the same digital analysis configurations shown in Figure 6.9.

Figure 6.9 – Digital analysis configurations required for testing the memory

system.

Testing the RAM Module

Testing the RAM module involves the following steps :

1. Write an assembly code (see Program 6.1) to write one word to memory location at

address 0000 :0120 and read it back.





Program 6.1 A Simple Memory Read/Write Program

01 ; assembly code to write one word to memory location at address 0000:0120

02 ; and read it back.

03 .MODEL SMALL

04 .8086

05 .STACK

06 .CODE

07 .STARTUP

08 MOV AX, 0

09 MOV DS, AX

10 MOV BX, 0120H

11 MOV AX, 3B7CH

12 MOV [BX], AX

13 MOV AX, [BX]

14 ENDLESS_LOOP:

15 JMP ENDLESS_LOOP

16 .DATA

17 END

After completing your design according to the previous procedure, you should obtain


memory write cycle to the RAM module followed by a memory read cycle from the RAM

module. The behavior of each monitored signals in this diagram is explained as follows :

– The ALE signal is active in T1 in the memory write cycle as well as in the memory

read cycle.

– The M/IO signal is active HIGH in both bus cycles which indicates a memory access.

– The WR signal is active LOW in the first bus cycle which indicates a memory write

cycle.

– The RD signal is active LOW in the second bus cycle which indicates a memory read

cycle.

– The address 00120H is latched on the address lines A19 − A0 at the end of T1 of each

bus cycle.

– The data lines D15 − D0 carry the correct data word 3B7CH in both bus cycles.

Testing the ROM Module

Before starting the test procedure, we need to load some data into the EPROM chips.

This can be done easily using a text file formatted according to Intel HEX format. The

details of this hex format is out of the scope of this LAB manual. An interested reader can

refer to the following Wikipedia website (http ://en.wikipedia.org/wiki/Intel_HEX). In this

experiment, we will load data into the EPROM chips according to Table 6.2.

Data

Offset Address Even EPROM Odd EPROM

1710H ACH 7DH

1712H 36H EBH

Table 6.2 – Sample data to be loaded into EPROM chips.


Figure 6.10 – Result of the digital analysis of an 8086 a RAM read and write

cycles.


The following procedure can be used to load data into the EPROM chips :

1. Using any text editor, type the data shown below in Intel HEX format and save the

file as "rom_data.hex" in the same directory as your design file.

:04171000AC7D36EB8B

:00000001FF

2. Double click the even EPROM chip to open its properties window and edit the follo-

wing properties as shown in Figure 6.11 :

– In Image File text box type the name of the data file "rom_data.hex".

– In File Base Address text box type the value 0. Note that this property is used to

re-map the addresses in the file in order to achieve byte splitting between even and

odd chips. Setting this property to 0 assigns even bytes (i.e. bytes 0, 2, . . . , etc.) to

this chip.

– In File Address Shift text box type the value 1. Note that this property is used

to shift the addresses in the file by a certain number of bits. In the case of 8086

microprocessor, the address is shifted by 1 bit because A0 is used to distinguish

even and odd banks and not used as part of the address lines connected to the

memory chip.

– Click OK button to save these setting.

3. Double click the odd EPROM chip to open its properties window and edit the following

properties :

– In Image File text box type the name of the data file "rom_data.hex".

– In File Base Address text box type the value 1. Setting this property to 1 assigns

odd bytes (i.e. bytes 1, 3, . . . , etc.) to this chip.

– In File Address Shift text box type the value 1.

– Click OK button to save these setting.

Testing the ROM module involves the following steps :

1. Write an assembly code (see Program 6.2) to read two words from the following me-

mory addresses : FC00 :1710 and FC00 :1712.




After completing your design according to the previous procedure, you should obtain a

timing diagram similar to the one shown in Figure 6.12. This timing diagram shows two

memory read cycles from the ROM module. The behavior of each monitored signals in this

diagram is explained as follows :

– The ALE signal is active in T1 in both memory read cycles.

– The M/IO signal is active HIGH in both bus cycles which indicates a memory access.

– The RD signal is active LOW in both bus cycle which indicates two memory read

cycles.


Figure 6.11 – Editing the properties of the even EPROM chip

– The address FD710H (FC00 :1710)is latched on the address lines A19−A0 at the end

of T1 of first bus cycle.

– The address FD712H (FC00 :1712)is latched on the address lines A19−A0 at the end

of T1 of second bus cycle.

– The data lines D15 − D0 carry the correct data words 7DACH and textEB36H res-

pectively.

Program 6.2 A Simple Memory Read Program

01 ; assembly code to read two words from the following memory addresses:

02 ; FC00:1710 and FC00:1712.

03 .MODEL SMALL

04 .8086

05 .STACK

06 .CODE

07 .STARTUP

08 MOV AX, 0FC00H

09 MOV DS, AX

10 MOV BX, 1710H

11 MOV AX, [BX+0]

12 MOV AX, [BX+2]

13 ENDLESS_LOOP:

14 JMP ENDLESS_LOOP

15 .DATA

16 END


Figure 6.12 – Result of the digital analysis of an 8086 a ROM read cycles.

7 — Designing a Parallel I/O Port

Objectives

The aim of this LAB experiment is to design the fourth phase of our microcomputer system

by interfacing the 8086 to a simple 8-bit parallel I/O port using LEDs and Dip-Switches.

7.1 8086 I/O Mapping

There are two different methods of interfacing I/O to the 8086 microprocessor : (1) isolated

I/O and (2) memory-mapped I/O. In isolated I/O, the IN, INS, OUT and OUTS instructions

transfer data between the microprocessor accumulator (i.e. AX) or memory and the I/O

device. In memory-mapped IO, any instruction that references memory can accomplish the

transfer. Our microcomputer system will be restricted to using isolated I/O mapping.

Isolated I/O

The most common I/O mapping technique used in the 8086 microprocessor is isolated I/O.

This technique uses a separate I/O address space isolated from the memory address space

as shown in Figure 7.1. The addresses for isolated I/O devices, called ports, are accessed

using only I/O instructions. Also, two separate control signals, I/O Read (IOR) and I/O

Write (IOW ), are needed to control access to the I/O space. These tow signals are decoded

form M/IO, RD, and WR signals as shown in Figure 7.2.

70 Designing a Parallel I/O Port

1M x 8

00000H

FFFFFH

1MB

Memory Address Space

64K x 8

0000H

FFFFH

64KB

I/O Address Space

Figure 7.1 – Isolated I/O address space.

RD

M/IO

WR

IOR

MEMR

MEMW

IOW

Figure 7.2 – Decoding memory and I/O read and write signals.


Memory-Mapped I/O

This technique uses the memory address space of the 8086 microprocessor as shown in

Figure 7.3. It uses any instruction that transfer data between the microprocessor and the

memory. A memory-mapped I/O device is treated as a memory location in the memory

map. The IOR and IOW control signals are not required in memory-mapped I/O system

which will reduce the amount of circuitry required for decoding. However, the disadvantage

of this technique is that a portion of the memory system is used for I/O mapping.

00000H

FFFFFH

1MB

Memory Address Space

I/O

Memory + I/O

Figure 7.3 – Memory-mapped I/O address space.

7.2 Designing a Simple 8-Bit Parallel Port

The I/O ports are very essential in any computer system because they enable the user to

communicate with the system. In this experiment, we will design and implement a very

simple form of I/O ports (switches for input and LEDs for output).

The input port should be designed to pass the data on the input switches to the data

bus if and only if an input instruction (I/O read cycle) is executed by the CPU. This can

be achieved using a tri-state buffer that will be enabled only during I/O read cycles.

The output port should be capable of storing the data on the bus when the CPU performs

an output instruction (I/O write cycle). In this case, a latch can be used to store the output

data and supply it continuously to the LEDs. The latch should be enabled to pass its input

to the LEDs only when the CPU is writing to the output port (i.e. I/O write cycle).

Just as each memory location has its own (memory) address, each I/O port has its

own (port) address. However, since we are using only one I/O port, we will not assign any

addresses to our I/O port. Thus, I/O instructions can use dummy addresses to access our

I/O port. Later on when we interface more I/O ports to our system, we will assign real

addresses to distinguish these ports.


Input Port

The 8-bits input port can be designed using a simple circuit as shown in Figure 7.4. The

design consists of the following parts :

1. 8-dip switches (DIPSW_8) which will be used to read 8-bits on parallel through the

data bus of the 8086 microprocessor. Note that it is our choice to connect the I/O

port to either the odd byte (D15 − D8) or the even byte (D7 − D0). If the I/O port is

connected to D15−D8, then odd dummy addresses must be used with I/O instructions

accessing this port. Otherwise even dummy addresses must be used.

2. 8 × 1KΩ resistors.

3. A 74LS244 octal 3-state buffer which is used for two purposes : (1) to buffer the I/O

data and (2) to enable the I/O data during I/O read operation and disable it otherwise.

The input port is enabled by the IOR signal which is connected to the Output Enable

(OE) pins of the octal buffer.

Figure 7.4 – 8-bits input port.


Output Port

The 8-bits output port can be designed using a simple circuit as shown in Figure 7.5. The

design consists of the following parts :

1. 8 LEDs (LED-RED) which will be used to display an 8-bit output byte on parallel.

2. A 74LS373 octal latch which will be used to store the output data and supply it

continuously to the LEDs. The latch is enabled to pass its input to the LEDs only

when the CPU is writing to the output port (i.e. I/O write cycle). This functionality is

achieved by connecting the complement of the IOW signal to the Latch Enable (LE)

pin of the 74LS373 chip.

Figure 7.5 – 8-bits output port.

Exercise 7.1 Open the microcomputer system design built throughout the previous experiments, and

create a new design sheet with title "I/O Ports". In the newly created design sheet, draw the schematic

of the I/O ports shown in Figures 7.4 and 7.5.

7.2.1 Testing the I/O Port

In this part of the experiment, we will test our system using an assembly code that reads on

byte from the input port and displays it on the output port. The testing procedure involves

the following steps :

1. Write an assembly code (see Program 7.1) to reads one byte from a dummy port

address 0EH and displays it on the same dummy port address. Note that we did not

assign any port addresses to our I/O parallel port, and hence we can use any port

address as long as it is even (Why ?).




4. Run the simulation.

Program 7.1 A Simple I/O Read/Write Program

01 ; assembly code to read one byte from dummy port address 0eh

02 ; and display it on the same dummy port address.

03 .MODEL SMALL

04 .8086

05 .STACK

06 .CODE

07 .STARTUP

08 IO_LOOP:

09 IN AL, 0EH

10 OUT 0EH, AL

11 JMP IO_LOOP

12 .DATA

13 END

Exercise 7.2 While the simulation is running, try to input any 8-bit binary value on the dip-switches

and see if it get displayed on the LEDs.

Appendix

This appendix contains the following data sheets :

1. 8086 16-Bit HMOS Microprocessor

2. 8284A CMOS Clock Generator

3. 74LS373 3-State Octal D-Type Transparent Latches

4. 74LS245 3-State Octal Bus Transceiver

5. 74LS244 3-State Octal Buffer

6. 6264 8K × 8 Static RAM

7. 2764 8K × 8 EPROM

8. 8255A Programmable Peripheral Interface

9. 8253 Programmable Interval Timer

10. 8259A Programmable Interrupt Controller

8284 Manual

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