8086 ppts

X86 Session_15Protected mode operations in 286 & 386 contd.

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PagingThe paging unit uses the linear address computed by the segmentation unit to produce the physical addressEach 4 Kbyte page is known as a page frameThe 32 bit base for the 1024 page frames are kept in a page tableThe 32 bit base addresses and some other information for page tables are kept in a page directory


PagingRegister CR3 points to the base of the page directoryThe selected entry in the page directory points to one of 1024 possible entries in the page tablesThe selected entry in the page table contains the 32 bit base address of the desired 4 Kbytes page frameThe maximum amount of memory represented is 1024 page tables x 1024 pages/page table x4096 bytes/page or 4Gb


Virtual x86 Mode

A 386 operating in protected mode can switch to virtual 8086 mode to execute a time slice and switch back to protected mode to perform a time sliceComputes physical addresses using the segment-offset mechanism used by an 8086 limiting the address range to 1MBThe OS must have a section of privilege level 0 code called a virtual machine monitor


Virtual x86 ModeMonitor intercepts interrupts and exceptionsDuring the task switch to the monitor,the state of the 8086 task is saved in its TSSMonitor may transfer execution to the 386 protected mode OS ,or DOS or to the 8086 program

Property of Accel Technologies Ltd., Copyright protectedTSS:Task state segment

Memory Management SummaryReal mode: 16-bit, no protectionIdeal for tiny to small system (1MB)Virtual X86 Mode16-bit, to run DOS boxes in protected mode


80386 Interrupts / ExceptionsThere are three types of interrupts available in 80386 and they are similar to the ones in 8086

1. Hardware interrupts 2. Exceptions 3. Software interrupts 80386 can handle 256 different interrupts / Exceptions


Hardware Interrupts NMI pin used as the non maskable

interruptThe 8 -bit vector is supplied internally INTR pin used as the maskable interrupt When IF bit is set to 1 an 8 -bit vector is supplied by the user via external hardware


Interrupt and Exception Handling The Software Interrupts is by execution of INT n It has the same effect as the hardware interruptSome examples of software interrupts are

INT 3 used as a breakpoint interrupt INT 1 used for single stepping purpose EXCEPTIONS: 1. Faults 2. Traps 3. Aborts


ExceptionsFaults : Exceptions that are detected and serviced before the execution of the faulting instructionTraps : They are user defined interruptsAborts : Exceptions which do not allow the exact location of the instruction causing the exception to be determined


Priorities of InterruptsIn case of several interrupts / exceptions occurring at the same time the following priority is followed.

1. Exception faults 2. TRAP instructions 3. Debug traps for this instruction 4. Debug faults for next instruction 5. NMI 6. INTR


80386 RESETUpon hardware reset the 80386 registers will be as below.The flag word will be UUUU0002H. Machine status word UUUUUUU0H. Instruction Pointer will have 0000FF0H The Code Segment will be F000H Data segment , Extra segment ES ,FS & GS will be initialized to 0000H. All other Registers will have U ( Undefined)


TESTABILITY

80386 can perform a self testSelf test starts when the RESET pin goes from High to Low and the BUSY # pin is lowThe self test takes about 30ms with a

16 MHz clockIf the self test is successful, the contents of EAX & EDX will be zero.If not zero , it will indicate a faulty chip


Interrupt TableStore interrupt handler addressesLocation and format depend on the memory model:Real mode:The table starts at physical address 04-byte entries (real mode far pointers)Protected modeInterrupt Descriptor Table (IDT)The RTOS determines where the table isContains 8-byte entries (descriptors)


DebuggingTwo dedicated types of debug registers:Address registersDebug control registersIdeal for hardware breakpoints:The registers monitors addresses on the busThey trigger the DEBUG exception on a matchThe DEBUG exception is called upon:Hardware of software breakpointsSingle step modeTask switch to a specific taskSupports software breakpoints (opcode 0xCC)


TSS:Task state segment

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