8086 module 1 & 2 work

INTEL 8086

MICROPROCESSOR

Suresh.PHOD / ECE

Royal College of Engineering and TechnologyChiramanangad PO, Akkikkavu

MODULE

1 & 2Complete idea about INTEL 8086

Microprocessor

Topics to be covered

1. Software Architecture of the INTEL 8086.

2. Hardware Architecture of INTEL 8086.

3. 8086 Programming and program development.

RCET Microprocessor & Microcontroller 3

Software architecture of the INTEL 8086

Memory segmentation and addressing

Block diagram of 8086

Address space & Data organization

Data Types

Registers

Stack

I/O space


Hardware Architecture of INTEL 8086

Pin Diagram and Pin Details

min/max mode

Coprocessor and Multiprocessor configuration

Hardware organization of address space

Control signals

I/O interfaces


8086 programming and program development.

Assembly Language Programming.

Instruction Set.

Assembler Directives.

Programming Exercises.


Software Architecture of

INTEL 8086


Software architecture of the INTEL 8086




Data Types

Registers

Stack

I/O space



• Von – Newman architecture & Harvard architecture

• Program Memory & Data Memory

• Need for Segmentation

– To implement Harvard architecture

– Easy to debug

– Same Interfacing ICs can be used

– To avoid overlap of stack with normal memory

– Compatible with 8085


Segmented Memory


Memory Address Generation

• The BIU has a dedicated adder for determining physical memory addresses.


Physical Address (20 Bits)

Adder

Segment Register (16 bits) 0 0 0 0

Offset Value (16 bits)

Segment : Offset Address

• Logical Address is specified as segment:offset

• Physical address is obtained by shifting the segmentaddress 4 bits to the left and adding the offset address.

• Thus the physical address of the logical addressA4FB:4872 is:

A4FB0

+ 4872

A9822


Segments, Segment Registers & Offset Registers

• Segment Size = 64KB

• Maximum number of segments possible = 14

• Logical Address – 16 bits

• Physical Address – 20 bits

• 2 Logical Addresses for each Segments.

– Base Address (16 bits)

– Offset Address (16 bits)

• Segment registers are used to store the Base address of the segment.


Segments, Segment Registers & Offset Registers

• 4 Segments in 8086

– Code Segment (CS)

– Data Segment (DS)

– Stack Segment (SS)

– Extra Segment (ES)


SEGMENT SEGMENT REGISTER

OFFSET REGISTER

Code Segment CSR Instruction Pointer (IP)

Data Segment DSR Source Index (SI)

Extra Segment ESR Destination Index (DI)

Stack Segment SSR Stack Pointer (SP) / Base Pointer (BP)

Pipelined architecture of the 8086 microprocessors


Execution and bus interface units


Software Model of the 8086 Microprocessors




Memory address space

Storing a word in memory

What is the word in (b) in Hex?

Aligned and misaligned data word


Aligned and misaligned double words of data


Storing double word in memory


Data Types


Unsigned word integer0 – 65,535

Unsigned byte integer0 - 255

Data Types


Signed integers

-128 - +127

-32,768 - +32,767

Data Types


Binary Coded Decimal (BCD)

Unpacked BCD

Packed BCD

American Standard Code for Information Interchange (ASCII)


Dedicated, Reserved, and General use Memory


8086 Registers


CS

SS

DS

ES

Segment

BP

Index

SP

SI

DI

AH

BH

CH

DH DL

CL

BL

AL

General Purpose

Status and Control

Flags

IP

AX

BX

CX

DX

General Purpose Registers

• Normally used for storing temporary results

• Each of the registers is 16 bits wide (AX, BX, CX, DX)

• Can be accessed as either 16 or 8 bits AX, AH, AL


AX - the AccumulatorBX - the Base RegisterCX - the Count RegisterDX - the Data Register


• AX– Accumulator Register

– Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code

– Must be used in multiplication and division operations

– Must also be used in I/O operations

• BX– Base Register

– Also serves as an address register



• CX

– Count register

– Used as a loop counter

– Used in shift and rotate operations

• DX

– Data register

– Used in multiplication and division

– Also used in I/O operations


Pointer and Index Registers

• All 16 bits wide, L/H bytes are not accessible

• Used as memory pointers– Example: MOV AH, [SI]

• Move the byte stored in memory location whose address is contained in register SI to register AH

• IP is not under direct control of the programmerRCET Microprocessor & Microcontroller 32

Flag Register


Carry

Parity

Auxiliary Carry

Zero

Overflow

Direction

Interrupt enable

Trap

Sign6 are status flags3 are control flag

8086 Programmer’s Model


ES

CS

SS

DS

IP

AH

BH

CH

DH

AL

BL

CL

DL

SP

BP

SI

DI

FLAGS

AXBX

CX

DX

Extra Segment

Code Segment

Stack Segment

Data Segment

Instruction Pointer

Accumulator

Base Register

Count Register

Data Register

Stack PointerBase Pointer

Source Index Register

Destination Index Register

BIU registers(20 bit adder)

EU registers

The Stack

• The stack is used for temporary storage of informationsuch as data or addresses.

• When a CALL is executed, the 8086 automatically PUSHesthe current value of CS and IP onto the stack.

• Other registers can also be pushed

• Before return from the subroutine, POP instructions canbe used to pop values back from the stack into thecorresponding registers.


The Stack


Example for PUSH


Example for POP


The I/O address space


Hardware Architecture of

INTEL 8086


Hardware Architecture of INTEL 8086

Pin Diagram and Pin Details

min/max mode

Coprocessor and Multiprocessor configuration

Hardware organization of address space

Control signals

I/O interfaces


INTEL 8086 - Pin Diagram


INTEL 8086 - Pin Details


Ground

Clock

Duty cycle: 33%

Power Supply

5V 10%

Reset

Registers, seg regs, flags

CS: FFFFH, IP: 0000H

If high for minimum 4

clks



Address/Data Bus:

Contains address bits A15-A0 when ALE is 1 & data bits D15 –

D0 when ALE is 0.

Address Latch Enable:

When high, multiplexed

address/data bus contains address

information.



INTERRUPT

Non - maskable interrupt

Interrupt request

Interrupt acknowledge



Direct Memory Access

Hold acknowledge

Hold



Address/Status Bus

Address bits A19 –A16 & Status bits S6

– S3



Bus High Enable/S7

Enables most significant data bits D15 – D8 during read or write operation.

S7: Always 1.

BHE#, A0:

0,0: Whole word (16-bits)

0,1: High byte to/from odd address

1,0: Low byte to/from even address

1,1: No selection



Min/Max mode

Minimum Mode: +5V

Maximum Mode: 0V

Minimum Mode Pins

Maximum Mode Pins

Microprocessor & Microcontroller

Minimum Mode- Pin Details

RCET 50

Read Signal

Write Signal

Memory or I/0

Data Bus Enable

Data Transmit/Receive

Maximum Mode - Pin Details


Status Signal

Inputs to 8288 to generate eliminated signals due to max

mode.

S2 S1 S0

000: INTA001: read I/O port010: write I/O port011: halt100: code access101: read memory110: write memory111: none -passive



DMA Request/Grant

Lock Output

Lock Output

Used to lock peripheralsoff the system

Activated by using theLOCK: prefix on anyinstruction



Queue Status

Used by numeric coprocessor (8087)

QS1 QS0

00: Queue is idle

01: First byte of opcode

10: Queue is empty

11: Subsequent byte of opcode

Minimum Mode 8086 System


‘Read’ Cycle timing Diagram for Minimum Mode


‘Write’ Cycle timing Diagram for Minimum Mode


Maximum Mode 8086 System


Maximum Mode 8086 System • Here, either a numeric coprocessor of the type 8087 or another

processor is interfaced with 8086.

• The Memory, Address Bus, Data Buses are shared resourcesbetween the two processors.

• The control signals for Maximum mode of operation aregenerated by the Bus Controller chip 8788.

• The three status outputs S0*, S1*, S2* from the processor areinput to 8788.

• The outputs of the bus controller are the Control Signals, namelyDEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc.


Memory Read timing in Maximum Mode


Memory Write timing in Maximum Mode


Memory Banking


64

Interface 8086 to 6116 Static RAM

8086

A____

BHE

ALE

A(10-0)

D(7-0)__

R/W

OE*

CS*

A(10-0)

__

R/W

OE*

CS*

D

D(7-0)

20

Latch

Addr

Decoder

A(11-1)

21

A0, BHE*

A(19-12)

A(11-1)

__

M/IO

___

RD

___

WR

Low byte

(Even Bank)

D(7-0)

D(15-8)

16

A0

RAMCS*

MEM*

BHE*

6116 (2K x8)

High byte

(Odd Bank)

8086 Interrupts


8086 Interrupts Procedure


8086 External Interrupts


8086 Interrupt Vector Table


Programmingwith

INTEL 8086


8086 programming and program development.

Assembly Language Programming.

Instruction Set.

Assembler Directives.

Programming Exercises.


General Syntax


x86 Instruction Set Summary(Data Transfer)

1. CBW ;Convert Byte to Word AL AX

2. CWD ;Convert Word to Double in AX DX,AX

3. IN ;Input

4. LAHF ;Load AH from Flags

5. LDS ;Load pointer to DS

6. LEA ;Load EA to register

7. LES ;Load pointer to ES

8. LODS ;Load memory at SI into AX

9. MOV ;Move

10. MOVS ;Move memory at SI to DI

11. OUT ;Output

12. POP ;Pop

13. POPF ;Pop Flags

14. PUSH ;Push

15. PUSHF ;Push Flags

16. SAHF ;Store AH into Flags

17. STOS ;Store AX into memory at DI

18. XCHG ;Exchange

19. XLAT ;Translate byte to ALRCET Microprocessor & Microcontroller 74

x86 Instruction Set Summary(Arithmetic/Logical)

1. AAA ;ASCII Adjust for Add in AX

2. AAD ;ASCII Adjust for Divide in AX

3. AAM ;ASCII Adjust for Multiply in AX

4. AAS ;ASCII Adjust for Subtract in AX

5. ADC ;Add with Carry

6. ADD ;Add

7. AND ;Logical AND

8. CMC ;Complement Carry

9. CMP ;Compare

10. CMPS ;Compare memory at SI and DI

11. DAA ;Decimal Adjust for Add in AX

12. DAS ;Decimal Adjust for Subtract in AX

13. DEC ;Decrement

14. DIV ;Divide (unsigned) in AX(,DX)

15. IDIV ;Divide (signed) in AX(,DX)

16. MUL ;Multiply (unsigned) in AX(,DX)

17. IMUL ;Multiply (signed) in AX(,DX)

18. INC ;Increment


x86 Instruction Set Summary(Arithmetic/Logical Cont.)

19. NEG ;Negate

20. NOT ;Logical NOT

21. OR ;Logical inclusive OR

22. RCL ;Rotate through Carry Left

23. RCR ;Rotate through Carry Right

24. ROL ;Rotate Left

25. ROR ;Rotate Right

26. SAR ;Shift Arithmetic Right

27. SBB ;Subtract with Borrow

28. SCAS ;Scan memory at DI compared to AX

29. SHL/SAL ;Shift logical/Arithmetic Left

30. SHR ;Shift logical Right

31. SUB ;Subtract

32. TEST ;AND function to flags

33. XLAT ;Translate byte to AL

34. XOR ;Logical Exclusive OR


x86 Instruction Set Summary(Control/Branch)

1. CALL ;Call

2. CLC ;Clear Carry

3. CLD ;Clear Direction

4. CLI ;Clear Interrupt

5. ESC ;Escape (to external device)

6. HLT ;Halt

7. INT ;Interrupt

8. INTO ;Interrupt on Overflow

9. IRET ;Interrupt Return

10. JB/JNAE ;Jump on Below/Not Above or Equal

11. JBE/JNA ;Jump on Below or Equal/Not Above

12. JCXZ ;Jump on CX Zero

13. JE/JZ ;Jump on Equal/Zero

14. JL/JNGE ;Jump on Less/Not Greater or Equal

15. JLE/JNG ;Jump on Less or Equal/Not Greater

16. JMP ;Unconditional Jump


x86 Instruction Set Summary(Control/Branch Cont.)

17. JNB/JAE ;Jump on Not Below/Above or Equal

18. JNBE/JA ;Jump on Not Below or Equal/Above

19. JNE/JNZ ;Jump on Not Equal/Not Zero

20. JNL/JGE ;Jump on Not Less/Greater or Equal

21. JNLE/JG ;Jump on Not Less or Equal/Greater

22. JNO ;Jump on Not Overflow

23. JNP/JPO ;Jump on Not Parity/Parity Odd

24. JNS ;Jump on Not Sign

25. JO ;Jump on Overflow

26. JP/JPE ;Jump on Parity/Parity Even

27. JS ;Jump on Sign

28. LOCK ;Bus Lock prefix

29. LOOP ;Loop CX times

30. LOOPNZ/LOOPNE ;Loop while Not Zero/Not Equal

31. LOOPZ/LOOPE ;Loop while Zero/Equal

32. NOP ;No Operation (= XCHG AX,AX)


x86 Instruction Set Summary(Control/Branch Cont.)

33. REP/REPNE/REPNZ ;Repeat/Repeat Not Equal/Not Zero

34. REPE/REPZ ;Repeat Equal/Zero

35. RET ;Return from call

36. SEG ;Segment register

37. STC ;Set Carry

38. STD ;Set Direction

39. STI ;Set Interrupt

40. TEST ;AND function to flags

41. WAIT ;Wait


8086 Instruction set Summary


8086 Assembler Directives

1. end label end of program, label is entry point

2. proc far|near begin a procedure; far, near keywords specify if the procedure is in different code segment (far), or same code segment (near)

3. endp end of procedure

4. page set a page format for the listing file

5. title title of the listing file

6. .code mark start of code segment


8086 Assembler Directives

7. .data mark start of data segment

8. .stack set size of stack segment

9. db define byte

10. dw define word (2 bytes)

11. dd define double word (4 bytes)

12. dq define quadword (8 bytes)

13. dt define tenbytes

14. equ equate, assign numeric expression to a name


8086 module 1 & 2 work

Engineering

Transcript of 8086 module 1 & 2 work