8051 Microcontroller

INTERRUPTS & PORTS

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Interrupts An event Deviates Normal flow of program execution Asynchronous in occurrence A mechanism to reduce CPU overhead

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Types Internal CPU attention is Requested by a Peripheral Unexpected/unimplemented program execution

External The condition to be Monitored/Updated by the system around the CPU

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Types contd. Vectored Interrupt Service Routine is pointed to by the event causing the Interrupt

Non-vectored Interrupt Service Routine is always at fixed point

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Interrupt Recognition CPU checks for interrupt in every machine cycle. If interrupted, disables further interrupts based on priority. Acknowledges the Interrupt Saves program context. Deviates program execution. Resumes the interrupted program after finishing the Interrupt Service Routine.ED501 5

Priority To solve servicing of simultaneous interrupts To allow Nested Interrupts of different kinds

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Pending Interrupts To hold one interrupt without servicing it To hold one interrupt without destroying it Cause May be blocked by a higher priority interrupt An uncompleted previously generated interrupt of the same kind / priority Intentionally prevented by the program (DI)ED501 7

8051 InterruptsExternal 0 Interrupt Timer 0 Interrupt External 1 Interrupt Timer 1 Interrupt Serial Interrupt Sources 2 External 4 InternalED501 8

- 0003H - 000BH - 0013H - 001BH - 0023H

8051 External Interrupts Based on IT0 / IT1 Flag in the TCON SFR A low level transition at pin P3.2 / P3.3 A low level detection at pin P3.2 / P3.3

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The requirements of the External Signal ? A high state in one machine cycle and low state in the following machine cycle Sufficiently large negative pulse to identify even after the execution of the longest instruction

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8051 Peripheral Interrupts Timer Interrupts Overflow of Timer 0 and Timer 1 in Different modes of Operation Peripheral indicates the overflow to the CPU CPU Services the Interrupt after clearing the Acknowledgement The Acknowledgement is TF0 / TF1 Flags in the TCON SFR

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8051 Peripheral Interrupts Serial Port Interrupts To indicate the CPU the reception of a new data To indicate the CPU the completion of a transmission ISR location is common for the two sources Respective flags will not be cleared even after reaching the ISRED501 12

8051 Interrupt Priority Default Priority ( Highest to Lowest priority) External 0 Interrupt (INT0) Timer 0 Interrupt (TF0) External 1 Interrupt (INT1) Timer 1 Interrupt (TF1) Serial Interrupt (RI+TI)

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Added Priority ( High Level ) Based on the setting of IP SFR Setting IP.x = 1 assigns a High Priority More than one IP.x = 1 seeks Priority within Level (Low level )

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Enabling Interrupts Two level Enable At Peripheral end by IE SFR At CPU end by CPU Instruction but in 8051 the flag is located in IE Register

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The Role of ISR Service the Peripheral e.g. Serial Port Service the System e.g. Timer Any of the above case must not disturb the interrupted program

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The Delimiters of an ISR Interrupt Flag of an enabled interrupt RETI instruction The subroutine is normally terminated by the RET instruction, while an ISR by RETI

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PORTS

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Ports Four bi-directional ports P0 & P2 External Memory Access P1& P3 Multi functional Port structure Latch Input buffer Output driverED501 19

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Ports I/O Configuration Write to latch Read latch Read pin

Address/Data Control Port0, 2 Alternate Function Control- Port1 & 3

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8051 Port Bit Latches and I/O Buffers

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Ports Pullup Internal pullup Port1,2,3 Open Drain Port0

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Alternate FunctionsPort pin Alternate FunctionP1.0 P1.1 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 T2 (External Count Input to Counter/Timer 2), clockout T2EX(Timer/counter 2 capture reload trigger & direction control) RXD (Serial Input Port) TXD (Serial Output Port) INT0/ (External Interrupt 0) INT1/ (External Interrupt 1) T0 (Timer0 External Input) T1 (Timer1 External Input) WR/ (External Data memory write strobe) RD/(External Data memory read strobe)ED501 24

Sometimes we need to access only 1 or 2 pins of the portCPL P1.2 SETB P1.3 complement third pin of port 1 make the 4th pin of port 1 1

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Some instructions read status of the port pin Some instructions read the contents of the read latch E.g. ANL P1,A P1 copied to CPU AND ed with A there Written back to P1 latch Now modified P1 latch data available on P1

This instruction performs a read-modify-writeED501 26

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