8051 Instruction Set
35
The 8051 Microcontroller: Instruction Set
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A short presentation on instruction set of MC-8051
Transcript of 8051 Instruction Set
The 8051 Microcontroller:Instruction Set
1. BYTE INSTRUCTION:
i. MOV A, Rn (Rn ranges)
ii. MUL AB
3. BYTE INSTRUCTION:
i. DNJZ Rn, rel
ii. SUBB A, direct address
5. BYTE INSTRUCTION
i. ANL direct, #data
ii. MOV direct, #data
Length of Instructions:
1.ARITHMETIC INSTRUCTION.
3.DATA TRANSFER INSTRUCTION.
5.LOGICAL INSTRUCTION.
7.BRANCHING INSTRUCTION.
9.LOGICAL OPERATION ON BITS INSTRUCTION.
Classification of instructions:
ARITHMETIC OPERATIONS.
LENGTH-
1 OR 2.
FLAGS AFFECTED.
Arithmetic instruction
FUNCTION.
LENGTH.
FLAGS AFFECTED.
ADDRESSING MODE.
ADD A, Rn
Before executionADD A, R3
A13
B
R0 R1
R2 R331
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
After executionADD A, R3
A44
B
R0 R1
R2 R331
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 1
FUNCTION.
LENGTH.
FLAGS AFFECTED.
ADDRESSING MODE.
INC Rn
Before executionINC A
A1F
B
R0 R1
R2 R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
After executionINC A
A20
B
R0 R1
R2 R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
SOURCE TO DESTINATION.
LENGTH.
FLAGS AFFECTED.
MOV/MOVC/MOVX
Data transfer group
FUNCTION.
MOV <destination byte>,<source Byte>
Flags affected.
Length-1, 2 or 3
Source-Destination combo.
Before executionMOV A, R7
A00
B
R0 R1
R2 R3
R4 R5
R6 R714
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
After executionMOV A, R7
A14
B
R0 R1
R2 R3
R4 R5
R6 R714
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
FUNCTION.
FLAGS AFFECTED.
LENGTH.
COMPULSORY OPERAND.
XCH A, Rn
Before executionXCH A, R5
A27
B
R0 R1
R2 R3
R4 R572
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
After executionXCH A, R5
A72
B
R0 R1
R2 R3
R4 R527
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
PERFORMS LOGICAL OPERATIONS.
LENGTH-1,2 OR 3
FLAG AFFECTED.
Logical group
FUNCTION.
FLAGS AFFECTED.
LENGTH.
ANL A, R0
Before executionANL A, R2
A10
B
R0 R1
R201
R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
After executionANL A, R2
A00
B
R0 R1
R201
R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
FUNCTION.
FLAGS AFFECTED.
LENGTH.
CPL A
Before executionCPL A
AFF
B
R0 R1
R2 R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
After executionCPL A
A00
B
R0 R1
R2 R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
TRANSFERS PROGRAM CONTROL.
LENGTH.
FLAGS AFFECTED.
Branching Instructions
FUNCTION.
LENGTH-
2 OR 3
FLAGS AFFECTED.
DJNZ <byte>,<rel-address>
FUNCTION.
LENGTH.
FLAGS AFFECTED.
JNZ rel
FUNCTIONS.
PERFORMED ON BITS.
LENGTH-
1 OR 2
Logical operations on Bit
FUNCTION.
LENGTH-
1 OR 2
FLAGS AFFECTED.
CLR bit
Before executionCLR C
AFF
B
R0 R1
R2 R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
1 0 - 1 1 0 - 0
After executionCLR C
AFF
B
R0 R1
R2 R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
FUNCTION.
LENGTH-
1 OR 2
FLAGS AFFECTED.
CPL bit
Before executionCPL C
AFF
B
R0 R1
R2 R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
0 0 - 1 1 0 - 0
After executionCPL C
AFF
B
R0 R1
R2 R3
R4 R5
R6 R7
CY AC F0 RS1 RS0 OV - P
1 0 - 1 1 0 - 0
By:Mayank Sharma
