80483977 DMA is Implemented Using a DMA Controller

7/29/2019 80483977 DMA is Implemented Using a DMA Controller

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OVERVIEW Introduction

Implementing DMA in a computer system

Data transfer using DMA controller

Internal configuration of a DMA controller

Process of DMA transfer

DMA transfer modes

Modification of the CPU to work with DMA

Summary


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What is DMA?

Direct Memory Access

Assists the movement of data between externalmemory and internal peripherals with minimal CPU

intervention An internal peripheral is assigned to one or more

DMA channels.

Each channel moves data one direction.

It either receives incoming data or transmitsoutgoing data.


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Direct Memory Access (DMA)

To transfer large blocks of data at high speed,

an alternative approach is used.

Blocks of data are transferred between an

external device and the main memory,

without continuous intervention by the

processor.


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Direct Memory Access (DMA)

Summary

10 Channels total

8 channels wired into NET+ARM modules

Ethernet, Serial, Parallel / ENI

2 Channels available for external Memory moves Handshaking signals muxed into GPIO lines

Can move data while ARM executes from Cache

Simple Implementation

Good for repetitive data movement


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DMA is implemented using a DMA controller

DMA controller

Acts as slave to processor

Receives instructions from processor


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Steps in a DMA operation

Processor initiates the DMA controller

Gives device number, memory buffer pointer,

Called channel initialization

Once initialized, it is ready for data transfer

processor DMA controller

Gives

device

number

I/O device number


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When ready, I/O device informs the DMA controller

DMA controller starts the data transfer process

Obtains bus by going through bus arbitration

Places memory address and appropriate control signalsCompletes transfer and releases the bus

Updates memory address and count value

If more to read, loops back to repeat the process

DMA controllermicroprocessor

Data bus

I/O device number


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Modes of Operation

Fly-by

Data is directly transferred between memory and the

peripheral

Memory to Memory

Data is not directly transferred, but buffered in between

transfers Data is copied from the source location into a temporary

area in the DMA channel, and then written into the

destination location.


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External DMA Fly By

Memory

DMA

Controller

Peripheral

Net+ARM

Add

DMA

Request

DMA

Grant

DATA


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External DMA Mem To Mem

Memory

DMA

ControllerPeripheral

Net+ARM

ADD

DMARequest

DMA Grant

DATA

DATA

ADD

Holding FIFO


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Implementing DMA in a Computer

System

A DMA controller implements direct memory accessin a computer system.

It connects directly to the I/O device at one end and

to the system buses at the other end. It also interactswith the CPU, both via the system buses and twonew direct connections.

It is sometimes referred to as a channel. In an

alternate configuration, the DMA controller may beincorporated directly into the I/O device.


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Data Transfer using DMA Controller

To transfer data from an I/O device to memory, theDMA controller first sends a Bus Request to the CPUby setting BR to 1. When it is ready to grant thisrequest, the CPU sets its Bus grant signal, BG to 1.

The CPU also tri-states its address,data, and controllines thus truly granting control of the system busesto the DMA controller.

The CPU will continue to tri-state its outputs as longas BR is asserted.cont


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Process of DMA Transfer To initiate a DMA transfer, the CPU loads the address

of the first memory location of the memory block (tobe read or written from) into the DMA addressregister. It does his via an I/O output instruction,

such as the OTPT instruction for the relatively simpleCPU.

It then writes the no. of bytes to be transferred intothe DMA count register in the sane manner.

Finally, it writes one or more commands to the DMAcontrol register.


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Internal Configuration

The DMA controller includes several registers :-

The DMA Address Register contains the memoryaddress to be used in the data transfer. The CPUtreats this signal as one or more output ports.

The DMA Count Register, also called Word CountRegister, contains the no. of bytes of data to betransferred. Like the DMA address register, it too istreated as an O/P port (with a diff. Address) by theCPU.

The DMA Control Register accepts commands fromthe CPU. It is also treated as an O/P port by the CPU.


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Operating Sequence of a DMA Transfer

To perform a DMA transfer the CPU: allocates a memory block and assigns it to the DMAC;

writes the transfer mode and the address of the peripheral device tothe DMAC registers;

waits for DMA request from the peripheral after configuring the

DMAC. If a peripheral device receives data from outside it asserts the

request signal to the DMAC.

The DMAC transfers the received data from the peripheral devicecontroller to the memory and asserts the acknowledge signal to theperipheral device.

When the transfer is completed a flag in the status register of theDMAC will be set and/or the DMA controller sends an interrupt tothe CPU.


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Main Features of the DMA Controller

(I) The DMAC will be designed for an AMBA AHB 2.0 bus with a big-

endian data format.

The DMAC is configurable for each valid AHB data bus width from32 bits up to 1024 bits.

The DMAC has several independent DMA channels. The number of

these channels is configurable from 1 up to 31. The DMAC executes only dual-access transfers using an internal

memory organised as FIFO.

The DMAC supports single transfers as well as a block transfer. Single transfer consists of a read burst and a subsequent write burst.

A block transfer consists of several successive single transfers.

The burst length as well as the number of transfers isprogrammable.


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a n ea ures o eController (II)

The data width of a transfer is programmable from 8 bits upto the data bus width in steps of powers to the base of two(8 bits, 16 bits, , 1024 bits).

The controller supports all four possible kinds of transfer

Peripheral

Memory Memory Peripheral

Peripheral Peripheral

Memory Memory

A transfer can be triggered by sending a software command

from the CPU or by asserting of a request signal DREQ. The controller asserts an acknowledge signal DACK as a

response on a hardware request.


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rans er a e o eController

0

50

100

150200

250

300

350

400

1 32

Burst Length

TransferRateinunitso

Mbits/sec

This chart shows the

theoretical (top curve) and

measured transfer rate of

the DMAC. These transfer

rates apply to a 25 MHz

system clock.The measured transfer rate

is lower than the

theoretical transfer rate

due to the used memoryconfiguration.


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Advantages of DMA

Fast memory transfer of data

CPU and DMA run concurrently under cache

mode

DMA can trigger an interrupt, which frees the

CPU from polling the channel


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Buffers and Arbitration

Most DMACs have a data storage buffernetwork interfaces receive data from mainmemory at bus speed, send data onto

network at network speed.

Bus Arbitration is needed to resolve conflicts

with more than one device (2 DMACs or DMAand processor, etc..) try to use the bus toaccess main memory.


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Summary Advantages of DMA

Computer system performance is improved by directtransfer of data between memory and I/O devices,bypassing the CPU.

CPU is free to perform operations that do not use systembuses.

Disadvantages of DMA In case of Burst Mode data transfer, the CPU is rendered

inactive for relatively long periods of time.

n ma ys em w a


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n ma ys em w aController

RequestPeripheral

Device

DMA

Controller

Memory

Acknowledge

CPU

On-Chip-BusInterrupt

Bus

Arbiter


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Conclusions

A DMA controller specification for a SoC has been conceivedsupporting a list of typical and application-specific features.

A sophisticated DMA controller has been designed. The DMA controller has been implemented successfully as a VHDL

IP core. The DMA Controller has been integrated together with the LEON-2

IP core in a Xilinx Virtex-II FPGA. The functionality of DMA controller has been tested extensively. The DMAC is suitable for use with High-bandwidth Peripherals. The following CAD tools have been used:

Mentor ModelSim

Synplicity Synplify XILINX Foundation ISE 5.1

80483977 DMA is Implemented Using a DMA Controller

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