78Q8430 ARM9 (920T) Embest Evaluation Board User Manual

Simplifying System IntegrationTM

78Q8430

ARM9(920T) Embest Evaluation Board User Manual

May, 2008 Rev. 1.0

UM_8430_007

78Q8430 ARM9(920T) Embest Evaluation Board User Manual UM_8430_007

2 Rev. 1.0

© 2008 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. ARM9 is a trademark of ARM Limited. Linux is the registered trademark of Linus Torvalds. Pentium is a registered trademark of Intel Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative.

Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com

UM_8430_007 78Q8430 ARM9(920T) Embest Evaluation Board User Manual

Rev. 1.0 3

Table of Contents

1 Introduction ......................................................................................................................................... 5 1.1 Package Contents......................................................................................................................... 6 1.2 Safety and ESD Notes .................................................................................................................. 7 1.3 System Hardware Requirements .................................................................................................. 7 1.4 System Software Requirements ................................................................................................... 7

2 System Setup ...................................................................................................................................... 8 2.1 Jumper and Dip Switch Settings ................................................................................................... 8 2.2 Connections .................................................................................................................................. 9 2.3 System Startup ........................................................................................................................... 10

3 78Q8430 Embest Evaluation Board Schematic, BOM and PCB Layout ...................................... 11

4 Ordering Information ........................................................................................................................ 20

5 Related Documentation .................................................................................................................... 20

6 Contact Information .......................................................................................................................... 20


4 Rev. 1.0

Figures Figure 1: 78Q8430 System Interface Diagram ............................................................................................. 6 Figure 2: 78Q8430 Embest Evaluation Board Jumper Locations ................................................................. 8 Figure 3: 78Q8430 Embest Evaluation System Hardware Connections ...................................................... 9 Figure 4: Bus Interface Block Diagram ....................................................................................................... 11 Figure 5: Bus Interface Schematic .............................................................................................................. 12 Figure 6: MICTOR Diagnostic Connectors Schematic ............................................................................... 13 Figure 7: MAC Interface Schematic ............................................................................................................ 14 Figure 8: PHY Interface Schematic ............................................................................................................. 15 Figure 9: Top Silkscreen Layout ................................................................................................................. 17 Figure 10: Top Layer Layout ....................................................................................................................... 17 Figure 11: VCC Layer Layout ..................................................................................................................... 18 Figure 12: Ground Layer Layout ................................................................................................................. 18 Figure 13: Bottom Layer Layout .................................................................................................................. 19 Figure 14: Bottom Silkscreen Layout .......................................................................................................... 19

Tables Table 1: 78Q8430 Embest Evaluation Board Jumper Settings .................................................................... 8 Table 2: 78Q8430 Embest Evaluation Board Bill of Materials .................................................................... 16 Table 3: Order Number and Part Description ............................................................................................. 20


Rev. 1.0 5

1 Introduction

The 78Q8430 Embest Evaluation Board (D8430T3A_EB) is a design example for a 10/100BASE-TX MAC+PHY Embest S3CEB2410 daughter card. The D8430T3A_EB plugs directly into the Embest S3CEB2410 (ARM9™ based) motherboard. The network connection is provided by the 78Q8430 which is a single chip auto-sensing, auto-switching (auto-negotiation or parallel detect modes and auto-MDIX) 10/100BASE-TX Fast Ethernet transceiver with full duplex operation capability. The device is designed specifically for the Audio/Visual (A/V) and Set Top Box (STB) markets and is easily interfaced to available A/V and STB core processors. The 78Q8430 is compliant with applicable IEEE-802.3 standards. MAC and PHY configuration and status registers are provided as specified by IEEE802.3u. The integrated MAC is supported by an internal 32KByte transmit and receive SRAM FIFO. The partition of transmit and receive queues is configurable through software, allowing the 78Q8430 to be tuned for specific applications. The device contains hardware support for TCP-IP checksum and ARC address recognition. The D8430T3A_EB provides support for the following 78Q8430 hardware interface features: • The system bus interface operates like external memory with an active low chip select. • Supports asynchronous big endian bus format. • Supports asynchronous 100 MHz operation. • Supports 32-bit wide data bus. • Optional EEPROM interface for configuration data. • Two programmable LED outputs for PHY status. • Single +3.3V power supply voltage with a common ground plane. A host processor interfaces directly to the FIFO via the Global Bus Interface (GBI). The D8430T3A_EB is configured for 32-bit big endian bus format. Figure 1 shows the 78Q8430 system interfaces.


6 Rev. 1.0

Activity (Programmable)

32-bit/16-bit/8-bitSystem

Bus

InterfaceConfiguration

EEPROM Interface

JTAGInterface

78Q8430Single Chip

10/100 EthernetMAC & PHY

RJ45

Integrated RJ-45 with 1:1

Transformer

CAT5Cable

LED

LED

Link (Programmable)

Figure 1: 78Q8430 System Interface Diagram

This document describes the setup and configuration of the 78Q8430 Embest Evaluation Board. The evaluation board requires operation with a +3.3 V power supply sourced from the Embest bus interface on the S3CEB2410 evaluation board. The 78Q8430 PHY interfaces to a CAT5 UTP cable via a 1:1 transformer. The supplied software driver includes support for the Linux® operating system. The included 78Q8430 Software Driver Development Guidelines and 78Q8430 ARM9 Linux Driver User and Test Guide documents describe the software interfacing requirements for quick driver integration and prompt system evaluation of the 78Q8430. Use this document with those listed in the Related Documentation section. 1.1 Package Contents The 78Q8430 Embest Evaluation Board kit includes: • A 78Q8430 Embest Evaluation Board (D8430T3A_EB). • The Embest ARM9 S3CEB2410 evaluation platform. • A memory card containing the 78Q8430 Linux software device driver and supporting tools. • The following documents on CD:

• 78Q8430 ARM9(920T) Embest Evaluation Board User Manual (this document) • 78Q8430 Preliminary Data Sheet • 78Q8430 Layout Guidelines • 78Q8430 Software Driver Development Guidelines • 78Q8430 78Q8430 Driver Guide for ARM920T Linux • 78Q8430 ARM9(920T) Linux Driver Diagnostic Guide

The printed circuit board Gerber files are available upon request.

UM_8430_007 78Q8

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8 Rev. 1.0

2 System Setup 2.1 Jumper and Dip Switch Settings The 78Q8430 Embest Evaluation Board utilizes several jumpers (JA, JC and J12 through J15) for establishing the startup configuration of the 78Q8430 device. Figure 2 shows the location of the jumpers. Table 1 describes the jumper options. The jumper numbers and settings are printed on the board.

Figure 2: 78Q8430 Embest Evaluation Board Jumper Locations

Table 1: 78Q8430 Embest Evaluation Board Jumper Settings

Jumper Name Setting Description J15 CLKMODE

Selection GND Internal clock. 3P3V External clock (default).

JA Chip Select Source CS0 Selects the source for the 78Q8430 chip select signal. The default setting is CS5. CS1

CS2 CS3 CS4 CS5

J12 J13 J14

Interrupt Selection INT5 Selects the destination for the 78Q8430 Interrupt signal. The default setting is INT16. INT6

INT7 INT8 INT9 INT16 INT17 INT18


Rev. 1.0 9

Jumper Name Setting Description JC Clock Source CLK1 Selects the source for the 78Q8430 clock.

The default setting is CCLK. CLK0 VCLK SCLK CCLK

2.2 Connections Connect the system components as shown in Figure 3. Refer to the Embest S3CEB2410 documentation for additional information on the connections for that platform.

Figure 3: 78Q8430 Embest Evaluation System Hardware Connections

STEP 1: Attach the 78Q8430 Embest Evaluation Board to the S3CEB2410 Evaluation Board via the three connectors on the bottom of the 78Q8430 evaluation board. STEP 2: Connect the 78Q8430 Embest Evaluation Board Ethernet port to the Linux PC using a CAT-5 cable. STEP 3: Connect a serial console cable from the Linux Host PC serial port to the S3CEB2410 board serial port. STEP 4: Insert the memory card containing the 78Q8430 Linux software device driver into the memory card slot on the S3CEB2410 board.


10 Rev. 1.0

2.3 System Startup STEP 1: On the Linux Host, set the testing port IP address to 192.168.10.100 (the S3CEB2410 platform boots with IP address 192.168.10.99). STEP 2: Open a full height xterm or kconsole window on the Linux Host. STEP 3: Start minicom on the Linux Host at the xterm/kconsole command prompt:

~# minicom

STEP 4: Turn on the S3CEB2410 board power. Refer to the S3CEB2410 documentation for additional information. The 78Q8430 Embest Evaluation Board receives its power through the Embest bus interface on the S3CEB2410 Evaluation Board. STEP 5: Boot the S3CEB2410 Board. Console messages must appear in the minicom window after power on.

▪ Hit the space bar at the first boot prompt ▪ Respond with: cpu set 200 2 ▪ On the next prompt, respond: boot

STEP 6: When boot up completes, enter the following at the prompt:

arp -s 192.168.10.100 00:0E:2E:5B:25:86 STEP 7: On the Linux Host, issue the following ping command to verify the connection to the target:

ping 192.168.10.99


Rev. 1.0 11

3 78Q8430 Embest Evaluation Board Schematic, BOM and PCB Layout

ENDIAN0

PMEB

BOOTSZ1BOOTSZ0WAITMODE

TDITDOTMSTRSTTCLKENDIAN1

TXP

LED1LED0

J1

XTLN

XTLP

RXNRXP

TXN

J2

RJ45

25MHz Crystal

Logic Analyzer PodsMictor Connectors

TP2 & TP5

PROMCSPROMCLK

PROMDIPROMDO

VDCLKCLK1

SDCLKCDCLK

NGCS3NGCS2

NGCS5NGCS4

R42BINT6BINT5

U4

BINT9BINT8BINT7

BINT17BINT16

BINT19BINT18

R43

JC

CLKMODEBUSMODE

INTERFACES3CEB2410

CLK0

DB31:0

AB9:0

BNWEBNOE

NGCS1NGCS0

NRESET

MEMWAIT

JP

J12-J14

VCC33 L1

78Q8430B

DATA31:0

ADDR9:0

WRBOEB

CSB

RESETB

BUSCLK

INTB

MEMWAIT

JA

VCCAVCCD

Figure 4: Bus Interface Block Diagram


12 Rev. 1.0

Figure 5: Bus Interface Schematic

11 2 2

33 4 4

55 6 6

77 8 8

99 10 10

1111 12 12

1313

1414

1515

1616

1717

1818

1919

2020

2121 22 22

2323 24 24

2525 26 26

2727 28 28

2929 30 30

3131 32 32

3333 34 34

3535

3636

3737

3838

3939

4040

4141

4242

4343 44 44

4545 46 46

4747 48 48

4949 50 50

5151 52 52

5353 54 54

5555 56 56

5757

5858

5959

6060

6161

6262

6363

6464

6565 66 66

6767 68 68

6969 70 70

7171 72 72

7373 74 74

7575 76 76

7777 78 78

7979

8080

JP3

PIN HEADER 40x2EBS40X2

11 2 2

33 4 4

55 6 6

77 8 8

99 10 10

1111 12 12

1313

1414

1515

1616

1717

1818

1919

2020

2121 22 22

2323 24 24

2525 26 26

2727 28 28

2929 30 30

3131 32 32

3333 34 34

3535

3636

3737

3838

3939

4040

4141

4242

4343 44 44

4545 46 46

4747 48 48

4949 50 50

5151 52 52

5353 54 54

5555 56 56

5757

5858

5959

6060

6161

6262

6363

6464

6565 66 66

6767 68 68

6969 70 70

7171 72 72

7373 74 74

7575 76 76

7777 78 78

7979

8080

JP1


GND GND

3P3V

(J302)

3P3V

(J301)

VCLKP

GND

3P3V3P3V 3P3V

MilMax 852-10-80-10-001

NGCS5

BNWEBNOE

NRESET

NGCS0NGCS2NGCS4

Mouser 575-002101 (2x50 pins)

Mount Solder Side

NGCS[5:0]

NGCS1NGCS3

DB17DB19DB21DB23

DB27DB29

DB25

DB31

DB3DB1

DB6DB8

DB4

DB12DB14

DB2

DB10

DB0

DB7DB5

DB11DB13

DB9

DB15

DB30DB28

DB24DB26

DB22

DB16DB18DB20

DB[31:0]

AB6

AB2AB4

AB8

CSB

AB7AB5

AB9

1.27x1.27 ST HDR

MEMWAIT

NRESET

1 2 3 4

J12

CON4

BNWEBNOE

11 2 2

33 4 4

55 6 6

77 8 8

99 10 10

1111 12 12

1313

1414

1515

1616

1717

1818

1919

2020

2121 22 22

2323 24 24

2525 26 26

2727 28 28

2929 30 30

3131 32 32

3333 34 34

3535

3636

3737

3838

3939

4040

4141

4242

4343 44 44

4545 46 46

4747 48 48

4949 50 50

5151 52 52

5353 54 54

5555 56 56

5757

5858

5959

6060

6161

6262

6363

6464

6565 66 66

6767 68 68

6969 70 70

7171 72 72

7373 74 74

7575 76 76

7777 78 78

7979

8080

JP2


R7330603

R6330603

1 2 3 4

J13

CON4

CLK0CLK1

AB3

1 2 3

JC3CON3

1 2 3 JC1CON3

AB[9:0]

SDCLK

CDCLK

(J307)

1 2 3 4

J14

CON4

CCLKSCLK

3P3V 3P3V

3P3V

GND

MEMWAIT

R3330603

R533

0603

CLKOUT1

BINT18

BINT16

BINT6

GND

BINT7

BINT5

BINT9

BINT17

BINT8

R433

0603

CLKOUT0

1

GND1

1 2 3

JC2CON3

BUSCLK

INTRB

BIN

T5B

INT6

AB0

BIN

T7B

INT8

AB1

C4100805

GND

3P3V

3P3V

VCLK

BIN

T17

BIN

T16

BIN

T9

BIN

T18

GND

1

GND2

BUSCLK

NG

CS

1

CSB

NG

CS

4N

GC

S2

NG

CS

5

NG

CS

3N

GC

S0

AB[9:0]

DB[31:0]

1 2 3

JA3CON3

1 2 3

JA2CON3

1 2 3 JA1CON3

INTRB

C2100805

GND

C3100805

GND


Rev. 1.0 13

Figure 6: MICTOR Diagnostic Connectors Schematic

11

TP3NC1

GND3

CLKE5

D15E7

D14E9

D13E11

D12E13

D11E15

D10E17

D9E19

D8E21

D7E23

D6E25

D5E27

D4E29

D3E31

D2E33

D1E35

D0E37

NC 2

NC4

CLKO6

D15O8

D14O 10

D13O 12

D12O14

D11O16

D10O18

D9O 20

D8O 22

D7O24

D6O26

D5O28

D4O 30

D3O 32

D2O34

D1O36

D0O38

GN

D39

GN

D40

GN

D41

GN

D42

GN

D43

TP2

Mictor 38 Pin Connector

NC1

GND3

CLKE5

D15E7

D14E9

D13E11

D12E13

D11E15

D10E17

D9E19

D8E21

D7E23

D6E25

D5E27

D4E29

D3E31

D2E33

D1E35

D0E37

NC2

NC4

CLKO 6

D15O 8

D14O 10

D13O12

D12O14

D11O 16

D10O 18

D9O 20

D8O22

D7O24

D6O 26

D5O 28

D4O 30

D3O32

D2O34

D1O 36

D0O 38

GN

D39

GN

D40

GN

D41

GN

D42

GN

D43

TP5

Mictor 38 Pin Connector

11

TP6

BUSCLK

MEMWAITINTRBPMEB

NRESETCSBBNWEBNOE

AB[9:0]

DB[31:0]

AB[9:0]

GND

2-767004-2

2-767004-2

AMP

AMP

DB28

(LSB)

DB13

DB11

DB18

DB26DB25

DB27

DB29

DB17

DB4

DB24

DB15

DB12

DB9

DB7DB23DB22

DB8

DB21

DB3

(MSB)

DB6DB5

DB1

DB30

DB0

DB20

DB2DB19

DB31DB14

DB10

DB16

AB4AB5

BNWE

AB7

BUSCLK

AB8AB9

BNOE

NRESET

AB6

AB2CSB

AB3

MEMWAIT

PMEBINTRB

AB1AB0

TP26

TP55

DB[31:0]

GND

GND


14 Rev. 1.0

Figure 7: MAC Interface Schematic

R381K0603

R43330603

GND GNDGND GND

GND GND

GND

GND

BNOEBNWE

VC

C8

GN

D5

CLK2

CS1

DI3

DO4

NC1 7

NC2 6

U493LC46BSOIC8

3P3V

GND

PROMCLK

PROMDI

DB14

INTB

DB3

DB12

PROMCSDB4

DB7

DB1PROMDO

DB13

DB15

DB9

DB2

R5610K0603

DB5DB6

DB8

DB0

DB10

DB[31:0]

DB11

BUSCLK

(LSB)

INTRB

DB[31:0]

GND

PMEB

MEMWAIT

R42330603

3P3V

R52 33

TDI

CSB CSB

R53 33

3P3V

R551K0603

DATA0 28DATA1 29DATA2 30DATA3 31DATA432DATA5 33DATA638DATA7 39DATA840DATA9 41DATA1042DATA11 45DATA12 46DATA13 47DATA14 48DATA15 49DATA16 52DATA1753DATA18 54DATA1955DATA20 56DATA2157DATA22 58DATA2359DATA24 62DATA25 63DATA26 64DATA27 65DATA2866DATA29 67DATA3068DATA31 69

INTB 72

PMEB73

MEMWAIT 13

ADDR218 ADDR319 ADDR420 ADDR521 ADDR622 ADDR723 ADDR824 ADDR925

ADDR010 ADDR19

BUSCLK15

RESETB7

CSB16

WRB11

OEB12

ENDIAN079 ENDIAN180

BUSMODE83

WAITMODE84

CLKMODE85

BOOTSZ1100

BOOTSZ01

PROMCLK74

PROMCS75

PROMDO76

PROMDI77

TCLK6 TRST5 TMS3 TDO81 TDI4

GN

D1

2

GN

D2

14

GN

D3

34

GN

D4

35

GN

D5

26

GN

D6

43

GN

D7

50

GN

D8

60

GN

D9

70

GN

D11

78

VC

C1

8

VC

C2

17

VC

C3

36

VC

C4

27

VC

C5

37

VC

C6

44

VC

C7

51

VC

C8

71

VC

C9

61

VC

C11

82U2A78Q8430B-100

TDO

BUSCLK

R54 33R57 33

123

J15

CON3

R371K0603

C100.10603

C110.10603

C120.10603

C5100805

C90.10603

C6100805

C80.10603

C70.10603

INTRB

R13 33 0603

3P3V

DB16

R11 33 0603

R22 33 0603

DB30

DB25R15 33 0603

R17 33 0603DB21

DB23

R12 33 0603

R9 33 0603

R14 33 0603

3P3V

DB18

R8 33 0603

MEMWAIT

DB24

DB28

DB17

R20 33 0603

R10 33 0603

R23 33 0603

(MSB)

BNOEBNWE

NRESET

R18 33 0603

R21 33 0603

TMS

DB22

R19 33 0603

DB31

DB26

R16 33 0603

DB27

DB29

DB19DB20R58 33

AB6

AB0

AB7

AB9

AB3AB2

AB5

AB8

AB4

AB[9:0]AB[9:0]

AB1

TRST

R59 33

NRESET

3P3V

R60 33

TCLK

R61 33

R24 33 0603R25 33 0603

R27 33 0603R26 33 0603

R28 33 0603R29 33 0603

R31 33 0603R30 33 0603

R62 33

GND

12345678910

J1

CON10

R32 33 0603R33 33 0603

TMS

TRST

TDI

TCLK

R35 33 0603

TDO

R34 33 0603

GND

R4410K0603

R4510K0603

R36 33 0603R39 33 0603

R41 33 0603R40 33 0603

DATA29

DATA31DATA30

DATA28

DATA25DATA26

DATA22

DATA27

DATA23DATA24

DATA18DATA19

DATA17

DATA21DATA20

DATA15

DATA13

DATA16

DATA14

DATA12DATA11

DATA6

DATA9

DATA7

DATA10

DATA8

DATA5

DATA2DATA1

DATA4DATA3

DATA0

R63 33

R64 33R65 33

3P3V

R66 33

PMEB


Rev. 1.0 15

Figure 8: PHY Interface Schematic

CGND

XTLN

XTLP

GND GND

TXP97

TXN98

RXP94

RXN93

XTLP87

XTLN88

VC

CA

186

VC

CA

295

VC

CA

396

GN

DA

189

GN

DA

291

GN

DA

399

LED192

LED090

U2B78Q8430B-100

GND

ACTIVE

LINK

RX/TX

Link

Gnd pins 2 and 4

Pulse Engr

TXOP

TXON

Use Zero Ohm ResistorGNDGND

RXIP

RXIN

CGND

C13100805

VCCA

GND

R516800603

R466800603

R4949.91%0603

C1927PF0603

1 3Y1

25.000MHZ50ppmRaltronL11B

R5049.91%0603

C17100805

R4749.91%0603

L1

FERRITER_0805

C160.10603

C1827PF0603

R4849.91%0603

C150.10603

C140.10603

3P3V

3P3V

3P3V

GND

3P3V

GND

8

1234567

1314

910

1112

23

24

RALEDRCLED

TD+TD-TDCTCGND1CGND2RDCTRD+RD-

LCLEDLALED

CGND3

CGND4J2

J0011F01P TabUp


16 Rev. 1.0

Table 2: 78Q8430 Embest Evaluation Board Bill of Materials

Item Quantity Reference Part PCB Footprint

Part Number Vendor

1 2 C18,C19 CAP., 27pF, 50V C_0603 C1608C0G1H270J TDK 2 9 C7-C12,C14-C16 CAP., 0.1uF,16V C_0603 ECJ-1VB1E104K Panasonic

3 7 C2-C6,C13,C17 CAP.,10uF,10V C_0805 GRM21BR61A106KE19L Murata

4 2 TP3,TP6 CON1 Testpoint 5011 Keystone

5 7 JA1-JA3,JC1-JC3, J15 SIP3 SIP\3P PBC03SAAN

Sullins Electronics Corp

6 3 J12,J13,J14 SIP4 SIP\4P PBC04SAAN Sullins Electronics Corp

7 1 J1 CON10 SIP\10P PBC10SAAN Sullins Electronics Corp

8 3 JP1-JP3 40-Pin Header EBS40X2 852-10-100-10-001000 Mill Max

9 1 J2 Integrated RJ45 RJ45-INT J1011F01P Pulse Eng 10 1 Y1 25MHz Crystal XTAL-SMD ABMM-25MHz Abracon 11 1 L1 Ferrite Bead L_0805 MMZ2012S181A TDK 12 3 R44,R45,R56 RES, 10k, 5% R_0603 ERJ-3GEYJ103V Panasonic 13 3 R37,R38,R55 RES, 1k, 1% R_0603 ERJ-EEKF1001V Panasonic 14 4 R47-R50 RES, 49.9, 1% R_0603 ERJ-3EKF49R9V Panasonic

15 52 R3-R36,R39-R43, R52,R53,R54, R57-R66

RES, 33, 5% R_0603 ERJ-3GEYJ330V Panasonic

16 2 R46,R51 RES, 680, 5% R_0603 ERJ-3GEYJ681V Panasonic 17 2 TP2,TP5 Mictor 38-pin MICTOR 2-767004-2 Tyco 18 1 L1 Ferrite Bead L_0805 MMZ2012S181A TDK

19 1 U2 78Q8430 100 LQFP 78Q8430 Teridian Semiconductor

20 1 U4 93LC46 SOIC8 93LC46BT-I/SN Microchip


Rev. 1.0 17

Figure 9: Top Silkscreen Layout

Figure 10: Top Layer Layout


18 Rev. 1.0

Figure 11: VCC Layer Layout

Figure 12: Ground Layer Layout


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Figure 13: Bottom Layer Layout

Figure 14: Bottom Silkscreen Layout


20 Rev. 1.0

4 Ordering Information Table 3 lists the order number for the 78Q8430 Embest Evaluation Board.

Table 3: Order Number and Part Description

Part Description Order Number 78Q8430 Embest Evaluation Board (D8430T3A_EB) EVM8430-ARM9

5 Related Documentation The following 78Q8430 documents are available from Teridian Semiconductor Corporation: 78Q8430 Preliminary Data Sheet 78Q8430 Layout Guidelines 78Q8430 Software Driver Development Guidelines 78Q8430 Driver Guide for ST 5100/OS-20 with NexGen TCP/IP Stack 78Q8430 STEM Demo Board User Manual 78Q8430 Driver Guide for ARM920T Linux 78Q8430 ARM9(920T) Embest Evaluation Board User Manual 78Q8430 ARM9(920T) Linux Driver Diagnostic Guide 6 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 78Q8430, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800

FAX: (714) 508-8878 Email: [email protected] For a complete list of worldwide sales offices, go to http://www.teridian.com.

http://www.teridian.com/


Rev. 1.0 21

Revision History Revision Date Description 1.0 May 6, 2008 First Publication

78Q8430 ARM9 (920T) Embest Evaluation Board User Manual

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