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Design of an OTA-Miller for a 96dB SNR SCMulti-bit Sigma-Delta modulator based on

methodology

Heiner Alarcon Cubas and Joao NavarroEngineering School of Sao Carlos, USP.

Email: heiner.alarcon@usp.br, navarro@sc.usp.brLSITEC-Sao Paulo

Email: heiner.alarcon@lsitec.org.br

Abstract This paper presents the design of an OTA-Milleramplifier of the first integrator of a Switched-Capacitor Multi-bit Sigma-Delta Modulator. The first integrator OTA is themost critical block in Sigma-Delta Modulator due to the highbandwidth, high Slew Rate and low noise requirements. Thefirst integrator OTA specifications are obtained from the Sigma-Delta Modulator designing for low power consumption. Thegm/ID methodology is used on the OTA design of the firstintegrator to reduce the power consumption. This methodologyis also applied in the other OTAs of the Sigma-Delta Modulator.The Chopper technique is also implemented to reduce the inputreferred noise of the first integrator. The SDM with the designedOTAs using the gm/ID methodology is simulated by the Spectresimulator. Implemented in 018 CMOS technology, the SDMachieves a 96 dB SNR for 20 kHz signal bandwidth and a powerconsumption of 277 mW for a 18 V supply.

Keywords:, Sigma-Delta Modulator, Audio, Multi-bit,low power.

I. INTRODUCTION

Currently, the request for portable audio commercial sys-

tems as phone-mobiles, high quality audio devices and hear-

ing systems is increasing the demand for low-power data-

converters. Audio signals are in the range of20 Hz to20 kHzand, generally, audio digital systems requires converters with

high resolution and low distortion. For this purpose, Sigma-

Delta A/D converters, which reachs high resolution with the

low power consumption, are the best choise.

The Sigma Delta Modulator (SDM) is the most important

part in the Sigma-Delta Converter, because it increases the

converter resolution in-band applying oversampling and noise-

shaping techniques [1]. SDMs can be implemented with

Switched Capacitors (SC) and Continuous Time (CT) struc-tures. For this work a SC structure is chosen due to the high

precision in the coefficients implementation. The most power

hungry block in a SDMs is the first integrator OTA (OTA 1),because it needs to be designed to drive high load capacitance,

to present low noise and high product gain-bandwidth ().The Miller architecture is chosen to implement the OTA 1.

In this work, a methodology design for the OTA 1 of aThird-order Four-bit CIFF (Cascade of Integrators Feedback

Form) SDM is presented. In section II, the SDM circuit is

presented. In section III, the OTA1specifications are obtained.In section IV the OTA1design is developed. Finally in sectionV and VI, the results of the OTA 1 and the Sigma-Deltamodulator and the conclusions are presented respectively.

II. SDM CIRCUIT I MPLEMENTATION

The Third-order Four-bit CIFF SDM shown in the figure 1 is

composed by three SC integrators, a capacitive resettable ana-

log adder with offset cancellation, a four bits flash quantizer,

and a four bits weighted-DAC. The OTA amplifiers are applied

in the three DC integrators (OTA 1, OTA 2 and OTA 3) and in

the analog adder (OTA 4). Two chopper modulators are added

at the first integrator to reduce the in-band flicker noise [2].

A Fully differential structure is selected to reduce the charge

injection generated by the switches and to increase the input

value range and the PSRR [3]. A bottom plate technique [1]

is also implemented to reduce the parasitic switch capacitanceerror. The switches are implemented with carefully designed

transmission gates to reduce the charge injection and time

constant.

III. OTA 1 SPECIFICATIONS

The input OTA specifications are obtained from the SDM

system design. The SDM is designed for high SNR (about

96 dB), so it is necessary to establish the noise budget ofthe system. The noise sources can be divided in internal

and external sources. The internal sources are due to the

quantization noise (), the KT/C noise, the intrisic noise ofthe OTAs, and the DAC non linearity (). The external

sources () are due to the references noise and power supplynoise. The sum of all noise source contributions must be less

or equal than the required noise to get the specified SNR.

Hence, the relation in equation 1 must be fulfilled[4].

10102 2

+ 2

+ 2

+ 2

(1)

In equation 1, is the maximum allowed inputsignal RMS and is the sum of the intrisic RMS noise ofthe OTAs and KT/C RMS noise. As the determines the

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Fig. 1. Third-order Four-bit SDM

SDM power consumption, it is assumed that contribuits to80% of the total noise. The , and the contribuit

to 1%, 9% and 10%, respectively [4]. For is possible todetermine the SQNR=20()=116dB. For thisSQNR can be demonstrated that it is necessary an OSR of

48 [4]. Thus, the sampling frequency () should be equal to2 MHz for a bandwidth slightly greater than 20 kHz. Usingthe found OSR and the modulator order (L), the modulator

coefficients can be obtained using the Matlab SDM toolbox

[5]. These coefficients are listed in the table I.

TABLE I

SDM COEFFICIENTS

3 2 1 1 2 3 4 1 2 334 24 07 08 0 0 1 08 14 11

The coefficients are scaled to limit the output swing to 20%of the full-scale at each output integrator and are rationalized

to implement the capacitance feedback of each integrator [4]

[5].The first integrator has the greatest noise contribution, so

it is fixed as 21 = 092

. The input referred noise of the

OTA 1 is fixed in 10%21, because of the used Chopper tech-nique. The first integrator noise can be expressed as4(12)[4], where C2 is the integration capacitanceof the first stage.

The OTA non-idealities are commanded by the finite DC

gain (), the finite gain-bandwidth (), the finite SlewRate (), and the input referred noise. The finite DC gaincan modify the transfer function (), shifting to the rightthe cut-off frequency. This shift may increase the noise floor

in signal band [6]. Hence, a higher value of is desirable.The and act during the integration phase [5]. For

this design the region holds a third part of the integrationphase, then = (6). is the maximumoutput value peak to peak of the integrator and is theoversampling period.

The remaining time of the integration phase is taken by the

settling time, then = (())(23) [4], where

is the settling error and is the feedback factor of theintegrator. To accomplish the specified, the settling error

is fixed in 106

for the OTA 1. The factor is equal to1(1 + ), being a SDM coefficient.An important parameter on the OTA 1 design is the output

load capacitance, . It is obtained in the integration phase(OTA 1 working) of the SC integrator and it can be approxi-

mate to the equation 2 [1].

= 2(21+ )

2+ 21+ (2)

whereis the OTA1input capacitance. The specificationsfor the RMS input referred noise (),2,,,and for the OTA 1 are listed in the table II.

TABLE IISUMMARIZED DESIGNOTA 1 SPECIFICATIONS

2 222 20 40 73 185 10 45

IV. LOWP OWER DESIGN FOR THEOTA1

A. Methodology

The OTA 1 is designed using the methodology.In this methodology the design parameters are expressed in

function of [7]. The parameter varies between0 and 30 (figure 2), depending on the inversion region. The

conduction operation of a transistor can be divided in threeapproximate regions, weak, moderate, and strong inversion

(figure 2).

The is extracted from simulations of the MOStransistors varying andbetween 0 and 1 8 [7].

B. OTA Miller design

The fully differential OTA Miller architecture shown in

figure 3 is chosen for the four OTAs of the SDM. The

advantages of this architecture are the high DC gain, low noise

and low power consumption [3]. The first stage of the OTA is

a differential pair and the second stage is a common source

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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80

5

10

15

20

25

30

35

VGS[V]

gm/Id

TypeN

TypePWeakInversion

ModerateInversion

StrongInversion

Fig. 2. vs for each transistor in the three inversion regionsfor= 420 and= 355

amplifier. To increase the Common Mode Gain it is used two

CMFB (Common Mode Feedback). A SC symmetrical load

architecture is applied for the two CMFBs. This architecturestabilizes faster than traditional SC-CMFBs.

Fig. 3. Fully Differential Two Stage OTA including CMFB

Most of the current consumption is due to the second stagecurrent,7 (shown in figure 3). This current can be expressedin function of77, , and the second dominant pole,2, as can be seen in the equation 3.

7 = 2(77)

(3)

The Phase Margin (PM) depends on the 2 and can beexpressed by the equation 4.

=90 1(2

) (4)

PM must be designed for 85 to assure stability, so must be at least ten times 2. From equation 3 and 4 we canbuilt the figure 4 curves of7 vs 77.

0 5 10 15 20 25 300

1

2

3

4

5

6

7x 10

3

gm7/I

D7

ID7

(A)

Fig. 4. 7 vs 77 for the OTA1

From figure 4 it can be deduced that it is necessary high

values of77 (weak inversion) to reduce7. However,high77designing implies in huge transistor dimensionsand, consequently, in large output capacitance. For this reason,

the value of77 is conveniently adjusted. The 3 and4 transistors are designed for the same inversion region ofthe 7 transistor to ensure low systematic offset [1].

In order to reduce the power consumption without increase

the current mismatch, it is necessary a current copy factor of3as maximum in the current mirrors. For minimize the current

consumption, the following relation is assumed.

7 = 35 = 61 (5)

where 1 is the differential pair current and 5 is thecurrent of the transistor 5. The compensation capacitancecan be obtained from the equation 6.

=21

(6)

The current 1 can also be expressed in function ofand 11 as it is shown in the equation 7 [1].

1 =211

(7)

To define the inversion region of 1, the parameter11 is varied between 0 and 30 in the equation 7. Theformer curve is compared with the obtained current (1 =76) being both curves shown in the figure 5.

From the figure 5 we can deduce that 11 shouldnot be greater than 20, because 1 would be less than thespecified current by 5. Finally,5,6 and9 transistors aredesigned in strong inversion reducing the mismatch between

current mirrors.

The values of 11, 5, , 7 and 77 forthe OTA 1 are summarized in the table III.

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0 5 10 15 20 25 300

0.2

0.4

0.6

0.8

1

1.2

1.4x 10

3

gm1/ID1

Id1(A)

ID7

/6

fta=7,3MHz

Fig. 5. 1 for fixed of 1 in function of 11

TABLE III

SUMMARIZED DESIGN RESULTS FOR THEOTA1

11 5 7 77 1 20 120 20 360 20

V. RESULTS

The shown in the figure 1 was designed using the018m CMOS7RF CMOS technology of IBM. The powersupply is18and the maximum input is1 (50%of FullScale). The input OTA results listed in the table IV, including

input referred offset () and the OTA 1 total current (),are obtained using the Spectre simulator.

TABLE IV

SUMMARIZED RESULTS FOR THE OTA1

OTA 1 62dB 8.2MHz 6.2V/ s 3.5mV 2.22V 968A

The other OTAs and blocks of the SDM are designed by

following a similar methodology. The SNR of the SDM is

measured from the transient simulation of the circuit of the

figure 1. The modulator input referred noise is generated from

the PSD simulated using the method shown in [8]. The SNR

is simulated using a test frequency of683. In the figure6 are shown the frequency response of the SDM and the input

referred noise PSD simulated using Spectre-RF.

The performance of the modulator is summarized in table

V and compared with low Power SDM for low power appli-

cations published in recent years.

TABLE V

COMPARISON OF THE PUBLISHED WORKS

[9] [10] [11] [] 93 838 92 96

[] 1849 181 045 102[] 135 11 06 277

[] 018 018 018 018 [] 15 1 18

[] 10 24 24 20

101

102

103

104

105

106

160

140

120

100

80

60

40

20

0

Amplitude[dB]

Frequency[Hz]

SDM Output Spectrum

Input Referred Noise PSD

Fig. 6. Output SDM frequency response compared with the input referredPSD noise

VI. CONCLUSIONS

A methodology to design low power SDM inputOTA was described. The merit of this OTA was verified by

simulating third order four bits SDM. The low power in

the OTAs are achieved designing the output source common

transistors in weak inversion.

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