7/13/2015 SENIOR PROJECT STUDENT:RICARDO V. GONZALEZ. ADVISOR: VINOD B. PRASAD.

04/19/23

SENIOR PROJECT

STUDENT:RICARDO V. GONZALEZ.

ADVISOR: VINOD B. PRASAD

04/19/23

DATA MOVER IN VLSIUSING L-EDIT

TESTED IN DIFFERENT CAD FOR FUNCTIONALITY ASSURANCE

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DATA MOVER IN VLSIUSING L-EDIT

WHAT IS VSLI?

- VSLI IS THE TECHNOLOGY THAT ALLOWS COMPANIES TO CREATE THEIR OWN CUSTOM MADE IC CHIPS.- VSLI CAN REDUCE THE SIZE OF THEIR ELECTRONIC DESIGNS.- THE CONTINUOUS USE OF IC FABRICATION TECHNOLOGY WILL LOWER THE PRODUCTION COST OF COMPLICATED DESIGNS

04/19/23

DATA MOVER IN VLSIRICARDO V. GONZALEZ. ADVISOR: VINOD B. PRASAD

OBJECTIVE

The main objective was to acquire experience in asic design building a data mover with testable features to transfer data from the input to the output following a geometric algorithm. This type of design will require the use of CMOS technology and logic gate design to be fabricated into a chip

WHY USE L-EDIT?

YOU CAN TEST YOUR CIRCUIT BEFORE IMPLEMENTING IT IN L-EDIT.

L-EDIT EXTRACTS THE NECESSARY CODE TO SIMULATE CIRCUITRY IN PSPICE

THE CIRCUIT IN L-EDIT IS THE FINAL LAYOUT THAT IS SENT FOR FABRICATION

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TABLE OF CONTENT

Block diagram Design equationsTwo bit example of a data moverTiming control neededTiming chart

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TABLE OF CONTENT

Designs in LogicWorksDesigns in L-EDITSimulations in PspiceFinal Layout

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BLOCK DIAGRAM

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DESIGN EQUATIONS

[FROM RTL LANGUAGE (REGISTER TRANSFER LOGIC)]Data mover:Memory a[2]; b[2]; c[2]. Inputs: x[2]Outputs: z[2]1 a x2 c /a3 b c[0], c[1]4 c a v b5 z = c


ALGORITHM OF THE DATA MOVER FOR TWO BITS


TIMING CONTROLLED NEEDED


CONTROL CIRCUIT


SIMULATION OF THE CONTROLLER CIRCUIT

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FINAL SIMULATION OF THE CONTROLLER CIRCUIT

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CONTROLLER CIRCUIT DESIGNED IN L-EDIT

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CONTROLLER SIMULATION IN PSPICE

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ALGORITHM OF THE DATA MOVER

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THE DATA MOVER

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ALGORITHM OF THE DATA MOVERIN L-EDIT

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SIMULATION OF DATA MOVER IN PSPICE TWO BITS

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ANOTHER SIMULATION OF DATA MOVER IN PSPICE TWO BITS

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D FLIP FLOP DESIGNED IN L-EDIT

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D FLIP FLOP SIMULATED IN PSPICE

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DATA MOVER COMPONENTS

AND GATE

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PSPICE SIMULATION OF THE AND GATE

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FOUR BIT DATA MOVER

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FINAL APPEARANCE OF THE PROJECT IN DESING PAD

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FOUR BIT SIMULATION OF DATA MOVER IN PSPICE


PROBLEMS ENCOUNTERED

CONTROLLER CIRCUIT NEEDED THE CLOCK ‘S RISING AND FALLING EDGE

D FLIP-FLOP HAD TO BE DESIGNED THE SMALLEST POSSIBLE TO REDUCED SPACE

PSPICE SIMULATION FILES WERE VERY LARGE AND NEEDED MANY CAPACITORS

WE HAD TO CHANGE THE DESIGN RULES IN THE DESIGN TO ADAPT IT TO A NEW TECHNOLOGY


ACCOMPLISHMENTS

I GOT INTRODUCED TO SEVERAL POWERFUL COMPUTER SOFTWARE THAT CAN SOLVE INDUSTRY PROBLEMS

A GREATER KNOWLEDGE WAS ACHIVED MANIPULATING LOGICWORKS, PSPICE, L-EDIT AND XILINX (VHDL)

I FEEL MORE CONFIDENT TO EXPLORE DIFFERENT FEATURES OF THESE SOFTWARE TO SOLVE PROBLEMS

I GAINED MUCH EXPERIENCE THAT IS REQUIRED IN THE INDUSTRY


RECOMMENDATIONS

TEST FEASIBILITY OF DESIGN EQUATIONS SYSTEM DESIGN IN LOGICWORKS AT

GATE LEVEL SYSTEM DESIGN AT TRANSISTOR LEVEL

IN LEDIT PSPICE SIMULATION OF TRANSISTOR

LEVEL PLACE IN DESIGN PAD FOR FINAL

FABRICATION


AFTERMATH

THE TOTAL AMOUNT OF TRANSISTORS WAS OVER SIX THOUSAND

THE AMOUNT OF LINES OF PSPICE CODE WAS OVER FIVE HUNDRED LINES

IT TOOK THREE HUNDRED AND FIFTY LINES OF VHDL CODE TO GENERATE A DATA MOVER OF TWO BITS

TIME CONSUMED WAS ABOUT 200 HOURS OF DESIGN AND PROGRAMING FROM HALF OF LAST SEMESTER AND LAST SENIOR SEMESTER


QUESTIONS?

7/13/2015 SENIOR PROJECT STUDENT:RICARDO V. GONZALEZ. ADVISOR: VINOD B. PRASAD.

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Transcript of 7/13/2015 SENIOR PROJECT STUDENT:RICARDO V. GONZALEZ. ADVISOR: VINOD B. PRASAD.