7 Main Memory

8/22/2019 7 Main Memory

1/30

Main MemoryMain Memory

ByProf. Dr. Shaiq A. Haq

Air University, E-9, Islamabad


2/30

Scheme of PresentationScheme of Presentation

Overview of Main Memory SRAM, DRAM

64MB DRAM Logical Organization Improved Architectures of DRAM for

Performance Enhancement

SDRAM (Synchronous DRAM)

RDRAM (Rambus DRAM)

DDR (Double Data Rate DRAM) Memory Interfacing

Cache Memory


3/30

Memory HierarchyMemory HierarchyRegs

L2 Cache

Main Memory

Disk

Tape

Instructions, Operands

Blocks

Pages

Files

Upper Level

Lower Level

Faster

Larger

L1 Cache

Blocks{

Virtual

Memory{

Inside CPU


4/30

Main Memory BackgroundMain Memory Background Next level down in the hierarchy

satisfies the demands of caches + serves as the I/O interface

Performance of Main Memory:

Latency: Cache Miss Penalty Access Time: time between when a read is requested and

when the desired word arrives

Cycle Time: minimum time between requests to memory

Bandwidth (the number of bytes read or written per unit time):I/O & Large Block Miss Penalty (L2)

Main Memory is DRAM: Dynamic Random Access Memory Dynamic since needs to be refreshed periodically (8 ms, 1% time)

Addresses divided into 2 halves (Memory as a 2D matrix):

RAS orRow Access Strobe + CAS orColumn Access Strobe

Cache uses SRAM: Static Random Access Memory

No refresh (6 transistors/bit vs. 1 transistor)


5/30

Memory Background:Memory Background: Static RAM (SRAM)Static RAM (SRAM)

Six transistors in cross connected fashion

Provides regular AND inverted outputs

Implemented in CMOS process

Single Port 6-T SRAM Cell


6/30

SRAM cells exhibit high speed/poor density

DRAM: simple transistor/capacitor pairs in high

density form

Memory Background:Memory Background: Dynamic RAM(DRAM)Dynamic RAM(DRAM)

Word Line

Bit Line

C

Sense Amp

.

.

.


7/30

Static RAMStatic RAM

Bits stored as on/off switches, uses digital flip-flops

No charges to leak

No refreshing needed when powered

More complex construction

Larger per bit More expensive

Does not need refresh circuits

Faster

Cache


8/30

Dynamic RAMDynamic RAM

Bits stored as charge in capacitors

Essentially analogue

Level of charge determines value

Charges leak

Need refreshing even when powered

Simpler construction Smaller per bit

Less expensive

Need refresh circuits

Slower

Main memory


9/30

SRAM v DRAMSRAM v DRAM

Both volatile

Power needed to preserve data

Dynamic cell Simpler to build, smaller

More dense

Less expensive Needs refresh

Larger memory units

Static Faster

Cache


10/30

Types of Read Only Memory (ROM)Types of Read Only Memory (ROM)

Written once, during manufacture

Very expensive for small runs

Programmable (once) PROM Needs special equipment to program

Read mostly Erasable Programmable (EPROM)

Erased by UV

Electrically Erasable (EEPROM) Takes much longer to write than read

Flash memory Erase whole memory electrically


11/30

DRAM logical organization (64DRAM logical organization (64 MbitMbit))

Square root of bits per RAS/CAS


12/30

Typical 16 Mb DRAM (4M x 4)Typical 16 Mb DRAM (4M x 4)


13/30

PackagingPackaging


14/30

Memory Interfacing CircuitMemory Interfacing Circuit


15/30

Enhanced DRAM (EDRAM)

EDRAM includes a small amount of Static

RAM inside a large amount of DRAM to

act as cache memory for storing columnaddress or row address. An older product

from Enhanced Memory Systems, inc.

EDRAM was also made by RAMTRON. It

is also known as Cache DRAM. CDRAM

was developed by Mitsubishi. Also known as Fast Page Mode DRAM.


16/30

Synchronous DRAM (SDRAM)Synchronous DRAM (SDRAM)

Access is synchronized with an external clock

Address is presented to RAM

RAM finds data (CPU waits in conventionalDRAM)

Since SDRAM moves data in time with system

clock, CPU knows when data will be ready CPU does not have to wait, it can do something

else

Burst mode allows SDRAM to set up stream ofdata and fire it out in block

DDR-SDRAM sends data twice per clock cycle(leading & trailing edge)


17/30

IBM 64Mb SDRAMIBM 64Mb SDRAM


18/30

Improving Memory Performance inImproving Memory Performance in

Standard DRAM Chips (contStandard DRAM Chips (contd)d) Synchronous DRAM add a clock signal to the DRAM interface

DDR Double Data Rate

transfer data on both the rising and falling edge of the

clock signal


19/30

Improving Memory Performance via aImproving Memory Performance via a

New DRAM Interface: RAMBUSNew DRAM Interface: RAMBUS (cont(contd)d) RAMBUS provides a new interface

memory chip now acts more like a system

First generation: RDRAM

Protocol based RAM w/ narrow (16-bit) bus

High clock rate (400 Mhz), but long latency Pipelined operation

Multiple arrays w/ data transferred on both

edges of clock

Second generation: direct RDRAM

(DRDRAM) offers up to 1.6 GB/s


20/30

RAMBUS (contRAMBUS (contd)d)

Adopted by Intel for Pentium & Itanium

Main competitor to SDRAM

Vertical package all pins on one side

Data exchange over 28 wires < cm long

Bus addresses up to 320 RDRAM chips at1.6Gbps

Asynchronous block protocol 480ns access time

Then 1.6 Gbps

i f iI i M P f i


21/30

Improving Memory Performance viaImproving Memory Performance via

a New DRAM Interface: RAMBUSa New DRAM Interface: RAMBUS

RDRAM Memory System

RAMBUS Bank


22/30

Summary of Memory TypesSummary of Memory Types FPM DRAM; Fast page mode dynamic random access

memory was the original form of DRAM. Uses a SRAM asCache to store page or column address.

EDO DRAM; Extended data-out dynamic random access

memory does not wait for all of the processing of the first bitbefore continuing to the next one. As soon as the address ofthe first bit is located, EDO DRAM begins looking for thenext bit. It is about five percent faster than FPM. Optimized

for 66MHz Pentium. Maximum transfer rate to L2 cache isapproximately 264 MBps.

SDRAM; Synchronous dynamic random access memorytakes advantage of the burst mode concept to greatlyimprove performance. It does this by staying on the rowcontaining the requested bit and moving rapidly through thecolumns, reading each bit as it goes. The idea is that most ofthe time the data needed by the CPU will be in sequence.SDRAM is about five percent faster than EDO RAM and is

the most common form in desktops today. Maximumtransfer rate to L2 cache is approximately 528 MBps.


23/30

Summary of Memory Types (contSummary of Memory Types (contd)d)

DDR SDRAM; Double data rate synchronous dynamic RAM isjust like SDRAM except that is has higher bandwidth, meaninggreater speed. Maximum transfer rate to L2 cache isapproximately 1,064 MBps (for DDR SDRAM 133 MHZ).

RDRAM; Rambus dynamic random access memory is a radicaldeparture from the previous DRAM architecture. Designed byRambus, RDRAM uses a Rambus in-line memory module(RIMM), which is similar in size and pin configuration to a

standard DIMM. What makes RDRAM so different is its use of aspecial high-speed data bus called the Rambus channel. RDRAMmemory chips work in parallel to achieve a data rate of 800 MHz,or 1,600 MBps. Since they operate at such high speeds, they

generate much more heat than other types of chips. To helpdissipate the excess heat Rambus chips are fitted with a heatspreader, which looks like a long thin wafer. Just like there aresmaller versions of DIMMs, there are also SO-RIMMs, designedfor notebook computers.


24/30

Summary of Memory Types (contSummary of Memory Types (contd)d)

FLASH MEMORY; Flash memory is a solid-state, non-volatile,

rewritable memory that functions like RAM and a hard disk drive

combined. Flash memory stores bits of electronic data in memory

cells, just like DRAM, but it also works like a hard-disk drive in

that when the power is turned off, the data remains in memory.

Flash memory is a type of EEPROM chip. Because of its high

speed, durability, and low voltage requirements, flash memory is

ideal for use in many applications - such as digital cameras, cellphones, printers, handheld computers, pagers, and audio

recorders. Flash memory is avaliable in many different form

factors, including: CompactFlash, Secure Digital, SmartMedia,

MultiMedia and USB Memory. SIMM is an acronym for Single Inline Memory Module

DIMM is an acronym for Dual Inline Memory Module.

RIMM is an acronym for Rambus Inline Memory Module

L l f h M Hi hL l f th M Hi h


25/30

Levels of the Memory HierarchyLevels of the Memory Hierarchy

CPU Registers100s Bytes


26/30

ProcessorProcessor--DRAM Speed GapDRAM Speed Gap

1

10

100

1000

1980

1981

1982

1983

1984

1985

1986

1987

1988

1989

1990

1991

1992

1993

1994

1995

1996

1997

1998

1999

2000

DRAM

CPU

Processor:

2x/1.5 year

Perfo

rmance

Time

Memory:

2x/10 years

Processor-Memory

Performance Gapgrows 50% / year


27/30

Why hierarchy works?Why hierarchy works?

Principal of locality

Temporal locality: recently accessed items

are likely to be accessed in the near future Keep them close to the processor

Spatial locality: items whose addresses

are near one another tend to be referencedclose together in timeMove blocks consisted of contiguous words

to the upper level

Rule of thumb:

Programs spend

90% of their

execution time in

only 10% of code

Address space

Probability

of reference


28/30

Why Virtual Memory?Why Virtual Memory?

Today computers run multiple processes,

each with its own address space

Too expensive to dedicate a full-address-spaceworth of memory for each process

Principle of Locality

allows caches to offer speed of cache memory

with size of DRAM memory

DRAM can act as a cache for secondary storage

(disk) Virtual Memory

Virtual memory divides physical memory into

blocks and allocate them to different processes


29/30

Virtual MemoryVirtual Memory MotivationMotivation

Historically virtual memory was invented whenprograms became too large for physical memory

Allows OS to share memory and protect programsfrom each other (main reason today)

Provides illusion of very large memory

sum of the memory of many jobsgreater than physical memory

allows each job to exceed the size of physical mem.

Allows available physical memoryto be very well utilized

Exploits memory hierarchy

to keep average access time low

i i l h i lM i Vi l Ph i l M


30/30

Mapping Virtual to Physical MemoryMapping Virtual to Physical Memory

Program with 4 pages (A, B, C, D)

Any chunk of Virtual Memory assignedto any chuck of Physical Memory (page)

Physical MemoryVirtual Memory

A

B

C

D

D

A

B

C

0

4 KB

8 KB

12 KB

0

4 KB

8 KB

12 KB

16 KB

20 KB

24 KB

28 KB

Disk

7 Main Memory

Documents

Transcript of 7 Main Memory